JPH0429991B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to an operational function test of an IC memory element constituted by a semiconductor integrated circuit (IC), and in particular to a test device for writing/reading a static RAMIC memory. Regarding improvements.

(b) Technology background As for IC memory, the capacity of IC memory is increasing with the development of semiconductor technology, especially integration technology. As a result, the number of man-hours required to test the operation and functionality of IC memory increases, so a test method that is as efficient as possible is required.

(c) Prior art and problems Conventional operational function tests on IC memories are performed to ensure normal operation within the specified operating range of the IC memory. Figure and second
This will be explained with reference to the time chart shown in the figure. In the figure, 1 is the tester, 2 is the IC memory element to be tested, and 3 is the address Aφ~n, chip select, write enable, out enable.
This is an input/output signal line consisting of OE and data input/output I/O1 to p.

In FIG. 2, a is a clock signal, b is an address signal, c is a signal, d is a signal, e is input data, f is a signal, and g is output data.

In the figure, to indicates one cycle, and as an example, 250ns.
It is.

In the conventional test method, each Aφ to n of the IC memory element 2 is accessed from the tester 1 via the connection line 3, and each control signal of and I/O1 is accessed from the tester 1 through the connection line 3.
~p writes a certain data pattern and reads it out in the next cycle. In the write/read test (WR test), the tester 1 sends the original input data written to the IC memory element 2 to the tester 1 via the connection line 3 from I/O1 to p, and outputs the original input data written to the IC memory element 2 as a read signal. Normal operation was determined by checking the data and finding a match between the two data. However, the IC memory element 2 has a rare defect in the memory cell (not shown) that makes up the memory cell, and the transistor elements that make up the memory cell are unbalanced, making it easy for data to be retained in one direction. There are cases where there is a bad part or an address malfunction. In this way, IC memory elements that have internal memory cells with weak memory retention capacity have defects that are difficult to detect using the conventional WR test method, but they pass as non-defective products using the normal test method and cannot be incorporated into equipment. This had the drawback of causing intermittent errors later on. In printed wiring boards and devices equipped with IC memory elements, this may vary slightly depending on the delay time difference (difference in the number of logic circuit stages) of the input signal system applied to the IC memory element, or the mounting and mounting position of each input signal. Since there is a large difference in delay time, various skews occur in each input signal.
However, in conventional IC memory testing equipment, each input signal is applied at a fixed timing, and the tester 1 is adjusted to minimize skew as much as possible, making it difficult to detect malfunctions caused by skew between input signals. It was difficult, but as IC memory becomes denser and faster, IC memory tends to cause errors due to skew, and IC
It is desirable to strengthen testing methods for memory skew.

(d) Object of the invention In order to eliminate the above-mentioned drawbacks, the object of the present invention is to include all combinations of input signals from the tester in the IC memory of the device under test in the same cycle as the conventional test cycle. The present invention aims to provide an IC memory testing device that is capable of applying arbitrary synchronous skew.

(e) Structure of the invention The object is to continuously connect an asynchronous oscillator having a frequency faster than the repetition period of a clock signal of a tester, and a plurality of flip-flops, and to synchronize the oscillation frequency with the clock signal for one cycle and/or multiple cycles. a plurality of delay signal generating means having delay times in increments;
means for generating p sets of q-bit variable strings obtained by arbitrarily combining m×n-bit output signals from sets of m-bit counters; p selector means for selecting the delayed signals according to the q-bit variable strings; and a plurality of flip-flops for switching input signals such as address, data input, and chip select to be sent from the tester to the IC memory of the test device according to the output signal of the selector. An IC characterized in that the delayed signal is selected for each signal according to the combination of output signals of the variable sequence generating means, and a different skew is applied to each input signal from the tester to the IC memory of the device under test. This can be achieved by providing a memory testing device.

(f) Embodiment of the invention An embodiment of the invention will be described below with reference to the drawings.

FIG. 3 is a block diagram of an IC memory testing apparatus according to an embodiment of the present invention, and FIG. 4 is a time chart thereof.

In the figure, 1 is a tester, 3a is a clock signal,
3b is an address input signal Aφ~7, _41~8 are D type flip-flops (FF), 5 is an oscillator (OSC),
6 is a 4-bit counter, 7 is an 8-input, 1-output selector, and 8 is a D-type flip-flop (FF).

In Fig. 3, the tester 1 displays the clock signal 3a and address information Aφ to 7 every cycle to, but in addition to this, the tester 1 also displays the chip select, write enable, and output signals (not shown) directly at the input terminals of the device under test. It is assumed that a write/read operational function test is performed on the device under test by sending enable and data output I/O1-p or receiving data input I/O1-p.

In the FFs _{41 to 8} shown in the figure, in order to generate eight types of delay pulses, they are reset in parallel and simultaneously by the clock signal 3a. The output terminal Q of the first stage is connected to the D input terminal of the next stage, and the output terminal Q of the next stage is connected in cascade to the D input terminal of the next stage, and so on, and the clock terminal CLK of each FF4 _{1 to 8} is connected in series. Since the oscillation frequency is input in parallel from OSC5, FF4, which has been given a high level to the D input terminal from the previous stage, changes its output terminal Q from low level to high level when the high level of the oscillation frequency is input at the next timing. and sequentially send out eight types of delayed signals as shown in FIG. 4 c to j. The first stage _FF4-1 receives clock signal 3.
When a is applied, the high level generated at the output terminal Q of the final stage _FF4-8 is applied to the D input terminal to set it. Therefore, the plurality of delayed signals from FF4 _{1 to 8} are reset by the clock signal and then become a group of delayed signals delayed by one cycle or multiple cycles depending on the oscillation frequency of OSC5, The delayed signal groups are each sent to the MPX 7 in parallel. On the other hand 6
Since each counter 6 does not involve a reset operation, it increments each time it receives the clock signal 3a from an undefined numbered state and outputs each 4-bit counting result.

If this total of 24 bits is arbitrarily combined to form 8 sets of number strings consisting of 3 bits, the 8 sets of number strings are 1
Variables with different contents are obtained for each clock signal 3a, resulting in a simple random number sequence. This 3-bit 8-set number string is sent as a selection signal for the MPX7.

Although not shown in the drawings, the counter 6 may further have another output terminal, such as a carry output, inputted to another counter to perform another increment every plural clocks.

Also, although 8 sets of 3 bits were obtained from 24 bits, this combination does not limit the present invention, and more, for example, 32 bits may be obtained, or some of them may be overlapped.

The eight MPX7s, which receive a 3-bit variable string for each clock signal 3a, send one delayed signal to the clock terminal of the corresponding FF8 according to the variable string from among the group of delayed signals received from FF4 _{1 to 8} . When input, the address information from the tester 1 is set to each D terminal in synchronization with the clock signal 3a, so its contents are output to the output terminal Q, and the next clock signal 3a is output.
address information is applied to the D terminal and waits, and the output contents are held until switching operation by the next cycle delay signal input again to the clock terminal CLK.

Therefore, each FF8 has a corresponding MPX for each cycle.
The new address information Aφ~ has a skew applied compared to the conventional address information that switches to the next cycle address information at the timing according to the delay signal selected by No. 7.
Sends 7. As described above, by applying skew to the new address information and sending it to the memory element of the test object, all of the This results in the combinations being presented out of order in write and read operations.

Also, by adjusting the oscillation frequency of OSC5, the width of the skew can be changed arbitrarily. Although the above description has been made using address information as an example, it goes without saying that the same effect can be obtained by applying it to other data input I/Os 1 to 1-p.

(g) Effects of the Invention As explained above, according to the present invention, multiple skews with changes in each input signal to the device under test, which could not be applied in conventional IC memory tests, can be solved in the same cycle as in conventional operational function tests. This is useful because malfunctions caused by skew can be easily detected without increasing the number of testing steps.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional IC memory test equipment, Figure 2 is its time chart,
FIG. 3 is a block diagram of an IC memory testing apparatus according to an embodiment of the present invention, and FIG. 4 is a time chart thereof. In the figure, 1 is a tester, 4 and 8 are D-type flip-flops, 5 is an oscillator, 6 is a counter, and 7 is a selector.

Claims (1)

[Claims] 1. An asynchronous oscillator with a frequency faster than the repetition period of the clock signal of the tester, a plurality of flip-flops connected in series, and a plurality of flip-flops having a delay time of one cycle and/or multiple cycles to synchronize the oscillation frequency with the clock signal. a delay signal generating means, a p-group q-bit variable string generating means obtained by arbitrarily combining m×n-bit output signals from n-sets of m-bit counters incremented by the clock signal;
p selector means for selecting the delayed signal according to a variable string of q bits, and address, data input, chip select, etc. for sending from the tester to the IC memory of the device under test according to the output signal of the selector. It is equipped with a plurality of flip-flops that perform switching operations for each input signal, and selects the delayed signal according to the combination of the output signals of the variable string generation means for each clock signal of the tester, and selects the delay signal from the tester to the IC under test. An IC memory testing device characterized in that a different skew is applied to each of the input signals to the memory.