JPH0430036B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a dot pattern generation circuit in an image processing apparatus or the like.

Conventionally, when a dot matrix pattern is generated in an image memory connected to a display device, the dot pattern and two-dimensional image memory address are transferred and written into the image memory one by one.

However, according to this conventional method, each dot has a two-dimensional address (i.e.,
Since it is necessary to store the dot patterns (Y or rows and columns), there is a drawback that the capacity of the dot pattern memory must be increased. Furthermore, when specifying a pattern to the dot pattern memory, it was necessary to give a two-dimensional address per dot for each pattern.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a pattern generation circuit that can eliminate the above-mentioned drawbacks, reduce the storage capacity of a dot pattern memory, and require only one of row or column addresses to be specified. do.

The main feature of the present invention is that a dot pattern is stored in a dot pattern memory in the form of 1 bit per dot, and that data can be extracted from this memory by specifying either a row or column address in the dot pattern memory. The point is that it is possible to generate a two-dimensional address for the image memory.

Hereinafter, the present invention will be described in detail based on illustrated embodiments. FIG. 1 shows an embodiment of a pattern generation circuit according to the present invention. Note that FIG. 1 shows an example in which the row address Y among the rows and columns is used as the address input to the dot pattern memory.
The dot pattern is a matrix, and therefore the present invention can be implemented using either row or column addresses, so a detailed explanation of the example using column address X will be omitted.

<Configuration> In FIG. 1, the dot pattern memory 10 has a configuration of 7 rows and 5 columns per pattern, and various patterns are formed by valid bits (here, bits with logic level "1") and their inverted bits. A dot matrix pattern is stored, and by inputting a combination of pattern number k and row address i (0≦i≦6) as an address input signal, the i-th row in the k-th pattern is selected for each specified address. row direction dot pattern P(i,0)k
~P(i,4)k data is output. These row direction dot pattern data P(i,0)k~P
(i, 4)k is input to the next gate circuit 20.

The gate circuit 20 is composed of five AND circuits, and is controlled by the input end side of the row direction dot pattern data P(i,0)k to P(i,4)k by a gate control signal from a feedback circuit 70, which will be described later. This row direction dot pattern data P(i,0)k to P(i,4)
Only the bit data inputted to the AND circuit to which the logic level "1" is inputted as the gate control signal passes through the AND circuit and is transferred to its output end. In addition,
Here, regarding the relationship between the upper and lower bits in the output data of the gate circuit 20, it is assumed that bit 0 is the most significant bit and bit 4 is the lowest bit. The output data of this gate circuit 20 is input to the next priority encoder 30.

The priority encoder 30 inputs the output data of the gate circuit 20 and has a predetermined priority rule regarding the positional relationship of valid bits included therein, and according to this priority rule, input bits 0, 0,
. . , 4 as the bit to be encoded, and the bit position of this bit to be encoded is encoded. Here, the bit position of only the lowest valid bit among the input valid bits is encoded and output. This encoded output becomes column address X. FIG. 2 shows a truth table representing the input/output relationship of the priority encoder 30. In this table, the END signal _E0 output from the priority encoder 30 is output as a signal indicating the end of encoding when all input data is "0", that is, when there is no longer any valid bit in the input data. Ru. In the truth table of FIG. 2, this is the top row, and the output E ₀ at this time is "1". On the other hand, the output data of the priority encoder 30 (ie, the data of column address X) is also given to the next decoder 40. The decoder 40 decodes the output data of the priority encoder 30 and provides it to the feedback circuit 70.

The feedback circuit 70 is a circuit from the output end of the decoder 40 to the input end of the gate circuit 20, and includes a latch register 50 that temporarily holds the output data of the decoder 40, and an inverter 60 that inverts the output data of the latch register 50. Contains. Note that the latch register 50 is cleared by the clear signal CL during initialization and when the END signal is generated.

<Operation> Next, the operation will be explained. First, in the following explanation, the k-th pattern stored in the dot pattern memory will be explained as the number "5" shown in FIG. In the figure, the black parts are valid bits.

FIG. 4 is a truth table showing the relationship between the input data of the priority encoder 30, its output data, the output data of the decoder 40, and the output data of the inverter 60. The following will explain based on this truth table.

Now, in FIG. 1, when pattern number k and row address "000" are input to the dot pattern memory 10 as an input address, the output lines P (i, 0), P (i, 1), P of the dot pattern memory 10 are
From (i, 2), P (i, 3), P (i, 4), the fourth
The data of the row direction dot pattern "11111" in the 0th row of the pattern shown in the figure is output. At this time, since the latch register 50 has been initialized (cleared), all outputs of the inverter 60 are at the "1" level.

As a result, bits 0 to 4 are output from the gate circuit 20.
The data “11111” is output to the input terminal No. 0, 1, 2, 3, 4 of the priority encoder 30.
are input respectively.

[Step 0] Priority encoder 30
encodes the data "11111" from the gate circuit 20, but as described above, what is encoded is the lowest bit position among the valid bits at that time. Specifically, the least significant bit at this time is bit 4, and the priority encoder 30 outputs data of "000". This data value becomes the data of column address X in pattern number k. The data at the row address Y is "000", which is the same as the designated row address Y input into the dot pattern memory 10.

The output data “000” of the priority encoder 30 is input to the decoder 40.
decodes this and outputs “00001” to output terminals 4 to 0.
Output the data. This data is latched in the latch register 50 in the feedback circuit 70, so that the output data _G0 to _G4 of the inverter 60 at this time becomes "11110" and is input to the gate circuit 20.

[Step 1] When the 0th row of the pattern in FIG. 4 is completed, Step 1 of the next row is started. At this time, the row address of the dot pattern memory 10 is sent from the priority encoder 30 to the END signal E ₀
The output data P(i, i,
0) to P(i, 4) are fixed to the state of "11111". Therefore, the gate circuit 20 stores the data "11110" in bits 0 to 4 based on the fixed data "11111" in the dot pattern memory 10 and the feedback data G ₀ to _{G 4} "11110" from the feedback circuit 70. Output. This data becomes the input data of the priority encoder 30 in step 1.

In this input data, the least significant bit of the valid bit is bit 3, and the priority encoder 3
0 encodes only the position of this bit 3 and outputs data of "001" to outputs 0-2. Therefore, the column address X in step 1 is “001”
(See Figure 5). This data is again input to the gate circuit 20 via the feedback circuit 70.

Thereafter, the above process is repeated until step 5 as shown in the truth table of FIG.
The address changes as "010", "011", and "100".
During this time, the priority encoder 30
Since the END signal _E0 is not output, the Y address remains "000".

To summarize the above, dot pattern memory 10
The address (X, Y) of the dot pattern generated from “11111” of the row direction dot patterns P(i, 0) to P(i, 4) in the 0th row of the kth pattern of
are (0,0), (1,0), (2,0), (3,0)
，
(4,0). At the end of this cycle, the output data of the priority encoder 30 is “100”
When this happens, the output data _G0 to _G4 of the inverter 60, which is the feedback data, becomes "01111", so the gate circuit 20 is completely prohibited. As a result, the priority encoder 30
All the input data becomes "0" and the END signal _E0 is generated. When this END signal _E0 is generated, the latch register 50 is cleared, the row address Y of the dot pattern memory 10 changes to "001", and the column address X also becomes "001".

In this way, when the END signal is generated, the processing for row address Y "000" ends, and then the processing for row address Y "001" is newly started.

That is, as shown at the bottom of FIG. 4, the output data P(i,0) of the dot pattern memory 10
~P(i,4) becomes “00001” and is input to the priority encoder 30. At this time, "000" is output as output data 0 to 2 of the priority encoder 30, which means that an address dot pattern of (0, 1) has been generated. Furthermore, “000” of this output data 0 to 2 is sent to the decoder 40.
, and the decoder 40 outputs its output terminals 4 to 0.
The data “00001” is output to the latch register 50 and latched to the latch register 50. As a result, the output data G ₀ to _{G 4} of the inverters become "11110" and are again given to the gate circuit 20 as feedback data. At this time, G ₀ of the feedback data is “0”
Therefore, the gate circuit 20 is prohibited and its output data becomes all "0" from bits 0 to 4. Then, the priority encoder 30 outputs the END signal _E0 . This means that the row address Y
“001” means that there is no valid bit at the row address X “000”, and the next second line “001”
Go into action about.

Thereafter, in the same way, at row address Y "001", column address X "001", "010", "011", "100"
Then, at row address Y “010”, column addresses “000”, “001”, “010”, “011”, “100”
”
All dots X, Y of the kth pattern
The address will be generated and the process will end. The above situation is summarized in the truth table of FIG. Note that FIG. 5 shows a pattern for the number "5".

<Modification> The above embodiment shows an example in which the row address Y is used as the address for specifying the dot pattern memory 10, but as mentioned earlier, the priority encoder 30 uses the column address A configuration may also be adopted in which address Y is generated. In that case, the pattern may be specified using a combination address signal of column address j (0≦j≦4) and pattern number k. Then, for each designated address, the data of the j-th column direction dot pattern P(o,j)k to P(b,j)k in the k-th pattern is obtained from the dot pattern memory 10 and processed in the same way. Bye.

<Effects> As described above, according to the present invention, either a row address or a column address may be used for the dot pattern memory, and the other address can be generated by the configuration of the present invention. Since it is not necessary to store dot patterns in a two-dimensional address in a dot pattern memory as in the conventional case, the storage capacity can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a pattern generation circuit according to the present invention, FIG. 2 is a diagram showing a truth table of a priority encoder, and FIG. 3 is a diagram showing a pattern of "5" stored in a dot pattern memory. 4 is a diagram showing a truth table of the operation of the pattern generation circuit for this pattern "5", and FIG. 5 is a diagram showing a truth table showing all address generation states for pattern "5". It is. DESCRIPTION OF SYMBOLS 10... Dot pattern memory, 20... Gate circuit, 30... Priority encoder, 40... Decoder, 50... Latch register, 60... Inverter, 70... Feedback circuit, X... Column address, Y... Row address, k... Pattern number, _E0 ...
end signal.

Claims (1)

[Scope of Claims] 1. A dot matrix pattern having a matrix configuration of m rows and n columns per pattern and forming various patterns by effective bits and their inverted bits is stored, and this dot matrix pattern number k(0 ≦k) and row address i (0≦i≦m−
1) or column address j (0≦j≦n-1) as an address input signal, and for each address input signal, the i-th row direction pattern P (i, 0 )k~P(i,n-
1) Column direction pattern P(0,j) for the k or jth column
A dot pattern memory that outputs data from k to P(m-1,j)k, and output data from this dot pattern memory as input data, and transfer of this input data to the output end side according to a gate control signal. and a gate circuit that takes output data of the gate circuit as input and has a predetermined priority rule regarding the positional relationship of valid bits included therein, and according to this priority rule, selects which of a plurality of input bits is selected. One effective bit is set as the bit to be encoded, and the bit position of the bit to be encoded is encoded to correspond to the other address i or j of the row address i or column address j input to the dot pattern memory. A priority encoder that outputs an address signal, a decoder that decodes the output code of this priority encoder, and a transfer control in the gate circuit that allows all valid bits included in the output data of the dot pattern memory to be transferred to the priority encoder. a feedback circuit that feeds back the output signal of the decoder as the gate control signal to the gate circuit so that the bits are sequentially set as the encoding target bits, and all rows on the dot matrix (i=0, 1,
…, m-1) or column (j=0,1,…,n-
1) A pattern generation circuit which sequentially outputs encoded values at effective bit positions in an n-bit or m-bit dot pattern constituting each row i or column j.