JPH0430531B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a vehicle oil level detection device suitable for detecting an insufficient amount of oil in an oil tank of a vehicle oil supply system based on its liquid level.

(Prior Art) Conventionally, this type of vehicle oil level detection device employs a self-heating type resistance temperature detector having a positive resistance temperature characteristic attached to an oil tank.
When a constant current is applied to this resistance thermometer, the internal temperature increases due to heat generation and heat radiation of this resistance thermometer depending on the degree of penetration of the resistance bulb into the oil in the oil tank. The oil level is detected based on the increase in resistance value, and when this detected level exceeds a predetermined reference level,
Some devices are designed to generate an output signal indicating oil shortage.

(Problem to be Solved by the Invention) However, in such a configuration, when detecting the oil level, a constant current is not applied to the resistance temperature sensor until the internal resistance value of the resistance temperature sensor is saturated. Because it is designed to continue,
There is a problem in that the output signal cannot be generated with good responsiveness in accordance with the timing at which constant current is started to be applied to the temperature-measuring resistor.

(Object of the Invention) In order to cope with such a problem, the present invention uses an oil level detection device for a vehicle to promptly detect a lack of oil in an oil tank after the ignition switch of the vehicle is closed. This is what we are trying to do.

(Means for solving the problem) In solving the problem, the configuration of the present invention is as follows:
a constant current generating means that is supplied with power from a DC power source of the vehicle in response to closing of an ignition switch and generates a constant current; a detection means for detecting an internal resistance value increasing due to self-heating as an analog signal; and a detection means for generating a second timing signal after being supplied with power from the DC power supply in response to closing of the ignition switch to generate a first timing signal. means for generating timing signals sequentially, converting the analog signal into a first digital signal in response to the first timing signal, and converting the analog signal into a second digital signal in response to each of the second timing signals after the conversion; A-to-D conversion means for repeatedly converting into a digital signal; setting signal generation means for generating a digital value corresponding to a predetermined rise width of the value of the analog signal as a setting signal; and a first calculating means for calculating the sum of the values of the respective second digital signals and generating the same as a comparison reference signal; The present invention further includes a comparison means for generating an output signal representing a liquid level corresponding to the oil shortage when the value becomes larger than the value of the comparison reference signal.

(Effects of the Invention) By configuring the present invention in this way, when a constant current generated from the constant current generating means is applied to the detecting means in response to the closing of the ignition switch, the A - D conversion means converts the analog signal into the first digital signal in response to the first timing signal, and the first calculation means calculates the sum of the value of the first digital signal and the value of the setting signal. is generated as a comparison reference signal, and in the process where the level of the analog signal increases after the start of applying the constant current to the detection means responsive to the closing of the ignition switch, the A-D conversion means detects the timing The analog signal is repeatedly converted into a second digital signal in response to each second timing signal generated subsequent to the first timing signal from the signal generating means, and the comparing means is configured to convert the analog signal into a second digital signal in response to each second timing signal generated subsequent to the first timing signal. When the value of the analog signal becomes larger than the value of the comparison reference signal, the output signal is generated. the start time of applying the constant current;
That is, the output signal is continuously checked from the time when the ignition switch is closed, and when the timing value corresponding to the level of the analog signal becomes larger than the value of the comparison reference signal, the output signal is generated. The detection of oil shortage by this type of vehicle oil level detection device can be carried out quickly after application of a constant current to the detection means in response to closing of the ignition switch.
As a result, it is possible to prevent seizure of the internal combustion engine due to oil shortage when the ignition switch is closed.

(Embodiment) An embodiment of the present invention will be described below with reference to the drawings. Fig. 1 shows an example of a vehicle oil level detection device to which the present invention is applied, and this oil level detection device includes an oil level sensor. 10, a constant current generating circuit 20 and a constant voltage regulator 30 connected to the positive terminal of the DC power supply B via the ignition switch IG of the vehicle, and a clock circuit 40 and a reset signal generator connected to the constant voltage regulator 30. A circuit 50 is provided. The oil level sensor 10 includes an oil level gauge 11 (third
It is mounted inside the tip of the tip (see figure 4), and its lower part is exposed to the outside through the opening 11a (see figure 4) of this tip, and has a positive resistance-temperature characteristic (see figure 6). It is formed from a self-heating type resistance temperature sensor. However, the oil level sensor 10
As will be described later, when a constant current is applied to it, it increases its internal resistance value due to self-heating, and this is generated as an analog voltage _Vs.

In such a case, the analog voltage V _s from the oil level sensor 10 changes as shown in FIG. 7 in relation to time t (seconds). However, in FIG. 7, the curve _L1 indicates the position where the oil level in the oil tank (not shown) of the vehicle is at the upper limit level at the tip of the oil level gauge 11.
(Indicated by reference numeral 11b in Figures 4 and 5)
The curve L ₂ corresponds to the case where the oil level is at the lower limit level position MIN (indicated by reference numeral 11c in FIGS. 4 and 5) at the tip of the oil level gauge 11. Corresponding to this, the curve L ₁ (or L ₂ ) shows that after starting to apply a constant current to the oil level sensor 10 at t=t ₀ , the analog voltage
This shows that V _s suddenly rises to V _s0 and then becomes almost saturated at V _s1 (or V _s2 ) as it rises. The oil level gauge 11 is attached to the oil tank by dipping its tip into the oil in the oil tank.

The constant current generating circuit 20, as shown in FIG.
The reference voltage generator 21 has a reference voltage generator 21, which receives the power supply voltage from the DC power supply B and generates a reference voltage in response to the closing of the ignition switch IG. The comparator 22 has its inverted input terminal connected to the output terminal of the reference voltage generator 21, and its non-inverted input terminal connected to both resistors 22a, 22b and the ignition switch IG.
It is connected to the positive side terminal of DC power supply B via.
Therefore, when the power supply voltage from the DC power source B is applied to the non-inverting input terminal of the comparator 22 via the ignition switch IG and both resistors 22b and 22a, the voltage at this non-inverting input terminal is applied to the reference voltage generator 21. higher (or lower) than the reference voltage from
At this time, a high level signal (or low level signal) is generated from the output terminal of the comparator 22.

The emitter of the buffer transistor 23 is grounded, and the base of the transistor 23 is connected to the output terminal of the comparator 22 via a resistor 23a, while the collector of the transistor 23 is connected to the output terminal of the comparator 22 via the resistor 23a, and the ignition terminal. Connected to the positive terminal of DC power supply B via switch IG. In addition, the transistor 24 passes the resistor 23b through the transistor 23 at its base.
The collector of this transistor 24 is grounded via the oil level sensor 10, while the emitter of this transistor 24 is connected to the positive terminal of the DC power supply B via a resistor 22b and an ignition switch IG. ing. Therefore, the transistor 23 becomes conductive in response to the high level signal from the comparator 22, and both the resistors 23 and 23 become conductive.
The base current of the transistor 24 is drawn through the resistor 23b so as to cause the transistor 24 to perform a current amplification effect in cooperation with the transistors b and 23c, and to maintain the current flowing from the transistor 24 to the oil level sensor 10 at a constant current. Function.

Further, the constant current generating circuit 20 includes a transistor 25
The transistor 25 has its emitter grounded and its collector connected to the base of the transistor 23. The transistor 25 also has a resistor 2 at its base.
5a to a NAND gate 60, and becomes conductive (or non-conductive) in response to a high level signal (or low level signal) generated from this NAND gate 60 as described later. This means that transistor 25, due to its conduction, comparator 2
This means that the transistor 23 is rendered non-conductive even while a high level signal is being generated from the comparator 22, and the non-conductive state allows the comparator 22 to control the transistor 23.

The constant voltage regulator 30 is supplied with power from the DC power supply B when the ignition switch IG is closed, and generates a constant voltage _Vd . Reset signal generation circuit 5
0 is a time constant circuit 51 that responds to the constant voltage V _d from the constant voltage regulator 30, as shown in FIG.
The reset signal R is generated by the cooperation of the inverter 52 and
(See Figure 8). The clock circuit 40 is
As shown in FIG. 2, an oscillator 41 connected to a constant voltage regulator 30, and a binary counter 4 connected to this oscillator 41 and a reset signal generating circuit 50.
The oscillator 41 generates a series of oscillation pulses in response to the constant voltage V _d from the constant voltage regulator 30 . The binary counter 42 is reset by the reset signal R from the reset signal generating circuit 50, counts each oscillation pulse from the oscillator 41, and transmits the counting result to each series of clock pulses _c1 from its output terminals _Q1 and _Q10, respectively. and occurs as c ₂ .

As shown in FIGS. 1 and 2, the drive signal generation circuit 70 is connected between the clock circuit 40, the reset signal generation circuit 50, and the NAND gate 60, and is connected between the binary counter 42 and the inverter 52.
A binary counter 71 connected to this binary counter 71, an AND gate 72 connected to this binary counter 71, and this AND
RS flip-flop 73 connected to gate 72 and inverter 52; inverter 74 connected to inverter 52;
It consists of an AND gate 75 connected to an RS flip-flop 73. binary counter 71
is reset in response to the reset signal R from the inverter 52 and inverts and counts each clock pulse _c2 from the binary counter 42, and this count value is counted for a predetermined period of time (for example, 1.5
When the value reaches the value corresponding to the elapsed time (seconds), high level signals are generated from both output terminals Q ₉ and Q ₁₀ .

The RS flip-flop 73 is reset in response to the reset signal R from the inverter 52 and generates a high level signal from its output terminal Q, and this high level signal is sent from both output terminals Q ₉ and Q ₁₀ of the binary counter 71. respond to each high level signal
annihilation under the control of AND gate 72.
AND gate 75 generates a high level signal in response to the inverting action of inverter 74 as reset signal R from inverter 52 disappears while a high level signal is being generated from output terminal Q of RS flip-flop 73. This means that AND gate 7
5 means that a high level signal is generated as a drive signal for the predetermined period of time after the reset signal R is generated.

As shown in FIGS. 1 and 2, the timing control circuit 80 includes a clock circuit 40, a NAND gate 60, an AD conversion circuit 90, and both AND gates 1.
10a, 120a, presettable down counter 110, presettable up counter 12
0 and the OR gate 130a. This timing control circuit 80 includes D-type flip-flops 81, 82, 83, and 84.
D-type flip-flops 81-83 are reset by a high level signal from NAND gate 60 and generate a low level signal and a high level signal from their respective output terminals Q, respectively. Further, after being reset, the D-type flip-flop 81 sends the output signal from each output terminal Q to the binary counter 42.
In response to each clock pulse c ₂ from the D-type flip-flop 82 or each high level signal from the output terminal Q of the D-type flip-flop 82, they are repeatedly inverted together in cooperation with the OR gate 81a.

After being reset, the D-type flip-flop 82 repeatedly inverts the output signals from its respective output terminals Q in response to each high-level signal from the output terminal of the D-type flip-flop 81 in sequence. This means that the D-type flip-flop 82, after being reset, outputs only a single high level signal from its output terminal Q based on the two consecutive clock pulses _c2 from the binary counter 42 in cooperation with the D-type flip-flop 81. It means to occur. After being reset, the D-type flip-flop 83 is supplied with a single high-level signal from the output terminal Q of the D-type flip-flop 81 or each high-level signal from an OR gate 89e (to be described later) via an OR gate 83a, and outputs each output terminal thereof. The output signals from Q and Q are repeatedly inverted together. This means that the D-type flip-flop 83 repeatedly generates each high level signal from its output terminal Q as the A-D conversion start command signal b (see FIG. 8) to the A-D converter circuit 90.

D-type flip-flop 84 is NAND gate 6
OR gate 8 in response to the high level signal from 0
4a generates a low level signal and a high level signal from each output terminal Q, respectively, and responds to the single high level signal from the output terminal Q of the D-type flip-flop 81 with these low level signals and high level signals. After both are inverted, they are inverted again by a high level signal from an AND gate 89a, which will be described later. In other words, after being reset, the D-type flip-flop 84 outputs a high-level signal and a low-level signal from each of its output terminals Q in response to a single high-level signal from the output terminal Q of the D-type flip-flop 81. Generated as gate signals d ₁ , d ₂ (see Figure 8),
These respective gate signals d ₁ and d ₂ are generated after that.
It is repeatedly maintained in the extinction state in response to each high level signal from the AND gate 89a.

Further, the timing control circuit 80 has D-type flip-flops 85, 86, 87, and 88. OR gate 85 in response to signal i (see Figure 9)
b, and generates a low level signal and a high level signal from each output terminal Q, respectively. In addition, this D type flip-flop 85
are output from each output terminal Q under each inverting action of the inverter 85a in response to the fall of each A-D conversion signal e (see FIG. 8) generated from the A-D conversion circuit 90 as described later. The output signals are repeatedly inverted together. Note that in FIG. 9, the symbol f indicates a high level signal from the output terminal Q of the D-type flip-flop 85.

The D-type flip-flops 86 to 88 constitute a frequency dividing circuit, and are repeatedly reset in response to each high-level signal from the output terminal of the D-type flip-flop 85, and output a low-level signal and a high-level signal from their respective connection terminals Q. A level signal is generated respectively. Furthermore, the D-type flip-flop 86 is
Each clock pulse c ₂ ( (see FIG. 9) through the AND gate 86b and its respective output terminals Q,
The output signals from both are repeatedly inverted. In addition,
In FIG. 9, symbol g indicates a high level signal from the output terminal Q of the D-type flip-flop 86.

D-type flip-flop 87 repeatedly inverts the output signals from its respective output terminals Q in response to each high level signal from the output terminal of D-type flip-flop 86. In such a case, the high level signal from the output terminal Q of the D-type flip-flop 87 is indicated by the symbol h in FIG. Also,
D-type flip-flop 88 repeatedly inverts the output signals from its respective output terminals Q in response to each high level signal from the output terminal of D-type flip-flop 87. In such a case, the high level signal from the output terminal Q of the D-type flip-flop 88 corresponds to the above-mentioned high level signal i.

The AND gate 89a performs an OR operation only when each high level signal g from the output terminal Q of the D-type flip-flop 86 and each high-level signal from the output terminal of the D-type flip-flop 87 are generated together.
A timing signal m (see FIG. 9) is generated as each high level signal to be applied to the gates 84a and 89e. The NOR gate 89b is activated only when both the high level signal from the output terminal of the D-type flip-flop 86 and the high-level signal from the output terminal of the D-type flip-flop 87 disappear.
Each clock pulse _c2 from the AND gate 86b is sequentially inverted and the timing pulse l (see FIG. 9)
occurs as. The OR gate 89e generates each timing signal m from the AND gate 89a or each timing signal l from the NOR gate 89b as each high level signal to be applied to the OR gate 83a.

NOR gate 89c is a D-type flip-flop 8
Only when the high-level signal g from the output terminal Q of the D-type flip-flop 87 and the high-level signal g from the output terminal of the D-type flip-flop 87 have both disappeared, each clock pulse _c2 from the AND gate 86b is sequentially inverted to generate the timing pulse j. (See Figures 8 and 9). Also, AND gate 89d
outputs each clock pulse _c2 from the AND gate 86b to the timing signal k only when a high level signal from the output terminal of the D-type flip-flop 86 and a high-level signal h from the output terminal Q of the D-type flip-flop 87 are both generated. (See FIGS. 8 and 9).

The A-D conversion circuit 90, as shown in FIG.
The transistor 91 has an emitter connected to the output terminal of the constant voltage regulator 30 via a resistor 91a, and a collector connected to ground via a capacitor 92. Further, the base of the transistor 91 is grounded through a resistor 9b and connected to the output terminal of the constant voltage regulator 30 through a diode 93 and a Zener diode 94. Therefore, the transistor 91 responds to the constant voltage V _d from the constant voltage regulator 30 and the diode 9
Under the conduction of 3, the zener voltage generated from the zener diode 94 causes the capacitor 92 to conduct.
Apply a constant current to. Capacitor 92 is charged by receiving a constant current from transistor 9 and generates a charging voltage.

The comparator 95 is connected to the oil level sensor 10
A low level signal is generated when the analog voltage V _s from the capacitor 92 is higher than the charging voltage from the capacitor 92, and an increase in the charging voltage above the analog voltage V _s causes the low level signal to be inverted. The transistor 96 has its base connected to the output terminal Q of the D-type flip-flop 83 through a resistor 96a and an inverter 96b.
A capacitor 92 is connected between the emitter and collector of 6. Thus, the transistor 96 becomes non-conductive under the inverting action of the inverter 96b in response to each A-D conversion start command signal b from the D-type flip-flop 83, allowing the capacitor 92 to be charged, and each A-D conversion start command signal b is turned off. When the D conversion start command signal b disappears, the inverter 96b becomes conductive in cooperation with the resistor 96a, and the capacitor 9
The charging voltage of No. 2 is extinguished by its discharge.

The D-type flip-flop 97 is reset by the OR gate 97a in response to the reset signal R from the reset signal generating circuit 50, and its output terminal Q is reset.
Generates a low level signal from. After being reset by the reset signal R, the D-type flip-flop 97 outputs the constant voltage V _d from the constant voltage regulator 30 to its output terminal Q in response to each A-D conversion start command signal b from the D-type flip-flop 83.
is repeatedly generated as a high level signal from the comparator 95 through the OR gate 97a, and each of these high level signals is extinguished in response to each high level signal generated from the comparator 95 through the OR gate 97a after each generation. This means that
The D-type flip-flop 97 converts each high-level signal from its output terminal Q into a signal width corresponding to the time from the generation of each A-D conversion start command signal b until the charging voltage of the capacitor 92 reaches the analog voltage _Vs. A-D conversion signal e (see Figures 8 and 9)
means that it occurs repeatedly.

AND gate 98 is a D-type flip-flop 97
During the generation of each A-D conversion signal e from the binary counter 42, each clock pulse _c1 from the binary counter 42 is generated sequentially as a clock pulse n (see FIG. 8). In other words, the AND gate 98 converts the number of clock pulses n corresponding to the generation time of each A-D conversion signal e into a digital signal representing the analog voltage _Vs corresponding to the generation time of each A-D conversion signal e. Occurs repeatedly.

AND gate 110a is connected to AND gate 110a during generation of gate signal _d1 from D-type flip-flop 84.
allowing each clock pulse n to be applied to the presettable down counter 110 from the gate 98;
Application of each clock pulse n to the presettable down counter 110 is prohibited by disappearance of the gate signal _d1 . AND gate 120a inhibits application of each clock pulse n from AND gate 98 to presettable up counter 120 during generation of gate signal _d2 from D-type flip-flop 84; Gate signal given to
Allow after the disappearance of d ₂ .

The presettable down counter 110 is connected between the reference value setting circuit 100 and the presettable up counter 120.
00 is the constant voltage V _d from the constant voltage regulator 30
When the oil level is near the lower limit level position MIN, the oil level sensor 1
Predetermined rise width △V of analog voltage V _s arising from 0
(For example, the one's complement of a binary number corresponding to the decimal number 64 is set as a digital reference value, and this is generated as a digital setting signal. The value of the digital setting signal from the reference value setting circuit 100 is preset in response to the signal R, and this preset value is counted down in response to each clock pulse n from the AND gate 110a, and the result of this countdown is used as a comparison digital signal. (See symbol p in FIG. 8). In this case, the value of the comparison digital signal is the value of the digital setting signal from the reference value setting circuit 100 and the initial value of the analog voltage V _s from the oil level sensor 10. corresponds to the sum of digital values corresponding to .

After being reset by the reset signal R from the reset signal generation circuit 50, the presettable up counter 120 repeats the value of the comparison digital signal from the presettable down counter 110 in response to each timing signal j from the NOR gate 89c. and after each of these presets
Each clock pulse n generated from the AND gate 120a is counted up, and each time each count-up value becomes larger than the preset value, a low level signal is generated from the output terminal corresponding to the most significant digit (in FIG. 8, a low level signal is generated). reference).

The shift register 130 passes each high level signal (see symbol u in FIG. 8) generated from the inverter 130b in response to each low level signal from the presettable up counter 120 from an AND gate 89d to an OR gate 130a. In response to each applied timing signal k, its respective output terminal
Shift to Q ₁ , Q ₂ , and Q ₃ sequentially. AND gate 14
0 indicates each output terminal Q ₁ , Q ₂ ,
A high level signal (see symbol w in FIG. 8) is generated only when both high level signals are generated from _Q3 . The NAND gate 60 controls the AND gate 14 while the drive signal from the AND gate 75 is being generated.
The high level signal is produced under the inverting action of the inverter 60a in response to the generation of the high level signal from 0 to 0. Lamp 150 is AND gate 140
The light is turned on by the inverting action of the inverter 150a in response to the generation of a high level signal from the inverter 150a. Note that the shift register 130 stops its shifting action under the control of the OR gate 130a that responds to the high level signal from the AND gate 140.

In this embodiment configured as described above, when the ignition switch IG is closed, the constant voltage regulator 30 is supplied with power from the DC power supply B to generate a constant voltage V _d , and in response to this, the reference value is set. Circuit 100 generates digital configuration signals. Also,
At the same time, the clock circuit 40 generates a clock pulse.
c ₁ and c ₂ , and the reset signal generating circuit 50 generates a reset signal R (see FIG. 8).
After the drive signal generation circuit 70 is reset by the reset signal R, it generates a drive signal in response to the disappearance of the reset signal R, and also outputs a drive signal from the clock circuit 4.
Count the series of clock pulses c ₂ from 0,
NAND gate 60 generates a low level signal upon generation of a high level signal from inverter 60a.

Then, the constant current generating circuit 20 turns off the ignition switch by turning off the transistor 25 which responds to the low level signal from the NAND gate 60.
Power is supplied from the DC power supply B through the IG to generate a constant current, and when the constant current starts flowing into the oil level sensor 10, the oil level sensor 10 self-heats in accordance with the oil level and increases its internal resistance value. Generated as an analog voltage V _s . Further, the D-type flip-flop 81 of the timing control circuit 80 is
In response to a plurality of clock pulses _c2 generated from the clock circuit 40 immediately after generation of the low level signal from the NAND gate 60, the OR gates 81a and D
In cooperation with the flip-flop 82, a single high-level signal is generated from its output terminal Q, and in response, the D-type flip-flop 83 outputs an A-D conversion start command signal b (see FIGS. 8 and 9). ), the D-type flip-flop 84 generates both gate signals d ₁ and d ₂ (see FIG. 8).

Next, the transistor 9 of the A-D conversion circuit 90
6 becomes non-conductive due to the inverting action of the inverter 96b in response to the A-D conversion start command signal b from the D-type flip-flop 83, and the capacitor 92
The transistor 91 responds to the constant voltage V _d from the constant voltage regulator 30 conducts and begins to be charged by applying a constant current, and after the D-type flip-flop 97 is reset by the reset signal R from the reset signal generating circuit 50. , generates an A-D conversion signal e (see FIGS. 8 and 9) in response to an A-D conversion start command signal b from a D-type flip-flop 83, and an AND gate 98 generates an A-D conversion signal e (see FIGS. 8 and 9). During the generation of clock pulses c1 from the clock circuit 40, each clock pulse _c1 is sequentially converted to clock pulse n.
(see Figure 8), and the AND gate 110
a is the gate signal from the D-type flip-flop 84
During the generation of _d1 , each clock pulse n from the AND gate 98 is sequentially applied to the presettable down counter 110, and the presettable down counter 110 performs a preset operation in response to the reset signal R from the reset signal generation circuit 50. The value of the digital setting signal from the reference value setting circuit 100 that has been completed is counted down in response to each clock pulse n from the AND gate 110a, and this is generated as a comparison digital signal (see symbol p in FIG. 8). Note that the AND gate 120a closes based on the gate signal _d2 from the D-type flip-flop 84, and prohibits the application of each clock pulse n from the AND gate 98 to the presettable up counter 120.

As described above, after the A-D conversion signal e is generated from the D-type flip-flop 97 of the A-D conversion circuit 90, when the charging voltage of the capacitor 92 exceeds the analog voltage _Vs from the oil level sensor 10, the comparator 95 goes high. A level signal is generated, and in response to this, the D-type flip-flop 97 eliminates the A-D conversion signal e, and stops the generation of the clock pulse n of the AND gate 98, that is, the A-D conversion effect on the analog voltage _Vs. . Also, in this way, the A-
When the D-conversion signal e disappears, the D-type flip-flop 85 of the timing control circuit 80 switches to the inverter 8.
5a generates a high level signal f (see FIG. 9) from its output terminal Q, and in response, AND gate 86b outputs NAND gate 60.
Under the inverting action of the inverter 86a based on the low level signal from the clock circuit 40, each clock pulse _c2 (see FIG. 9) is passed through the D-type flip-flop 86, both NOR gates 89b, 89c and
It is sequentially applied to the AND gate 89d.

Therefore, after the generation of the high level signal f from the D-type flip-flop 85, the AND gate 89a
A high-level signal g is generated from the output terminal Q of the D-type flip-flop ₈₆ in response to the first clock pulse c2 generated from the AND gate 86b, and a high-level signal g generated before the generation of the high-level signal f is generated from the output terminal of the D-type flip-flop 87. Generates a timing signal m (see Figure 9) based on the high level signal,
In response, the D-type flip-flop 83
At the same time as the D-conversion start command signal b disappears, the D-type flip-flop 84 is reset by the OR gate 84a, and both gate signals d ₁ and d ₂ disappear. As a result, the subsequent application of each clock pulse n from the AND gate 98 to the presettable down counter 110 is prohibited by the AND gate 110a, and the application of each clock pulse n from the AND gate 98 to the presettable up counter 120 is permitted. be done. Incidentally, the capacitor 92 is instantaneously discharged as the transistor 96 becomes conductive due to disappearance of the A/D conversion start command signal b.

Then, when a second clock pulse _c2 is generated from the AND gate 86b following the first clock pulse _c2 , the D-type flip-flop 86 generates a low level signal and a high level signal from its respective output terminals Q, and Flip-flop 87 responds to the high level signal from the output terminal of D-type flip-flop 86 by producing a high level signal and a low level signal from its respective output terminals Q, and AND gate 89d outputs the second signal from AND gate 86b. Under the generation of clock pulse _c2 , a high level signal from the output terminal of the D-type flip-flop 86 and a high-level signal from the output terminal of the D-type flip-flop 87 are generated.
A timing signal k (see FIGS. 8 and 9) is generated in response to a high level signal from an output terminal Q of the shift register 1 through an OR gate 130a.
Granted to 30. At this time, inverter 130b
is generating a low level signal, the shift register 130 responds to the timing signal k from the OR gate 130a to invert the inverter 130b.
Shifts the low level signal from Q1 to its output terminal _Q1 .

Thereafter, when the second clock pulse _c2 from the AND gate 86b falls, the NOR gate 89c outputs a low level signal from the output terminal Q of the D-type flip-flop 86 and a low level signal from the output terminal of the D-type flip-flop 87. Upon generation of the signal, a timing signal j (see FIGS. 8 and 9) is generated, and in response, the presettable up counter 120 changes the value of the comparison digital signal from the presettable down counter 110. Preset. Thus, when the third clock pulse _c2 is generated from AND gate 86b, D-type flip-flop 86 generates a high level signal and a low level signal from its respective output terminals Q.
NOR gate 89b is both D type flip-flop 8
Under the generation of each low level signal from the output terminals 6 and 87, the third signal from the AND gate 86b is
A timing signal 1 (see FIG. 9) is generated in response to the falling edge of the th clock pulse _c2 .

Then, the D-type flip-flop 83 receives the timing signal l from the NOR gate 86b through both OR gates 89e and 83a, and generates the A-D conversion start command signal b, and the capacitor 92 of the A-D conversion circuit 90 - The non-conduction of the transistor 96 in response to the D conversion start command signal b starts its charging and generates a charging voltage, and the D-type flip-flop 97 converts the A-
In response to the D conversion start command signal b, an A-D conversion signal e is generated. In response, the AND gate 98 sequentially generates each clock pulse _c1 from the clock circuit 40 as a clock pulse n, and the AND gate 120a With the disappearance of gate signal d ₂ from D-type flip-flop 84, each clock pulse n from AND gate 98 is applied to presettable up counter 120. Note that the D-type flip-flop 88 receives a high-level signal i under the action of both D-type flip-flops 86 and 87 which respond to the fourth clock pulse _c2 from the AND gate 86b.
This causes the D-type flip-flop 85 to be reset and the high level signal f to disappear.

Next, this presettable up counter 1
20 counts up each clock pulse n from the AND gate 120a, and when this count-up value, that is, the digital value of the analog voltage _Vs , becomes greater than the value of the preset comparison digital signal, the output terminal corresponding to the highest digit is output. In response to this, inverter 130b generates a high level signal and applies it to shift register 130. When the comparator 95 of the A-D conversion circuit 90 generates a high level signal due to the charging voltage from the capacitor 92 rising above the analog voltage _Vs from the oil level sensor 10, the D-type flip-flop 97 performs the A-D conversion. The signal e is eliminated and the AND gate 98 A-D
Stop the transformation action.

Furthermore, the D-type flip-flop 85 receives the inversion effect of the inverter 85a due to the extinction of the A-D conversion signal e, and generates a high-level signal f, and the AND gate 89a cooperates with both the D-type flip-flops 86 and 87 to achieve the above-mentioned signal. Similarly, the timing signal m
Both OR gates 89e, which generate and respond to
D-type flip-flop 83 under the control of 83a.
causes the A/D conversion start command signal b to disappear, and the transistor 96 becomes conductive, thereby instantly discharging the capacitor 92. Then, AND gate 89d
In cooperation with AND gate 86b and both D-type flip-flops 86 and 87, timing signal k is generated in the same manner as described above, and shift register 130 is operated under the control of OR gate 130a responsive thereto.
shifts the high level signal from inverter 130b to its output terminal _Q1 , and NOR gate 89c
In cooperation with the AND gate 86b and both D-type flip-flops 86 and 87, a timing signal j is generated in the same manner as described above, and in response, the presettable up counter 120 outputs the comparison digital signal from the presettable down counter 110. Preset signal values.

Furthermore, the NOR gate 89b is connected to the AND gate 86
b and both D-type flip-flops 86 and 87 generate a timing signal l in the same manner as described above, and both OR gates 89e and 83 respond to the timing signal l.
Under the control of A, the D-type flip-flop 83
-Generate a D conversion start command signal b. Thereafter, if the presettable up counter 120 successively generates a low level signal by repeating the same operation as described above in cooperation with the A/D converter circuit 90, the AND gate 120a, and the timing control circuit 80, the shift register 130 In cooperation with the inverter 130b, the timing control circuit 80, and the OR gate 130a, the high level signal is sequentially shifted from the output terminals _Q1 to _Q3 in the same manner as described above.

Therefore, each output terminal of the shift register 130
When high level signals are generated from Q ₁ , Q ₂ and Q ₃ ,
AND gate 140 generates a high level signal;
It is applied to both inverters 60a and 150a. This means that the digital value corresponding to the analog voltage V _s is greater than the value of the comparison digital signal from the presettable down counter 110, that is, an abnormal signal indicating that the oil in the oil tank is insufficient. Gate 140 generates a high level signal and both inverters 60a, 150a
It means to give to. In such a case, the count-up action of the presettable up counter 120 is repeated until high level signals are generated from each of the output terminals Q ₁ to Q ₃ of the shift register 130, so that the abnormal signal from the AND gate 140 is not affected by noise, etc. It cannot be caused by.

As described above, when the abnormal signal from AND gate 140 is applied to both inverters 60a and 150a, lamp 150 is turned on by the inverting action of inverter 150a. In other words, the process in which the analog voltage V _s rises after the start of constant current application to the oil level sensor 10 in response to the closing of the ignition switch IG can be achieved without the problems described in the prior art section of this specification. AND gate 14 in
When an abnormal signal is generated from zero, the lamp 150 is turned on to promptly notify the oil shortage. At the same time, the NAND gate 60 receives the inverting action of the inverter 60a and generates a high level signal, and in response, the constant current generating circuit 20 makes its transistor 25 conductive and stops generating a constant current. In other words, oil level sensor 1
Since the supply of constant current from the constant current generating circuit 20 is stopped at the same time as the abnormal signal from the AND gate 140 is generated, this helps to reduce wasteful power consumption of the DC power supply B.

Incidentally, the timing at which an abnormal signal is generated from the AND gate 140 in the process of increasing the analog voltage V _s after the start of constant current application to the oil level sensor 10 was repeatedly tested in relation to the oil level in the oil tank. However, when the ignition switch IG was operated at normal speed, the experimental results shown in FIG. 10 were obtained. According to this, the lower the oil level is, the more the abnormal signal occurs (i.e., the digital conversion value by the A-D conversion circuit 90 becomes larger than the value of the comparison digital signal from the presettable down counter 110). It is confirmed that the timing is early. Furthermore, when the ignition switch IG was operated at a slow speed, experimental results as shown in FIG. 11 were obtained. According to this, even if the analog voltage V _s decreases due to a DC voltage drop of the DC power supply B due to starting of the starter of the vehicle, etc. before the internal resistance value of the oil level sensor 10 is saturated, the timing of this decrease is determined. The timing of occurrence of the abnormal signal is earlier than that of the above-described abnormal signal, and therefore, an oil shortage can always be correctly detected without erroneously detecting that the oil amount is appropriate even though there is an oil shortage. As a result, it is possible to reliably prevent seizure or the like caused by oil shortage in the internal combustion engine of the vehicle immediately after the ignition switch IG is closed.

Next, a modification of the above embodiment will be explained with reference to FIG. 12. In this modification, a reference value setting circuit 100a is adopted in place of the reference value setting circuit 100 in the above embodiment, and a clock circuit 40, its configuration is characterized in that a setting adjustment circuit 160 is connected between the AND gate 110a and the presettable down counter 110, and the reference value setting circuit 100a is a one's complement of a binary number corresponding to the decimal number 36. is set as the digital reference value and generated as a digital setting signal.

The setting adjustment circuit 160 has a binary counter 161, which is reset by an OR gate 161a in response to a reset signal R from the reset signal generation circuit 50, and is reset by a series of signals from the clock circuit 40. The clock pulse _c2 is sequentially inverted and counted, and this count value corresponds to the predetermined period T.
(for example, 0.375 seconds), both output terminals
Both _Q7 and _Q8 generate high level signals.
AND gate 161b repeatedly generates a high level signal in response to both high level signals from respective output terminals Q ₇ and Q ₈ of binary counter 161. In addition,
The binary counter 161 responds to each high level signal from the AND gate 161b to
It is repeatedly reset by a to begin its counting operation.

Further, the setting adjustment circuit 10 includes a binary counter 16
2. It has a D-type flip-flop 163 and a shift register 164, and the binary counter 162 receives the reset signal R from the reset signal generation circuit 50.
counts the series of clock pulses _c1 from the clock circuit 40 and produces a high level signal at its output terminal _Q4 each time this count reaches a value corresponding to four times the period of each clock pulse _c1 . . The D-type flip-flop 163 receives the reset signal R from the reset signal generation circuit 50 or
OR in response to a high level signal generated from any of AND gates 166a, 166b, 166c.
It is reset by the gate 163a and generates a low level signal and a high level signal from its respective output terminals Q, respectively. Further, after the D-type flip-flop 163 is reset, the AND gate 16
Each output signal from both output terminals Q is repeatedly inverted in response to high level signals sequentially generated from 1b.

The shift register 164 is reset by the reset signal R from the reset signal generation circuit 50.
In response to high level signals sequentially generated from the AND gate 161b, the constant voltage V _d from the constant voltage regulator 30 is sequentially shifted as a high level signal across its output terminals Q ₁ to Q ₃ . AND gate 16
5 applies each high level signal from the binary counter 162 to a binary counter 166 based on the generation of each high level signal from the output terminal Q of the D-type flip-flop 163, and passes it through an OR gate 167 to a presettable down counter. 110. The binary counter 166 is reset by the OR gate 163a in response to the reset signal R from the reset signal generation circuit 50, counts each high level signal from the AND gate 165, and counts each high level signal from the AND gate 165 until the count reaches 16. When it generates a high level signal from its output terminal _Q5 .

In addition, this binary counter 166 is activated by the high level signal generated from the AND gate 166a in response to the high level signal from its output terminal _Q5 and the high level signal from the output terminal _Q1 of the shift register 164. It is reset under control and counts each high level signal from the AND gate 165, and when this count reaches eight, it generates a high level signal from its output terminal _Q4 . In addition, this binary counter 166 responds to the high level signal from its output terminal Q ₄ and the high level signal from the output terminal Q ₂ of the shift register 164, and the high level signal generated from the AND gate 166b causes the OR gate 163a to be activated. It is reset under control to count each high level signal from the AND gate 165, and when the count reaches four, a high level signal is generated from its output terminal _Q3 . Note that the binary counter 166 controls the OR gate 163a by the high level signal generated from the AND gate 166c in response to the high level signal from its output terminal _Q3 and the high level signal from the output terminal _Q3 of the shift register 164. It will be reset below.

The presettable down counter 110 presets the value of the digital setting signal from the reference value setting circuit 100a using the reset signal R from the reset signal generation circuit 50, and uses this preset value.
It counts down in response to each clock pulse n from AND gate 110a through OR gate 167 and generates the result of this countdown as a first comparison digital signal. In such a case, the first
The value of the comparison digital signal is determined by the reference value setting circuit 10.
This corresponds to the sum of the value of the digital setting signal from 0a and the digital value corresponding to the initial value of the analog voltage _Vs from the oil level sensor 10. Further, the presettable down counter 110 sequentially generates signals through the AND gate 165 to the OR gate 167 as the predetermined period T elapses after the preset.
The preset value is further counted down in response to the 16 high level signals, and the result of this countdown is generated as a second comparison digital signal. In such a case, the value of the second comparison digital signal corresponds to the value obtained by increasing the value of the first comparison digital signal by a value corresponding to the above-mentioned 16 high level signals.

In addition, a presettable down counter 110
After the preset, the preset value is further counted down in response to eight high level signals sequentially generated through the AND gate 165 and the OR gate 167 after the elapse of twice the predetermined period T, and the result of this countdown is calculated. A third comparison digital signal is generated. In such a case, the third
The value of the comparison digital signal corresponds to the value obtained by increasing the value of the second comparison digital signal by a value corresponding to the above-mentioned eight high level signals. Further, the presettable down counter 110 sets the preset value in response to four high level signals which are sequentially generated from the AND gate 165 to the OR gate 167 after the elapse of three times the predetermined period T after the preset. It further counts down and generates the result of this countdown as a fourth comparison digital signal. In such a case, the value of the fourth comparison digital signal is the value obtained by increasing the value of the third comparison digital signal by the value corresponding to the four high level signals (i.e., the value of the presettable down signal in the above embodiment). (the value of the comparison digital signal originating from counter 110). Note that the other configurations are the same as those in the previous embodiment.

Therefore, in this modified example configured in this way, the presettable up counter 120 is
During the predetermined period T after the start of applying a constant current to the oil level sensor 10, the value of the first comparison digital signal from the presettable down counter 110 and
The difference between the number of clock pulses n from the AND gate 120a and the digital value of the analog voltage _Vs is counted, and after the predetermined period T has elapsed and before 2T elapses, the presettable down counter 110
The value of the third comparison digital signal from the presettable down _counter 110 is counted after 2T and before 3T. and the digital value of the analog voltage V _s ,
After 3T has passed and before 4T has passed, the difference between the value of the fourth comparison digital signal from the presettable down counter 110 and the digital value of the analog voltage _Vs is counted.

In other words, presettable up counter 1
Presettable down counter 1 to be constantly compared with the digital value of the analog voltage V _s at 20
The value of the comparison digital signal from 10 is increased by approximating the rise curve of the analog voltage _Vs after the start of applying constant current to the oil level sensor 10, and the presettable up counter 1
Low level signal from 20, i.e. AND gate 1
The timing of generation of the abnormal signal from 40 can be realized earlier and more accurately, and as a result, it is possible to accelerate the timing and improve the accuracy of the oil shortage indication by lamp 150.

In the above modification, the value of the comparison digital signal from the presettable down counter 110 is increased stepwise in four steps every 1/4 of the generation time of the drive signal from the drive signal generation circuit 70. Although an example has been described in which the value of the comparison digital signal from the presettable down counter 110 is increased in stages, the process of increasing the value of the comparison digital signal from the presettable down counter 110 may be changed as necessary.

Furthermore, in carrying out the present invention, the DC power supply B
is supplied with power in response to the operation of the ignition switch IG, converts the analog voltage V _s from the oil level sensor 10 into a first digital value, and after this conversion, repeatedly converts the analog voltage V _s into a second digital value. , the sum of the rise width digital value corresponding to the predetermined rise width of the analog voltage V _s and the first digital value is compared with each of the second digital values, and one of these second digital values is determined as the above-mentioned. The clock circuit 40, the reset signal generation circuit 50, and the drive signal generation circuit 70 are programmed to generate a microcomputer that is programmed to generate an output signal representing the liquid level corresponding to the oil shortage when the oil level becomes larger than the sum of the oil levels. , the timing control circuit 80, the A-D conversion circuit 90, the reference value setting circuit 100 (or 100a), the presettable down counter 110, and the presettable up counter 120.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
Figure 2 is a detailed circuit diagram of the same, Figure 3 is an external view of the oil level gauge, Figures 4 and 5 are enlarged views of the same parts, and Figure 6 is a correct illustration of the oil level sensor in Figures 1 and 2. Graph showing resistance temperature characteristics, 7th
The figure is a graph showing the output characteristics of the oil level sensor, Figures 8 and 9 are output waveform diagrams of each circuit element in Figures 1 and 2, and Figures 10 and 11 are graphs showing the output characteristics of the oil level sensor.
The figure is a graph showing the experimental results of the relationship between the digital value corresponding to the analog voltage from the oil level sensor in FIGS. 1 and 2 and the value of the comparison digital signal from the presettable down counter,
FIG. 12 is a block diagram showing a partial modification of the above embodiment. Explanation of symbols, 10...Oil level sensor, 2
0... Constant current generation circuit, 80... Timing signal generation circuit, 90... A-D conversion circuit, 100, 1
00a...Reference value setting circuit, 110...Presettable down counter, 120...Presettable up counter, B...DC power supply, IG...Ignition switch.

Claims (1)

[Claims] 1. A constant current generating means that is supplied with power from a DC power source of a vehicle in response to closing of the ignition switch of the vehicle and generates a constant current, and a constant current generating means that is supplied with the constant current and generates a constant current in response to closing of the ignition switch of the vehicle; a detection means for detecting an internal resistance value that increases due to self-heating according to the level as an analog signal; timing signal generating means for sequentially generating two timing signals; and converting the analog signal into a first digital signal in response to the first timing signal, and converting the analog signal into a first digital signal in response to each of the second timing signals after the conversion; A-to-D converter means for repeatedly converting a signal into a second digital signal; a setting signal generating means for generating a digital value corresponding to a predetermined rise in the value of the analog signal as a setting signal; a first calculating means for calculating the sum of the first digital signal and the value of the first digital signal and generating this as a comparison reference signal;
When the digital signal is compared with the comparison reference signal and the value of any one of the second digital signals becomes larger than the value of the comparison reference signal, this is determined as a liquid level corresponding to the oil shortage. and comparing means for generating an output signal representative of the vehicle.