JPH0431227B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a sync separation circuit that separates a composite sync signal from a television composite video signal, and particularly to a sync separation circuit suitable for field effect integrated circuits.

(Background of the Invention) Various types of synchronous separation circuits have been devised, and the applicant proposed the circuit shown in FIG. 1 as being particularly suitable for construction on a field-effect integrated circuit. That is, what is shown in FIG. 1 includes a voltage comparator CP ₁ , a capacitor C ₁ , a reference voltage source VR ₁ , a resistor R ₁ and
R ₂ and field effect transistors Q ₁ and Q ₂ . Resistors R ₁ and R ₂ and one end of capacitor C ₁ are connected to the negative phase input terminal of voltage comparator CP _{1 .}
The remaining end is designated as input terminal _I1 . voltage comparator
A reference voltage source VR ₁ is connected to the positive phase input terminal of CP ₁ . The output of the voltage comparator CP ₁ is connected to the output terminal O ₁ , and also connected to the gate and drain of the transistor Q ₁ and the source of the transistor Q ₂ .
Furthermore, the source of the transistor Q ₁ is connected to the remaining end of the resistor R ₁ , and the drain and gate of the transistor Q ₂ are connected to the remaining end of the resistor R ₂ .

In such a configuration, when the composite video signal SI ₁ shown in FIG. 2 is applied to the input terminal I ₁ ,
If the negative phase input terminal of the voltage comparator CP ₁ is at a lower potential than its positive phase input terminal, a synchronous separation output is output to the output terminal O ₁ .
If SO ₁ appears and the negative phase input of the voltage comparator CP ₁ is at a higher potential than its positive phase input, no synchronous separation output will appear at the output terminal O ₁ .

During the synchronizing signal period T ₁ , the capacitor C ₁ is charged by the rectifier of the transistors Q ₁ and Q ₂ and by the resistor R ₁ , and is discharged by the resistor R ₂ during the video signal period T ₂ . Composite video signal that is repeatedly input
In order for the synchronous separation operation to be repeated normally for SI ₁ , the above-mentioned charging and discharging charges only need to be equal.

In other words, for simplicity of explanation, the reference voltage source
The potential V _r of VR ₁ is located between the high and low levels V _H and V _L of voltage comparator CP ₁ , and 2V _r = V _H + V _L [1] The equivalent impedance of transistors Q ₁ and Q ₂ is stopped. If they are sufficiently smaller than R ₁ and R ₂ , then R ₁ and R ₂ should be set so that T ₂ ·R ₁ =T ₁ ·R ₂ [2].

In this way, the synchronous separation characteristic is determined by equation [2], and the relative ratio of resistors R ₁ and R ₂ is required to be highly accurate. can only be obtained by a few percent. Moreover, although the resistive layer on a field-effect integrated circuit has a sheet resistance of several tens of ohms, the equivalent sheet resistance of a field-effect transistor is several tens of kilohms, so that the transistor Q ₁ ,
In order to make the equivalent impedance of Q ₂ sufficiently smaller than the resistors R ₁ and R ₂ , there was a drawback that the element size would have to be large. It is also possible to omit the resistors R ₁ and R ₂ and actively use the equivalent impedance of the transistors Q ₁ and Q ₂ , but in this case, the synchronous separation characteristics will be different from those of the transistors.
It is determined by the channel conductance ratio of Q ₁ and Q ₂ , which is generally a dozen percent or worse than the relative accuracy of the resistor.

(Object of the Invention) An object of the present invention is to provide a synchronous separation circuit whose characteristics do not depend on the relative accuracy of resistors, transistors, etc.

(Structure of the Invention) A synchronous separation circuit according to the present invention includes a voltage comparator, first and second capacitors, a reference voltage source, a changeover switch, and a selection circuit, and a reverse phase input terminal of the voltage comparator has a changeover circuit. Connect the first switching end of the switch and one end of the first capacitor, use the remaining end of the first capacitor as the signal input end, connect the reference voltage source to the positive phase input end of the voltage comparator, and compare the voltages. The signal output terminal of the switch is connected to the second switching terminal of the changeover switch and the control input terminal of the selection circuit, and the two input terminals of the selection circuit are respectively clock input terminals, and The output end thereof is connected to the control input end of the changeover switch, and the second capacitor is connected between the common end of the changeover switch and ground.

(Action of the invention) In the synchronous separation circuit configured as described above,
The selection circuit has a signal applied to its control input, namely the voltage comparator output, and a clock signal applied to its input by the synchronization separation output signal (with its frequencies f ₁ and f ₂ ). Select one of them and output. Further, the changeover switch alternately connects one end of the second capacitor to the output terminal and the negative phase input terminal of the voltage comparator in accordance with the above-mentioned selected one of the clock signals, and repeats this process.

By the way, if the voltage at the output terminal of the voltage comparator is V ₀ , the voltage at the negative phase input terminal is V _i , and the capacitance of the second capacitor is C, then one end of the second capacitor is connected to the output terminal of the voltage comparator. The amount of charge accumulated by the second capacitor is CV _p when connected to the negative phase input terminal.
CV _i . Therefore, the amount of charge transferred from the output end of the voltage comparator to the negative phase input end by one switch operation is CV _p -CV _i =C(V _p -V _i ) [3]. Now, if the selection circuit selects a clock with a frequency of f ₁ , the charge transfer in formula [3] will be performed _f times per second, and the total amount of charge will be:
Cf ₁ (V _p −V _i ), which is equivalent to the resistance of 1/Cf ₁ .

Similarly, if frequency f ₂ is selected, a feedback equivalent to a resistance of 1/Cf ₂ is applied, and since frequency selection is controlled by the voltage comparator output, feedback is also applied in the synchronous separation circuit according to the present invention. The amount will be controlled by the state of its sync-separated output.

Next, connect the composite video signal to the signal input terminal (see Figure 2).
SI ₁ ), and if the negative phase input terminal of the voltage comparator is at a lower potential than the positive phase input terminal, a synchronous separation signal is output to the signal output terminal, and the amount of feedback at that time is 1/Cf ₁ Alternatively, it becomes 1/Cf ₂ , but here we will temporarily set it as 1/Cf ₁ . If the negative phase input terminal is at a higher potential than the positive phase input terminal, synchronous separated output cannot be obtained,
The amount of feedback is 1/Cf ₂ .

Therefore, in order for the synchronization separation operation to be repeated normally for a composite video signal that is repeatedly input, the total feedback amount in the synchronization signal period T ₁ and the total feedback amount in the video signal period T ₂ should be equal. To simplify the explanation, if we assume that the output potential of the reference voltage source is between the high and low levels of the voltage comparator, then T ₁ /Cf ₂ =T ₂ /Cf ₁ T ₁・f ₁ =T ₂・f ₂ [4] is a necessary condition.

(Effects of the Invention) As explained above, the characteristics of the present invention are determined by the frequency ratio of two clock inputs, and according to recent logic circuit technology, it is easy to keep the two clock frequency ratios constant. Therefore, it is possible to realize a synchronous separation circuit that does not depend on the manufacturing accuracy of integrated circuits, unlike conventional synchronous separation circuits. Further, the changeover switch and capacitor, which are the main constituent elements of the present invention, can be easily obtained on a field effect integrated circuit, and from this point of view as well, it can be said that the synchronous separation circuit is easy to integrate into an integrated circuit.
Furthermore, the capacitance C of the second capacitor is 2
The clock frequencies f ₁ and f ₂ can be freely set by selecting the values of the clock frequencies f 1 and f 2 , and selecting a small value C has the effect of reducing the area occupied on the integrated circuit.

(Examples) In order to help understand the effects of the present invention and its applicability to field-effect integrated circuits, some examples will be shown below with reference to the drawings.

FIG. 3 shows an embodiment of the invention, which includes a voltage comparator CP ₂ , capacitors C ₂ and C ₃ , a reference voltage source VP ₂ , a changeover switch SW ₁ , and a selection circuit SC ₁ . One switching end of a changeover switch _SW1 and one end of a capacitor _C2 are connected to the negative phase input end of the voltage comparator _CP2 , and the remaining end of the capacitor _C2 is used as a signal input terminal _I2 . A reference voltage source VP ₂ is connected to the positive phase input terminal of the voltage comparator CP ₂ . The output terminal of the voltage comparator CP ₂ is set as a signal output terminal O ₂ and is connected to the remaining switching terminal of the switching switch SW ₁ and the control input terminal of the selection circuit SC ₁ . The two input terminals of the selection circuit _SC1 are clock terminals _CK1 and _CK2 , respectively, and the output terminal thereof is connected to the control input terminal of the changeover switch _SW1 . Capacitor C ₃ is configured to be connected between the common end of changeover switch SW ₁ and ground.

Changeover switch in one embodiment of FIG. 3
SW ₁ includes field effect transistors Q ₃ , Q ₄ and an inverter I ₁ , and connects the channel electrodes of each of the N-channel transistors Q ₃ , Q ₄ in common, making this a common end, and connecting the channel electrodes of the channel electrodes. The remaining one each is used as a switching terminal, and the output of inverter I ₁ is connected to the gate of transistor Q ₃ , and the gate of transistor Q ₄ and the input of inverter I ₁ are made common, and these are used as control input terminals. There is. Selection circuit SC ₁ is an inverter
I ₂ , OR circuits OR ₁ , OR ₂ , and AND circuit AN ₁ , the output of AND circuit AN ₁ is the output terminal, and its input is connected to the output of OR circuits OR ₁ , OR ₂ . , the output of inverter I ₂ is input to OR circuit OR ₁ , the input of inverter I ₂ is used as a control input together with the input of OR circuit OR ₂ , and
Two clock input terminals with OR ₁ and OR ₂ inputs
CK ₁ and CK ₃ .

In the embodiment of FIG. 3 constructed in this way, clock signals SCK ₁ and SCK ₂ shown in FIG. 4 are applied to the clock input terminals CK ₁ and CK ₂ , respectively. Now, if the voltage comparator CP ₂ output outputs the synchronization separation signal SO ₁ , the selection circuit SC ₁ outputs the clock signal SCK ₁ during the synchronization signal period T ₁ and the clock signal SCK ₂ during the video signal period T ₂ . appear (see Figure 4).
SSC ₁ ), the clock is selectively controlled.

When the clock signal selected in this way is at a high potential, transistor _Q4 is turned on and the capacitance is
Short circuit one end of C ₃ and the output of voltage comparator CP ₂ , inverter I ₁ outputs a low potential, and transistor Q ₃
is in the off state. Conversely, when the clock signal is at a low potential, transistor _Q3 is turned on and transistor _Q4 is turned off, shorting one end of capacitor _C3 to the negative phase input end of voltage comparator _CP2 . As the clock signal repeats, one end of the capacitor _C3 is alternately shorted to the output end of the voltage comparator _CP2 and the negative phase input end, and as described above, it functions equivalently as a feedback resistor.
The amount of feedback is controlled by the selected clock frequency, ie, the selected synchronous separation output, and the embodiment of FIG. 3 operates as a synchronous separation circuit.

The changeover switch in the embodiment shown in FIG. 3 can be constructed in a variety of ways using field effect transistors, examples of which are shown in FIGS. 5 and 6.

In the embodiment shown in FIG. 5, the main parts of _the configuration are the same as those in FIG. ₃ , so _a detailed explanation thereof will be omitted. It is equipped with effect transistors Q ₇ and Q ₈ and an inverter I ₃ , and the channel electrodes of each of the transistors Q ₅ , Q ₆ , Q ₇ , and Q ₈ are connected in common to use this as a common terminal, and the transistors Q ₅ , Q The remaining channel electrodes of transistors 7 and ₇ and the remaining channel electrodes of transistors Q ₆ and Q ₈ are made common, and these are respectively used as switching ends. The output of the inverter I ₃ is connected to the gates of the transistors Q ₅ and Q ₈ , and the gates of the transistors Q ₆ and Q ₇ and the input of the inverter I ₃ are shared, and this is used as a control input.

That is, in the embodiment shown in FIG. 5, the directionality of the switch element is reduced by adding transistors with different polarities in parallel to the transistors Q ₃ and Q ₄ in the structure shown in FIG.

Also, in the embodiment shown in FIG. 6, the main parts of the configuration _are the same as those shown in FIG. ₃ , and the explanation thereof will be omitted. Transistor Q ₁₀ and Transistor
Connect the channel electrodes of Q ₉ and Q ₁₀ in common, and use this as a common end, and use the remaining channel electrodes as each switching end, and make their gates common,
This is used as a control input.

That is, in the embodiment of FIG. 6, the control input is inverted by the inverter _I1 in the embodiment of FIG.
The transistors Q ₃ and Q ₄ were turned on and off alternately, but the inverter I ₁ was omitted by changing the polarity of the transistors.

As explained above, according to the present invention, the synchronization separation characteristic, which was conventionally determined by the manufacturing precision of integrated circuits, can be determined by the clock frequency ratio, which can be obtained easily and with high precision using logic circuit technology, and the field effect A synchronous separation circuit suitable for integrated circuits can be obtained, and its practical value is extremely high.

Further, although the synchronization separation operation for a television composite video signal has been described here as an example, the present invention can be widely used in general electronic circuits.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a synchronous separation circuit previously proposed by the present applicant, FIG. 2 is a diagram showing a composite video signal and a synchronous separation output signal, and FIGS. 3, 5, and 6 are respectively in accordance with the present invention. FIG. 4 shows a synchronization separation circuit which is an embodiment of
The figure is a diagram for explaining the operation of the selection circuit. I ₁ , I ₂ ... input terminal, O ₁ , O ₂ ... output terminal,
C ₁ , C ₂ , C ₃ ... Capacitance, VR ₁ , VR ₂ ... Reference voltage source, CP ₁ , CP ₂ ... Voltage comparator, R ₁ , R ₂ ... Resistance, Q ₁ , Q ₂ , Q ₃ , Q ₄ , Q ₅ , Q ₆ , Q ₉ ... N-channel field effect transistor, Q ₇ , Q ₈ , Q ₁₀ ...
P-channel field effect transistor, SI ₁ ...
Composite video signal, SO ₁ , SO ₂ ... synchronous separated output signal, T ₁ ... synchronous signal period, T ₂ ... video signal period,
SCK ₁ , SCK ₂ ... Clock signal, SSC ₁ ... Selection circuit output signal, AN ₁ ... AND circuit, OR ₁ , OR ₂
...OR circuit, I ₁ , I ₂ , I ₃ ...inverter.

Claims (1)

[Claims] 1. A voltage comparator having a first input terminal supplied with an input signal via a first capacitor and a second input terminal supplied with a reference voltage, and one terminal connected to a reference voltage point. a second capacitor, a switch means for alternately connecting the other end of the second capacitor to the output terminal and the first input terminal of the voltage comparator; 1. A synchronous separation circuit comprising: a selection circuit that selects according to an output signal level of a voltage comparator. 2. The switching means includes first and second field effect transistors and an inverter, and connects channel electrodes of each of the first and second field effect transistors in common to form a common end, and each of the remaining channel electrodes is used as a first and a second switching end, respectively;
The output of the inverter is connected to the gate of the first field effect transistor, and the gate of the second field effect transistor and the input of the inverter are commonly used as a control input terminal. The synchronous separation circuit according to scope 1. 3. The switching means includes first and second field effect transistors, third and fourth field effect transistors having polarities different from these, and an inverter, The channel electrodes of the first and third field effect transistors are connected in common, and the remaining channel electrodes of the second and fourth field effect transistors are connected in common. These are commonly used as first and second switching terminals, respectively, the output of the inverter is connected to the gates of the first and fourth field effect transistors, and the output of the inverter is connected to the gates of the first and fourth field effect transistors.
2. The synchronous separation circuit according to claim 1, wherein the gate of the third field effect transistor and the input of the inverter are shared and used as a control input terminal. 4. The switching means includes a first field effect transistor and a second field effect transistor having a different polarity from the first field effect transistor, and connects one channel electrode of each of the first and second field effect transistors in common. and use this as a common end, and the remaining channel electrodes as first and second switching ends, respectively.
2. The synchronous separation circuit according to claim 1, wherein the gates of these gates are commonly used as control inputs. 5. The selection circuit includes an inverter, first and second OR circuits, and an AND circuit,
The output of the AND circuit is an output terminal, and its input is connected to the outputs of the first and second OR circuits, the output of the inverter is input to the first OR circuit, and the output of the inverter is connected to the output of the first and second OR circuits. The input is a control input together with the input of the second OR circuit,
2. The synchronous separation circuit according to claim 1, wherein the inputs of the first and second OR circuits are configured as two input terminals.