JPH0431232B2 - - Google Patents

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a real-time signal processing processor that implements digital signal processing such as digital filtering and high-efficiency encoding on video signals such as television signals using software. .

(Prior art and its problems) The advantage of real-time digital signal processing is that it is possible to create filters and modulation/demodulators with guaranteed high precision or high stability, which cannot be achieved with analog technology. For example, time-varying adaptive filters can be easily realized. Furthermore, by incorporating the results of digital LSI technology, which has developed rapidly in recent years, it has become possible to miniaturize and reduce power consumption of real-time digital signal processing circuits, and they are gradually being used to replace analog circuits and improve functionality. It is progressing towards. For more detailed information on the advantages of digital signal processing, please refer to pages 1280 to 1284 of the December 1982 issue of the Journal of the Institute of Electronics and Communication Engineers.

Although digital signal processing has many advantages, it also has the drawback of requiring a huge amount of calculation. To perform real-time signal processing, a given digital signal processing must be performed within a sampling period for each sample of the input signal. When performing cyclic digital filter processing,
It requires 8 multiplications and 8 additions in 125 microseconds. Therefore, the frequency bandwidth is more than 1000 times wider than that of telephone voice, and the sampling period is also 1/1000.
To perform signal processing on the following video signals, a circuit that is more than 1000 times faster than a telephone audio signal processing circuit is required. For this reason, advanced digital signal processing can currently only be performed on signals in the audio domain, and video signal processing is currently limited to very simple processing.

Furthermore, regarding digital signal processing for signals in the audio domain, in order to perform advanced digital signal processing, various parameters are often changed or part of the signal processing algorithm is changed. Therefore, there is a strong demand for a signal processing device that can change algorithms and parameters using software. Conventional hardware that performs digital signal processing using software is the IEEE Journal of Solid State Circuits (IEEE Journal of Solid State Circuits).
Circuits) Vol. 16, No. 4 (August 1981), 372
There is a signal processor listed on page 376, and a typical application example of this signal processor is the Proceedings of International Conference on Acoustics Speech Signal Processing, published by IEE in 1982.
of International Conference on Acoustics,
From page 960 of Speech, Signal, Processing) magazine
There is a 32kbps ADPCM published on page 963, which is also targeted at telephone voice processing.

With such conventional processor formats, no matter how fast the arithmetic circuit is made, it is not easy to achieve a speed increase of more than 1000 times, so it is not suitable for software-controlled processors that perform advanced digital signal processing on video. It was hot.

(Object of the Invention) An object of the present invention is to provide a software-controlled circuit capable of performing advanced digital signal processing, particularly highly efficient encoding of moving image signals, on moving image signals such as television signals.

(Structure of the Invention) The real-time video processor of the present invention has a first control system that notifies the position of a partial screen to be input within one screen determined by a synchronization signal that notifies the start of one screen of a video signal such as a television signal. a control unit that generates a second control signal that informs the signal and the screen position to be output; the first control signal is input from the control unit; a capture unit that separately captures the sections specified by the first control signal; and a capture unit that separately processes the input video signal and auxiliary video signal captured by the capture unit before the capture of the next screen starts. A processing unit connected to the output side of the processing unit to store the output video signal and the output auxiliary video signal processed by the processing unit, and to specify the first control signal separately input from the control unit. a plurality of unit processors comprising an output section that separately outputs the stored output video signal and output auxiliary video signal at a time; and a plurality of unit processors each configured to receive the synchronization signal and the input video signal. an input bus for supplying the output video signal, an output bus for transmitting the output video signal output from each of the plurality of unit processors, and an output bus for transmitting the output video signal output from each of the plurality of unit processors; and a feedback bus that transmits the auxiliary video signal to each of a plurality of unit processors, and divides a screen made up of the input video signal and a screen made up of the fed back auxiliary video signal by allowing overlap. , is characterized in that each divided screen undergoes dedicated processing.

(Principle of the Invention) The principle of the present invention is to divide one screen (frame) into multiple partial screens and assign one unit signal processor to each partial screen. It is used to process

First, if a video signal is treated as a one-dimensional signal suitable for transmission, it needs to be sampled at about 10 MHz as mentioned above, and in this case, it is necessary to process each sample within a period of about 100 hsec. If a video signal is treated as a two-dimensional signal called a screen, for example, a television signal only sends 30 screens per second. In other words, if one screen can be processed in 33 milliseconds, there will be a delay of one screen, but real-time performance will be maintained.

Therefore, by dividing one screen into multiple partial screens, assigning multiple unit signal processors to process each partial screen, and having the multiple unit signal processors process in parallel, the unit signal processor Even if the processing capacity per setter is such that it can process audio signals in real time, it is possible to process video signals in real time as a whole.

A particularly important example of application in video signal processing is high-efficiency coding technology that can increase the efficiency of transmission path usage. A typical example of this is the communication system study group material CS81- published by the Institute of Electronics and Communication Engineers on July 22, 1981.
There is a motion compensated interframe coding method published in 87. This method is based on taking the difference between an image one screen old and the currently input image, encoding this difference, and transmitting it, and the receiving side receives the difference image signal decoded from the received code. A new decoded screen is regenerated by adding one screen to the previous decoded screen.
For this reason, the above-mentioned image used on the transmitting side that is one screen old is input by reproducing the decoded image on the receiving side from the encoded signal in order to match the calculation result on the receiving side. The difference between the received image and the received image is generally calculated for the decoded image reproduced on the transmitting side. Particularly in motion-compensated interframe coding, the difference between an input partial image and a partial image whose position is shifted by the amount of motion in the decoded image is calculated. FIG. 2 shows this relationship and shows that by making the decoding partial image area Q wider than the encoding area O, it is possible to prepare images whose positions differ by the amount of movement.

It is also possible to filter the input image prior to encoding, but in this case the coordinates (i,
j) for the two-dimensional sampled signal x(i, j), 2
The signal y(l,j) in the encoding region O is passed through a filter with the dimensional impulse response {h(k,l)}.
If we obtain y(i,j)= 〓(k,l)εph(k,l)x(i
−k, j−l) (1). Here, the area P is P={(k, l): M≦k≦M, −M≦l≦M} (2) and the area of O is O={(i, j): −N≦i≦N , −N≦j≦N}
(3), then x(i, j) required to calculate equation (1)
The area Q of is Q={(i, j): −(N+M)≦i≦(N+M), −(N+M)≦i≦(N+M)} (4). Therefore, the input image is also shown in Figure 2.
As shown in the relationship between and Q, more input signals are required in the region Q than in the coding region O.

Therefore, one screen is divided into a plurality of partial screens, and a plurality of unit signal processors are assigned to process each partial screen, and each unit signal processor processes the input image signal of a wider area than the allocated partial screen. and decoded image signals, and when the capture is completed, each unit signal processor performs signal processing independently. Therefore, if each unit signal processor processes the assigned partial screen in 33 milliseconds, which is the one frame sample period mentioned above, and outputs the decoded partial image and code signal to the predetermined partial image area, Overall, real-time image processing becomes possible.

(Embodiments of the present invention) Next, embodiments of the present invention will be described with reference to the drawings. Figure 1 shows an embodiment of the present invention in which four unit signal processors are used, including a synchronization signal input line 1, a video signal input line 2, unit signal processors 3, 4, 5, and 6, and a video signal output line. 7 and an auxiliary video signal 8, and the unit signal processors 3, 4, 5, and 6 are respectively an acquisition section 10 and a processing section 1.
1, an output section 12, and a control section 13. The capture section 10 and the output section 12 are each two sets of storage circuits, and details of the processing section 11 and the control section 13 will be described later.

A synchronizing signal transmitted from the signal line 1 is input to the unit signal processors 3, 4, 5, 6 and the respective control sections 13. The control unit 13 identifies the point in time when a signal belonging to a pre-allocated capture partial screen area is transmitted to the video signal input line 2 and the auxiliary video signal line 8 based on the input synchronization signal, and transmits the signal to the capture unit 10 as a capture signal. Notify. The import unit 10 is a control unit 13
The input and auxiliary input signals transmitted through the signal line 2 and the signal line 8 are captured and stored by the captured signal transmitted from the signal line 2 and the signal line 8.

The control unit 13 also transmits an execution signal to the processing unit 11 when the video signal of a predetermined partial screen area to be captured has been input based on the synchronization signal inputted from the signal line 1. Predetermined digital signal processing is performed based on the input execution signal, for example, the input video signal stored in the capture unit 10 via the video signal input line 2 described above is processed by formula (1).
The convolution calculation is performed, and the difference between the decoded signal and the decoded signal stored in the capture unit 10 via the auxiliary video signal line 8 is taken and encoded, and the calculation result is divided into a coded signal and a decoded signal. Write to the output section 12.

The control unit 13 further detects a predetermined partial screen area output time based on the synchronization signal input from the terminal 1, and when the partial screen area is reached, transmits an output command signal to the output unit 12. The code signal is the processed data processed and written by the processing section 11 described above from the output command signal of the signal line 7.
The decoded signals are sequentially output to the signal line 8.

Figure 3 a to e, b', c', and d' are unit signal processors 3 in the video processor configured as shown in Figure 2.
4 shows the acquisition signal, execution signal, and output command signal used in 4. To simplify the explanation, the moving image signal used in FIG. 3 is assumed to have undergone scanning line conversion in which a normal scan signal covering the entire screen is rearranged for each partial screen. The synchronization signal (a) transmitted to the signal line 1 informs the start of one screen, and in the unit signal processor 3 that processes the first divided screen, the acquisition signal (b) generated by the control unit 13 is synchronized. It rises at the same time as the signal and continues commanding capture until the capture area ends. Furthermore, after the capture is completed, the control section 13 also sends an execution signal to the processing section 11.
Convey (c). The result processing unit 11 performs signal processing from the rise of the execution signal (c) to the next rise of the next acquisition signal (b). The control section 13 transmits an output command signal (d) to the output section 12. This output command signal can also be considered as a position signal of the processing partial screen of the unit signal processor 3. As explained in Figure 2, the captured partial screen is generally larger than the processed partial screen, so the time when signal (b) is on is longer than the signal (b) and (d) corresponding to each. (d) longer.

Signals (b'), (c'), and (d') are input signals, execution signals, and
This is an output command signal. The relationship between signals (b') and (d') results from the difference between the captured partial screen and the processed partial screen shown in FIG. The processing time allowed for the processing section 11 of the unit processor 4 is the execution signal (b')
This length is the same as the time allowed for the processing section 11 of the unit processor 3 from the rising edge of the output command signal to the rising edge of the output command signal.

Although the control signals for only unit processors 3 and 4 have been described in FIG. 3, the same applies to unit processors 5 and 6. Is each unit processor outputting only when each output command signal is on? Processed code signals and decoded video signals are output to signal lines 7 and 8 in Figure 1 in the format shown in Figure 3 e. be done. However, here A, B, C of signal (e),
The parts marked D mean the outputs from the unit signal processors 3, 4, 5, and 6, respectively. Therefore, the processed encoded signal and the decoded video signal are outputted to the signal lines 7 and 8 without interruption.

Figure 4 shows unit signal processors 3, 4, 5,
6, is an example of the control unit 13 used in
Synchronous signal input terminal 20, clock signal input terminal 2
1, Capture signal output terminal 22, Execution signal output terminal 2
3, Output command signal output terminal 24, Column counter 2
5, row counter 26, read-only memory 27, 2
8. Consists of gate circuits 29, 30, and 31.

The read-only memory 27 is programmed to output 3 bits, and the first bit is programmed to output 1 if the value of the input address matches the line number of the captured screen, and zero otherwise.The second bit is the input address. The program is programmed to output 1 if the value of is the line number on the screen at the time when you want to output the execution command, and zero otherwise.The third bit is programmed to output the line number of the processing screen when the value of the input address is 1 for those that match,
Others are programmed to output zero.

Similarly, the read-only memory 28 is programmed to output 3 bits, and the first bit is programmed to output 1 if the value of the input address matches the column number of the captured screen, and 0 otherwise. The 2nd bit is programmed to output 1 if the input address value corresponds to the column number on the screen at the time when you want to output the execution command, and 0 otherwise. It is programmed to output 1 for the column number that matches the column number on the processing screen, and 0 for the others.

When a synchronizing signal is input from terminal 20, column counter 25 and row counter 26 are reset and both output zero. Assuming that we are now considering the control section of the unit processor 3 that processes the first section in FIG. The third bit is "1" and the second bit is "0". Further, due to the value 0 of the row counter, the read-only memory 27 outputs "1" to the first bit indicating the captured screen and the third bit indicating the output screen, and the second bit is "0". Therefore, the gates 29, 30, and 31 each output "1" to the capture signal output terminal 22, "0" to the execution signal output terminal 23, and "1" to the output command output terminal 24.
Output. Every time a sampled video signal is applied to the terminal 2 in FIG. 1, a signal is applied to the clock terminal 21 in FIG.
is advanced one step and the column counter 25 returns to zero. Therefore, the first bit of the read-only memories 28 and 27 outputs "1" as long as the column counter 25 and the row counter 26 respectively indicate the column and row belonging to the captured screen, and the gate 29 outputs "1" as long as the column and row counters belonging to the captured screen are indicated. A "1" is output to the terminal 22 for the sample position belonging to the screen.

Similarly, the read-only memories 28 and 27 output "1" only when the column counter 25 and row counter 26 indicate the values of the column and row that should instruct the start of processing, and at this time the gate 30 outputs an execution signal to the terminal 23. as “1”
Output.

Similarly, when the column counter 25 and row counter 26 indicate the column and row corresponding to the output screen, the read-only memories 28 and 27 each output "1", and as a result, the gate 31 outputs "1" to the terminal 24 as an output command signal. Outputs 1”. FIG. 5 shows an embodiment of the processing section in the unit signal processors 3, 4, 5, and 6 shown in FIG.
3. Address output terminal 44 to the import section, output terminal 45 to the output section, address output terminal 4 to the output section
6. Write signal output terminal 47 to output section, execution signal input terminal 48, capture section output prohibition signal output terminal 49
It consists of It is assumed that the signal processor 40 uses μPD7720 manufactured by NEC, which is described in the second document of the present invention. μPD7720
is a signal processing processor that has internal multipliers and adders and a unique bus configuration, but the details are left in the second document. The μPD7720 can perform interrupt processing when a signal arrives at the interrupt input terminal (INT), and has programmable output bits P1 and P2. Input/output is performed via a bidirectional parallel bus (D), and if a signal is coming to the write terminal (W), it is used as an input direction bus.
If no signal comes to (W), it is used as the output direction bus.

Now, when an execution signal from the control section 13 in FIG. 1 is applied to the terminal 48 in FIG.
0 starts digital signal processing as an interrupt process. For this reason, input data from the import unit 10 of FIG. 1 is required, and first, the necessary address is prepared at port D and "1" is output from the bit output port P1. At this time, the gate 42 outputs "0", the data at port D can be output from the signal processor 40 to the outside, and the address is stored in the register 41. Next, when P1 is set to "0", the contents of the register 41 are transmitted to the acquisition section 10 via the terminal 44, and the corresponding data is input from the terminal 43 to the port "D".

Similarly, in order to transfer the processed data from the signal processor 40 to the output section 12, the output section 1
In order to specify an address to 2, the necessary address is prepared in port D, "1" is output from bit output port P1, and the address is written in register 41. This address is transmitted to the output section 12 via the output terminal 46. Next, prepare the processed data in port D and output “1” from bit output port P2.
Output. At this time, the gate 42 outputs "0", the signal processor 40 outputs from the port D to the outside, and in order to notify the input section that output is prohibited via the output terminal 49, the D port data is transmitted to the output section via terminal 45. “1” of bit output port P2 is terminal 47
is transmitted to the output section, and commands to write the data transmitted from the terminal 45 to the output section.

The present invention can be implemented in the manner described above.

In the embodiments described above, a read-only memory is used in the control unit, but it may also be replaced with a random access memory or the like to dynamically change the predetermined positions of the captured partial image and the processed partial image. It is part of the present invention.

Furthermore, in the present invention, each unit signal processor has a control unit that specifies the position of the captured partial image and the processed partial image, but these units can be centralized to send control signals to each unit signal processor. The present invention also includes a method of dispensing only .

Furthermore, although video encoding has been described as an example of an embodiment of the present invention, since the present invention is not limited to just video encoding, the output signal line 7 does not necessarily contain codes, and the auxiliary image signal line 8 does not necessarily contain decoding. The present invention also includes a case where the signal is not transmitted, but both are image signals.

Further, in the present invention, the sizes of the input video partial screen and the auxiliary image partial screen are the same, but a method of independently setting these sizes is also part of the present invention. In this case, the control section 13 requires two control signals for the input video partial screen and the auxiliary image section input screen to the capture section 10, and in this case, the ROM 27 and ROM 28 shown in FIG. The input control signal for the auxiliary image section can be generated by a gate that performs an AND operation on the 1-bit data that has been increased.

(Effects of the Present Invention) As seen above, according to the present invention, video signals are processed by digital signal processing at the boundaries between the unit signal processors without communicating with each other. Advanced digital signal processing can be achieved without any adverse effects. Therefore, by using many unit signal processors, real-time digital signal processing can be applied to video signals.

Also, the unit signal processors placed in parallel differ only in the designation of the acquisition screen and processing screen.
Since the processing section of each unit signal processor should be processed by the same digital signal processing program, it is only necessary to develop the program for a single signal processor, and the programs for other unit signal processors should be developed using the developed program. Since all you need to do is copy the program, programming becomes easier.

Furthermore, since only the capture screen and processing screen areas differ between unit signal processors, it is installed in parallel with many unit signal processors, prohibits the output of a unit signal processor that has caused a failure, and displays other spare units. Failures can be recovered by simply changing the definitions of the signal processor's capture screen and processing screen. Therefore, it can also be used as a highly reliable signal processing processor.

[Brief explanation of drawings]

Fig. 1 is a diagram showing an embodiment of the present invention, Fig. 2 is a diagram showing the principle of the invention, Fig. 3 is a diagram showing the operation timing of Fig. 1, and Fig. 4 is a part of Fig. 1. FIG. 5 is a diagram showing a part of FIG. 1. In the figure, 1... synchronization signal line, 2... video signal input line, 3, 4, 5, 6... unit signal processor, 7... output signal line, 8... auxiliary video signal line, 10... Intake unit, 11... Processing unit, 12...
Reading unit, 13 . . . is a control unit.

Claims (1)

[Claims] 1. A first control signal that indicates the position of a partial screen to be input in one screen determined by a synchronization signal that indicates the start of one screen of a video signal such as a television signal, and a second control signal that indicates the screen position that should be output. a control unit that generates a signal; the first control signal is input from the control unit; and a section specified by the first control signal is separately acquired from an input video signal and an auxiliary video signal that are input separately. an intake section for entering the
a processing section that performs signal processing on the input video signal and the auxiliary video signal captured by the capture section before the capture of the next screen starts; and a processing section that is connected to the output side of the processing section; The processed output video signal and output auxiliary video signal are stored, and the stored output video signal and output auxiliary video signal are separately output at a time specified by the first control signal inputted separately from the control unit. an input bus for supplying the synchronization signal and the input video signal to each of the plurality of unit processors; and an input bus configured to output from each of the plurality of unit processors. It is composed of an output bus that transmits the output video signal, and a feedback bus that collects the output auxiliary video signals output from each of the plurality of unit processors and transmits them as the auxiliary video signal to each of the plurality of unit processors. The screen comprising the input video signal and the screen comprising the fed-back auxiliary video signal are divided by allowing overlap, and each divided screen is subjected to dedicated processing. Real-time video processor.