JPH0433059B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an instruction fetching device in a high-speed information processing device.

[Prior Art] In recent years, high-speed information processing devices have developed an instruction buffer for reading the subsequent instruction sequence of the currently executed instruction sequence from a cache memory and temporarily storing it in parallel with the execution of the instruction. I often have it. Pipeline processing includes a series of processing stages corresponding to each process of fetching instructions from an instruction buffer, decoding instructions, and preparing operands, and processes instructions by sequentially passing them through the series of stages at the cycle of the machine cycle. is often done.

Conventionally, one method for fetching instructions in processing devices dedicated to scientific and technical calculations is to increase the capacity of the instruction buffer to, for example, several kilobytes, divide it into multiple blocks, and store the instructions in the instruction word area of the storage device. The instruction word to be decoded is transferred block by block to a block on the instruction buffer, and at the same time, means is provided for holding the instruction address of the instruction word held in each block of the instruction buffer for each block of the instruction buffer. There is a method in which a block number on the instruction buffer is obtained by searching the address of the address holding means using the instruction address of the word, and instructions are sequentially taken out from the block to the decode stage. Note that an address on the instruction buffer is different from an address in the main memory, and is composed of a block number on the instruction buffer, a word number within the block, and sometimes a word number within the word.

[Problems to be solved by the invention]

The problem with the above method is that when reading instructions in the order of their addresses on main memory, the instruction to be read moves from the last instruction of a certain block to the first instruction of another block. (Hereinafter, the case described on the left will be referred to as "block crossing.") When searching for a block beyond the block, there will be a delay in reading out the instruction words of other blocks. That is, since the correspondence table between the block number and the start address of the block is usually referred to, it takes time to extract the block number at the destination of the block. Therefore, if the next block number is determined after detecting from the value of the read address register that it is the last instruction in the block, there is a disadvantage that reading will be delayed.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an instruction fetching device which solves the above-described delay in fetching instructions when a block is exceeded.

[Means to solve problems]

In order to achieve the above object, the instruction fetching device of the present invention, in addition to the conventional instruction fetching method, uses a method in which the address of the instruction word read from a block on the instruction buffer is predetermined from the end of the block. It has a means for detecting whether it is located within the number of instructions.

That is, according to the present invention, there is an instruction buffer that holds instruction words read from a storage device in block units, and an address of the instruction word held in the block group corresponding to each block on this instruction buffer. an instruction counter that holds the upper bits of the address of the instruction word that is being read from the instruction buffer; and an instruction pointer that indicates the block number and address within the block of the instruction word that is being read from the instruction buffer. an instruction fetching device that detects from the value of the instruction pointer whether the address of the instruction word read from the block on the instruction buffer is located within a predetermined number of instructions from the end of the block; and when the detecting means detects that the address of the instruction word being read from the block on the instruction buffer is located within a predetermined number of instructions from the end of the block, the and means for adding +1 to the contents of the instruction counter and searching for a value in the address holding means that matches the added value of the instruction counter. An instruction fetching device is obtained which is characterized by determining a block number.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an instruction fetching device which is an embodiment of the present invention. In this embodiment, the instruction length is 4 bytes or 32 bits, and the logical address of the instruction is a 30-bit byte address.

In Figure 1, the instruction buffer 3 is 32 bytes x
It has a 64-word structure and is realized with a memory element that can be read and written simultaneously, and blocks 0, 1,
Use as 2 and 3. Each block contains one block of command information in cache memory.
512 bytes of information starting on a 512-byte boundary are loaded. The write data register 2 is a register for once receiving response information from the cache memory at the time of loading and writing it to the command buffer 3, and is 32 bytes long. The selector 4 selects one of the eight read output words of the instruction buffer 3, and the output is strobed into the 4-byte instruction register 5.

Head address registers 11 and 12 are head address registers for holding the upper 23 bits of the address of the instruction word held in block 0 to block 3 of instruction buffer 3, respectively.
Although some are omitted in FIG. 1, a total of four registers are provided corresponding to each block of the start address register instruction buffer 3.

The instruction counter 9 is set to the upper 23 bits of the address on the storage device of the instruction word being read from the instruction buffer 3 and the upper 23 bits of the initial value (hereinafter referred to as initial IC) of an instruction counter (not shown). It is a register. The value of the instruction counter 9 is compared with the start address registers 11 and 12 by comparators 13 and 14, respectively, and the block number in which the block destination instruction word is located is obtained from a match output. Here, the two counters input to the instruction buffer 3 will be explained.

FIG. 2A is a diagram showing the format of the read address counter (hereinafter referred to as "instruction pointer") 6 of the instruction buffer 3. Bits 0 and 1 are block numbers,
Bits 2 to 5 indicate the word number within the block, and bits 6 to 8 indicate the word number within the word. When the instruction words are sequentially read from the instruction buffer 3, the lower 7 bits of bits 2 to 8 are incremented by 1 every cycle.

FIG. 2b is a diagram showing the format of the write address counter 1 for the instruction buffer 3, and is the same as a in terms of format. Bits 0 and 1 are the block number, and bits 2-5 are the word number within the block. When instruction word information is being loaded from the main memory or cache memory to the instruction buffer 3, bits 2 to 5 are incremented by 1, and the instruction word information is sequentially written into the instruction buffer 3.

The control circuit 19 is a circuit that generates signals for reading and writing the instruction buffer 3, strobes the registers, and switches the input/output of the registers.

Next, the operation of the present instruction fetching device will be explained with reference to FIGS. 1 and 2. When the control circuit 19 receives an instruction to start fetching an instruction, it sets the upper 23 bits of the initial IC to the instruction counter 9 via the selector 8, and sets the lower 7 bits of the initial IC to the in-block word number part and word of the instruction pointer 6. Set in internal word number section.

At the time when the start instruction is received, no valid instruction words are loaded into the instruction buffer 3, and the validity display bits (V bits, not shown) corresponding to the start address registers 11 to 12 are all reset. state. Therefore, none of blocks 0 to 3 is hit, and a block load request is sent to a cache memory (not shown) using the value of instruction counter 9 as an access address. As the load destination block number, the smallest number is selected preferentially from among the blocks whose V bit is "0", so block 0 is initially selected.

When the control circuit 19 receives a response signal from the cache memory, it writes 32 bytes x 16 response information sent through the data line 20 into each word of block 0 of the command buffer 3. The information consists of 16 bytes starting with 32 bytes containing the request address information.
It will be sent back.

When the control circuit 19 receives the response signal from the cache memory, it sets the value of the instruction counter 9 in the start address register 11, and at the same time sets the V bit corresponding to this register. As a result, the output of the comparator 13 becomes "1", and the encoder 15 outputs the hit signal 16 and the block number signal 1.
7 is output.

The control circuit 19 sets the block number signal 17 in the block number portion of the instruction pointer 6, and thereafter sequentially counts the lower 7 bits of the counter by +1 (as mentioned earlier in the explanation of FIG. 2a). As a result, predetermined instruction words are sequentially read into the instruction register 5.

When the lower 7 bits of the instruction pointer 6 indicate 125, that is, when the address of the third instruction word from the end of the block is set, +1 is output from the detection circuit 7.
A select signal 18 is generated, which causes the selector 8
The instruction counter 9 outputs the output via the +1 adder 1
+1 is added by 0. The instruction pointer 6 is still accessing block 0, but the upper 23 bits of the address on the main memory of the instruction word have been previously set to the address of the instruction word beyond the block. Therefore, the value of instruction counter 9 is set to comparator 1.
3, 14 to start address register 11, 1
2, and the block number in which the next instruction word exists is determined by the matching output.

When the lower 7 bits of the instruction pointer 6 are incremented to all "0", that is, by the time when a block overtake occurs, the above-mentioned search for the block number to be overtaken is completed. Therefore, when a block is exceeded, the output of the encoder 15 is set to the upper two bits of the instruction pointer 6, and the instruction word at the destination of the block is read out without any delay.

If a block number beyond the block is searched and there is a miss, a request is issued to the cache memory after reading all the instruction words of block 0.

Figure 3 shows a time chart when passing a block. As can be seen from the figure, it is better to set the instruction counter 9 in advance to search for the next block number than in the case where the instruction counter 9 is not set in advance.
The instruction word ahead of the block can be read out in quick cycles.

In this embodiment, three machine cycles are required to process the block crossing. Therefore, + shown in Figure 3
If the 1 select signal is issued at least two instructions ahead of the last instruction in the block, the block can be processed without any problem. In a machine that generally requires N machine cycles to process a block, if a +1 select signal is issued and block crossing processing is started when the Nth instruction counting from the end of the block is being executed, the block will be processed. Crossings are handled without a hitch.

When the instruction counter 9 is incremented by the block crossing process, the execution address and the address indicated by the instruction counter 9 do not match until the block crossing process is completed. Therefore, in order to shorten this mismatch time as much as possible, the +1 select signal 18 is output from the timing when the Nth instruction counting from the end of the block is executed. In other words, N counting from the end of the block
When it is detected from the value of the instruction pointer 6 that the instruction is within the number of instructions, the value of the instruction counter 9 is incremented by one.

Even if the block crossing processing does not start at the timing when the Nth instruction is executed counting from the end of the block, if the +1 select signal 18 is issued before the timing when the instruction at the end of the block is executed,
The time required to cross a block is shorter than when the instruction counter 9 is not advanced.

From the above, generally speaking, it is necessary to detect that the block is located within a predetermined number of instructions from the end.

[Effects of the Invention] As described above, the present invention increases the processing speed of an information processing device including the instruction fetching device by fetching the instruction word beyond the block faster than the instruction buffer and supplying it to the execution stage. It has the effect of improving

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the entire instruction fetching device according to the present invention, FIG. 2 is a diagram showing the format of the instruction pointer 6 and the write address register 1 shown in FIG. 1, and FIG. These are time charts when the instruction counter 9 is not advanced and when it is advanced. Explanation of symbols: 1 is write address counter, 2 is write data register, 3 is instruction buffer, 4 is selector, 5 is instruction register, 6 is instruction pointer,
7 is a detection circuit, 8 is a selector, 9 is an instruction counter, 10 is a +1 adder, 11 or 12 are start address registers, 13 and 14 are comparators, 1
5 represents an encoder, and 19 represents a control circuit.

Claims (1)

[Claims] 1. An instruction buffer that holds instruction words read from a storage device in block units, and address holding means that holds addresses of instruction words held in the block group corresponding to each block on the instruction buffer; An instruction fetching device including an instruction counter that holds the upper bits of the address of the instruction word being read from the instruction buffer, and an instruction pointer indicating a block number and an address within the block of the instruction word being read from the instruction buffer. means for detecting from the value of the instruction pointer whether the address of the instruction word read from the block on the instruction buffer is located within a predetermined number of instructions from the end of the block; When it is detected by the means that the address of the instruction word being read from the block on the instruction buffer is located within a predetermined number of instructions from the end of the block, the contents of the instruction counter are incremented by +1. and means for searching for a value in the address holding means that matches the value of the added instruction counter,
An instruction fetching device characterized in that this determines the block number of a block that is continuous to the block in question from the address of the storage device.