JPH0433177B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a signal switching device for switching audio input signals from external audio input devices such as television receivers and stereo amplifiers.

2. Description of the Related Art In recent years, analog signal processing has been changing to digital signal processing, and digital signal processing has been introduced starting with relatively low frequency signals such as audio signals. The audio signals are switched using an analog method and converted into digital signals by an A/D converter.

An example of the conventional analog signal switching mentioned above will be described below with reference to the drawings.

FIG. 8 shows analog signal switching.
In FIG. 8, a number of inputs 44 are input to a switch 25 with a input and one output, and the output of the switch 25 is input to an A/D converter 27, where it is A/D converted and digitally converted to an output line 28. get the output. The switch 25 is controlled by a control circuit 26, and the position of the switch 25 is determined by a control signal input from a control line 29.

Problems to be Solved by the Invention However, in an analog signal switching circuit as shown in FIG. 8, as the number of input signals increases, the number of control signals increases. This is because each control signal is sent in the form of high level (H) or low level (L), so the number of inputs is 1 to 2.
1 line for 4 inputs or less, 3 lines for 8 inputs or less, 4 lines for 16 inputs or less...For i inputs or less,
log2i (2 ^l ≠ i), l・(2 ^l = i), and as the number of input signals increases, the control signal increases. If the signal generation parts are far apart, the number of wires to be connected will increase, which increases the cost of the wires, and the increase in the number of wires increases the complexity of the configuration and the complexity of the work. It had

Means for Solving the Problems In order to solve the above problems, the present invention inputs n analog signals to a first n-input 1-output switch circuit, and converts the output of the first switch circuit into a comparator. the output of the comparator is input to a D-flip-flop operating with a clock of period T ₁ , the output of the D-flip-flop is input to each of n D-flip-flops, and the output of the comparator is input to one of n D-flip-flops, - the outputs of the flip-flops are input to n integrators, respectively, and the outputs of the n integrators are input to a second n-input, one-output switch circuit;
The switch output of the second n-input and one-output is input to the other side of the above comparator, and the first switch and the second switch are configured to be switched synchronously by the switch control of the switch control/control pulse generation circuit. The switch control/control pulse generation circuit is controlled by the start pulse, and the above clock with period _T1 is input, and the switch control/control pulse generation circuit is controlled by the start pulse.
The control pulse generation circuit is configured to output n pulses having a different period by T ₁ of nT ₁ and supply each of these pulses as clock pulses to the n D-flip-flops. be.

Function According to the present invention, the comparator, the integrator, and the D-flip-flop basically constitute the ΔM according to the above-described configuration. Here, ΔM will be explained.

First, in Figures 5 and 6, the input signal [ei]
is input to the comparator 31 from the line 30 and compared with the comparison signal [ec] on the line 32,
Obtain the error signal [ee] of [ei-ec]. According to this error signal ee, the comparator 31
The comparator output signal is outputted to the top, and this comparator output signal is quantized by the D-FF 35 and the clock 36. Quantized D-FF3
The output of 5 becomes a 1-bit signal and is output to line 37, a part of which is passed through an integrator 38 to obtain a comparison signal [ec] as an output of the integrator 38, which is input to the comparator 31. That is, .DELTA.M is a method of quantizing the input signal ei while making the 1-bit output signal follow the output of the integrator 38.

The signal switching device of the present invention uses the ΔM type A/D converter as described above to convert n input signals into ΔM
A/D conversion is performed using the method, and the n input signals are treated as 1-bit quantized signals, and
For the 1-bit quantization, by outputting each of the n signals in time series, the three lines of the clock, start pulse, and 1-bit quantization output can be used to connect other processing stages. Input signals can be transmitted to.

Embodiment A signal switching device according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of a signal switching device according to an embodiment of the present invention. In FIG. 1, 1 is a n input signal, 2 is a switch with n inputs and 1 output, 3 is a comparator, 4 is a D-flip-flop (D-FF) operated by a clock applied from line 14, 5, 6, 7 and 8 are D-FFs, which operate with different control pulses for each phase. 9,1
0, 11 and 12 are integrators, 16 is a switch with n inputs and 1 output, and 18 is a control for switches 2 and 16 and D
- This is a switch control/control pulse generation circuit that generates control pulses for FF5, 6, 7, and 8. A start pulse is applied from line 15 to switch control/control pulse generation circuit 18.

Regarding the signal switching device configured as above,
The operation will be explained below using FIGS. 1 and 2.

First, the A/D conversion method of ΔM is the same as described in the function, D-FF4, D-FF8, D-FF4
and D-FF7, D-FF4 and D-FF6, D-FF4
and D-FF5 are the same as D-FF31 in FIG. 5 described in the operation section. D-FF4 is line 1
It is operated by the clock above 4, and D-FF8~D
-FF5 operates with pulses C ₁ to _Co , which have a period n times that of the clock, and the clock period differs by one period. Therefore, if the period of the clock is T ₁ , then
The pulse on line 17 operates at a period of nT ₁ , resulting in a sampling period of 1/nT ₁ . Therefore, the switches 2 and 16 with n inputs and 1 output are as shown in FIG.
When the comparator 3 is in the position (1) (see the states of switches 2 and 16 in Figure 2), the comparator 3 is in the position (1) of the input signal 1.
and the output signal of the integrator 12, and the result is expressed as D-
Input to FF4. D-FF4 uses a clock to sample the data at a period of _T1 and outputs it on line 13. The output signal is D-FF8
is latched by the control pulse _C1 and input to the integrator 12 for integration. This integrator 12 holds the integrated output until the next data arrives.

Next, when the states of switches 2 and 16 become state (2), comparator 3 compares (2) of input signal 1 with the output signal of integrator 11, and inputs the result to D-FF4. D-FF4 uses a clock to sample the data at a period of _T1 and sends an output to line 13. The same thing is done up to the integrator n as described above, and the switch control/control pulse generation circuit 18 is reset by the start pulse shown in FIGS. 1 and 2, and the same thing is done from input signal (1). As a result, input signal 1 (1) to (n) are each sampled at a sampling period of nT ₁ , and as shown in the bottom diagram of Figure 2, the data sampled at a period of T ₁ of the clock is (1). ), (n) and become a 1-bit signal, which becomes the output of the D-FF 4 and is transmitted to the next stage.

The data on line 13 transmitted in the above state is received on the receiving side, and if there is a clock and start pulse, control pulses C ₁ to _{C o} are generated from the clock and start pulse in the same way as above, and D-FF By passing through it, you can obtain a signal that is ΔM of the input signal. Its block diagram is shown in FIG. This third
4, the output data of D-FF4 and the clock and start pulse signals from FIG. 1 are input to D-FF20, the clock and start pulse are input to the control section 24, and The control unit 24 generates a control pulse with the same timing as C _k among the control pulses of
Enter 20. In this way, the data of the D-FF output k of period nT ₁ in FIG. 4 is reproduced, and by integrating it with the integrator 21, the original input signal 1 (k) in FIG. 1 can be reproduced.

In addition, the output of the D-FF 20 in FIG. 3 is transferred to a digital integrator 39 and a digital LPF as shown in FIG.
40, switch 41, and quantization circuit 42 to perform digital conversion, the output line 43
Since a PCM code is obtained, it is also possible to perform digital signal processing on the signal. Regarding this conversion circuit, please refer to [{Good man, DJ: The
APPLICATION OF DELTA MODULATION TO ANALOG TOPCM ENCODING
modulation to Analog to PCM encoding”,)
Bell System Technology (Bell Syst.Tech.)
J., 48, 2, PP.321-342 (Feb.1969)}, {“Applications of Digital Signal Processing” edited by Institute of Electronics and Communication Engineers, PP144.
(May 20, 1981)] is introduced in detail.

Effects of the Invention As described above, according to the present invention, an analog signal can be converted into a 1-bit ΔM signal using ΔM,
The ΔM signal is a digital circuit and can be converted into a PCM signal.
Digital signal processing can be performed, and as described in the example, three signals, data, clock, and start pulse, can be processed.
It is possible to transmit n input signals using a main line, and on the receiver side, create an appropriate control pulse and use D-FF to easily extract one signal from among the n input signals. , and the ΔM reproduced through simple digital processing can be converted into PCM and signal processed. In addition, the block shown in Figure 1 can be easily integrated into an IC, and the analog part consists of a switch, comparator, and integrator, and everything else can be constructed from digital circuits, so it can be manufactured at a lower cost than a normal A/D converter. It also has the advantage of being able to

[Brief explanation of drawings]

FIG. 1 is a block diagram of a signal switching device according to an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of FIG. 1, and FIGS. 3 and 4 are block diagrams of ΔM analog conversion means and Timing chart for explaining operation, Figure 5 is a block diagram of the ΔMPCM conversion means, Figures 6 and 7.
The figure is a block diagram showing the principle configuration of ΔM and a waveform diagram for explaining the operation, and FIG. 8 is a block diagram of a conventional signal switching device. 2...n input 1 output switch, 3...comparator, 4...D-FF(0), 5...D-FF(n),
6...D-FF(n-1), 7...D-FF(2), 8...
...D-FF(1), 9... Integrator (n), 10... Integrator (n-1), 11... Integrator (2), 12... Integrator
(1), 16...n input 1 output switch, 18... switch control/control pulse generation circuit.

Claims (1)

[Claims] 1 Input n analog signals to the first n-input 1-output switch circuit, input the output of the first switch circuit to one of the comparators, and operate the output of the comparator with a clock of period T _1. The outputs of the D-flip-flops are input to n D-flip-flops, the outputs of the n D-flip-flops are input to n integrators, and the outputs of the n D-flip-flops are input to n integrators. The output of the switch is inputted to a second n-input 1-output switch circuit, the second n-input 1-output switch output is inputted to the other of the comparators, and the first switch and the second switch are connected to the switch circuit. The switch control/control pulse generation circuit is configured to be switched synchronously by the switch control of the control/control pulse generation circuit, and the switch control/control pulse generation circuit is controlled by the start pulse, and the clock with the above period _T1 is input, and the switch control/control pulse generation circuit is controlled by the start pulse. The control pulse generation circuit has a period nT ₁ of T ₁
By outputting n pulses with different periods and supplying these pulses as clock pulses to the n D-flip-flops, the period output from the switch control/control pulse generation circuit is determined.
A signal switching device characterized in that signals are switched by using one of n pulses of _nT1 as a control pulse C _K and latching the output of a D-flip-flop operating with a clock of period _T1 .