JPH0434327B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a complementary signal output circuit that obtains complementary signals that are in phase and in opposite phase to an input signal.

(Prior Art) FIG. 9 is a diagram showing the configuration of a complementary signal output circuit for obtaining complementary signals that are used as clock signals for logic circuits and have opposite phases to each other.

The complementary signal output circuit shown in FIG. 9 is, for example,
It consists of inverter circuits I ₁ to I ₄ made of CMOS, and the input signal (IN) is sent to the inverter circuit.
The output of inverter circuit I ₁ is inverted by inverter circuit I ₂ , and the output of inverter circuit _{I 2 is} inverted by inverter circuit I ₃ , so that the output of inverter circuit I ₃ is It is obtained as a complementary signal φ having an opposite phase to the input signal. On the other hand, the output of the inverter circuit I ₁ is inverted by the inverter circuit I ₄ to obtain the output of the inverter circuit I ₄ as a complementary signal φ having the same phase as the input signal.

Therefore, in such a configuration, the complementary signal φ is obtained by the odd-numbered stages of inverter circuits I ₁ , I ₂ , and I ₃ connected in cascade with respect to the input signal, whereas the complementary signal φ The signal φ is obtained by an even number of stages of inverter circuits I ₁ and I ₄ cascade-connected to the input signal. In other words, the complementary signal φ is output with a delay time of two inverter circuit stages relative to the input signal, whereas the complementary signal φ is output with a delay time of three stages of inverter circuits relative to the input signal. Therefore, as shown in the operational waveform diagram of FIG. 10, the complementary signal φ is delayed by one stage of the inverter circuit compared to the complementary signal φ.

(Problems to be Solved by the Invention) As explained above, in the complementary signal output circuit as shown in FIG. φ is a complementary signal φ and a complementary signal φ, since the input signal is provided through inverter circuits with different numbers of stages.
There was a problem that the switching time was different.

The present invention has been made in view of the above, and its purpose is to simplify the switching time for input signals of a complementary signal that is in phase with the input signal and a complementary signal that is in opposite phase to the input signal. It is an object of the present invention to provide a complementary signal output circuit that can have the same configuration.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention receives an input signal at the first stage of inverting circuits among a plurality of inverting circuits connected in series. A complementary signal output circuit that provides a complementary signal that is in phase with the input signal to the output terminal of the inverting circuit in each stage, and a complementary signal that is in phase opposite to the input signal to the output terminal of the inverting circuit in the odd-numbered stage is used. A transistor connected between the output terminal of the even-numbered inverting circuit and the power supply and/or a transistor in the odd-numbered stage whose conduction is controlled by a signal having a phase opposite to the input signal. It consists of a transistor connected between the output terminal of the inverting circuit and the power supply.

(Function) In the above configuration, the present invention controls the conduction of the transistor connected between the output end of the even-numbered inversion circuit and the power supply by a signal in phase with the input, or the inversion circuit of the odd-numbered stage. By controlling the conduction of the transistor connected between the output end of the circuit and the power supply using a signal that is in phase opposite to the input signal, the switching operation of one or both of the complementary signals that are in phase opposite to each other is compensated for. .

(Example) Hereinafter, an example of the present invention will be described using the drawings.

FIG. 1 is a diagram showing the configuration of a complementary signal output circuit according to an embodiment of the present invention.

The complementary signal output circuit shown in FIG. 1 includes cascade-connected inverter circuits I ₅ , I ₆ , I ₇ and an NPN bipolar transistor Q1, and the load of complementary signals φ and φ is relatively low. This figure shows the configuration when the weight is light.

Inverter circuit _I5 receives an input signal (IN), inverts it, and provides its output to inverter circuit _I6 . Inverter circuit _I6 receives and inverts the output of inverter circuit _I5 , and provides a complementary signal φ that is in phase with the input signal. Inverter circuit I ₇
receives the complementary signal φ that is the output of the inverter circuit _I6 , inverts it, and provides a complementary signal φ having an opposite phase to the input signal.

The bipolar transistor Q1 has its base connected to the output end of the inverter circuit _I5 via a current limiting resistor R, its collector connected to the power supply, and its emitter connected to the output end of the inverter circuit _I7 . There is.

In such a configuration, when the input signal falls from a high level state to a low level state, the output of the inverter circuit _I5 changes from a low level state to a high level state. When the output of the inverter circuit _I5 shifts from the low level state to the high level state, the output of the inverter circuit _I5 is inverted by the inverter circuit _I6 , and the complementary signal φ falls from the high level state to the low level state.

On the other hand, when the output of the inverter circuit _I5 rises from a low level state to a high level state, the bipolar transistor Q1 changes from a non-conductive state to a conductive state. As a result, the complementary signal φ begins to rise from a low level state to a high level state. Then, the output of the inverter circuit _I6 , that is, the complementary signal φ
When goes from a high level state to a low level state,
The complementary signal φ is inverted by the inverter circuit _I7 , and the rising of the complementary signal φ from the low level state to the high level state is also performed in the inverter circuit _I7 .

In other words, the falling of complementary signal φ and the falling of complementary signal φ
The start-up of both will begin to be performed by the output of the inverter circuit _I5 . Therefore, the time difference (skew) between the rising edge of the complementary signal φ and the falling edge of the complementary signal φ becomes smaller than the skew of the complementary signals φ and φ obtained in the complementary signal output circuit shown in FIG. It can be made significantly smaller.

Further, the delay time of the complementary signal φ with respect to the input signal is approximately the delay time of two stages of inverter circuits, and can be made faster than the complementary signal φ obtained in the configuration shown in FIG.

FIG. 2 is a diagram showing an example in which the inverter circuits I ₅ , I ₆ , and I ₇ forming the complementary signal output circuit shown in FIG. 1 are constructed using CMOS.

In Fig. 2, inverter circuit I ₅ is PMOSP
The inverter circuit _I6 is composed of PMOSP2 and NMOSN2, and the inverter circuit _I7 is composed of PMOSP3 and NMOSN1.
It is composed of 3.

Even in this configuration, the same effect as shown in Fig. 1 can be obtained, and by configuring the inverter circuits I ₅ , I ₆ , and I ₇ with CMOS, it is possible to reduce power consumption. I can do it.

FIG. 3 is a diagram showing the configuration of a complementary signal output circuit in which inverter circuits I ₅ , I ₆ , and I ₇ are constructed of CMOS similarly to the complementary signal output circuit shown in FIG. 2.

The complementary signal output circuit shown in FIG. 3 is different from the complementary signal output circuit shown in _FIG.
The difference is that NMOSN4, whose conduction is controlled by an input signal, is connected between NMOSN3 and the ground, and the other configurations are the same as in Fig. 2.
They are indicated with the same reference numerals.

The features of this complementary signal output circuit are as follows:
In the complementary signal output circuit shown in FIG. 2, after the output of the inverter circuit _I5 changes from a low level state to a high level state, until NMOSN3 changes from a conductive state to a non-conductive state, bipolar transistors Q1 and NMOSN3 There is a period when both are in a conductive state, and during this period, the normal current flowing from the power supply to the ground via bipolar transistors Q1 and NMOSN3 is reduced when the input signal falls from a high level state to a low level state.
This is prevented by changing the NMOSN4 from a conductive state to a non-conductive state.

Therefore, even in such a configuration, it is possible to reduce the skew between the rising edge of the complementary signal φ and the falling edge of the complementary signal φ with respect to the falling edge of the input signal.

FIG. 4 is a circuit diagram showing the configuration of a complementary signal output circuit according to another embodiment of the invention. The complementary signal output circuit shown in the figure consists of an inverter circuit _I8 and a CMOS
It consists of Note that in the embodiments described below, components with the same reference numerals have the same functions, and their explanations will be omitted.

In FIG. 4, the output of the inverter circuit _I8 that receives and inverts the input signal (IN) includes a PMOSP5 whose gate terminal is connected to the output of the inverter circuit _I8 and whose source terminal is connected to the power supply. It consists of an NMOSN5 whose gate terminal is connected to the output of the inverter circuit _I8 and whose source terminal is connected to the ground, and an inverter circuit _I9 that outputs a complementary signal φ from mutually connected drain terminals. The output of this inverter circuit _I9 is connected to the source of NMOSN6, whose gate terminal is given an input signal and whose drain terminal is connected to the power supply.The output of this inverter circuit I9 is also connected to the source of NMOSN6, whose gate terminal is given an input signal and whose drain terminal is connected to the power supply. connected to
The source terminal of PMOSP6 is connected.

In addition, the input of the inverter circuit _I8 is connected to a PMOSP7 whose respective gate terminals receive an input signal and whose respective drain terminals are connected to each other.
An inverter circuit _I10 is connected thereto, which outputs a complementary signal φ from mutually connected drain terminals. This inverter circuit I ₁₀
The output of the inverter circuit I _{8 has its gate terminal connected to the output of the inverter circuit I 8} and its drain terminal connected to the power supply.
The source terminal of NMOSN8 is connected, the gate terminal is connected to the output of inverter circuit _I8 , and the drain terminal is connected to ground.
The source terminal of PMOSP8 is connected.

In such a configuration, first, a case where the input signal rises from a low level to a high level will be described.

When the input signal starts to rise from low level to high level, NMOSN6 and N7 become conductive, and as a result, complementary signal φ starts to rise from low level to high level, and at the same time, complementary signal φ falls from high level to low level. start. Then, when the output of the inverter circuit _I8 changes from high level to low level, PMOSP5,
P8 becomes conductive. Therefore, the rising speed of the complementary signal φ and the falling speed of the complementary signal φ become faster, and the rising and falling waveforms become sharp. Furthermore, the complementary signal φ is raised to the power supply potential by PMOSP5.

Next, a case where the input signal falls from high level to low level will be explained. When the input signal starts to fall from high level to low level,
PMOSP6 and P7 become conductive, so that the complementary signal φ starts to fall from high level to low level, and at the same time, complementary signal φ starts to rise from low level to high level. Then, when the output of the inverter circuit _I8 changes from low level to high level, NMOSN5 and N8 become conductive. Therefore, the rising speed of the complementary signal φ and the falling speed of the complementary signal φ become faster, and the rising and falling waveforms become sharp.

In this way, one complementary signal is not used as an input signal to obtain the other complementary signal, but NMOSN6, N7 or PMOSP6, P7 are made conductive at the same time with respect to the input signal, and the input signal IN
After a delay time of one stage of inverter circuit for
Since PMOSP5, P8 or NMOSN5, N8 are made conductive at the same time, complementary signals φ,
It becomes possible to substantially match the potentials at the intersections at the rising and falling points of φ, and it becomes possible to make the switching times of the complementary signals φ and φ with respect to the input signal substantially the same. Furthermore, since the PMOSP8 and NMOSN8 are provided at the output of the inverter circuit _I10 , the rising and falling waveforms of the complementary signal φ can be sharpened.

FIG. 5 is a circuit diagram showing the configuration of a complementary signal output circuit according to still another embodiment of the present invention. The complementary signal output circuit shown in the figure is composed of inverter circuits I ₈ , I ₉ , I ₁₀ shown in FIG. 4 and NPN type bipolar transistors (hereinafter referred to as "BT") Q2 and Q3.

In Fig. 5, BTQ2 has an input signal applied to its base terminal, a collector terminal connected to a power supply, and an emitter terminal connected to an inverter circuit _I9 .
connected to the output end of the This BTQ2 is controlled to be conductive by an input signal, and causes the complementary signal φ to rise.

BTQ3 has an inverter circuit at its base terminal.
It is connected to the output terminal of _I8 , the collector terminal is connected to the power supply, and the emitter terminal is connected to the inverter circuit.
Connected to the output end of I ₁₀ . This BTQ3 is
Continuity is controlled by the output of inverter circuit _I8 ,
This is used to raise the complementary signal φ.

In this configuration, when the input signal starts rising from low level to high level, BTQ
2 and NMOSN7 become conductive, the complementary signal φ starts to rise, and the complementary signal φ starts to fall. Then, when the output of inverter circuit _I8 falls from high level to low level, PMOSP5
becomes conductive, causing the complementary signal φ to rise. In this way, when the input signal rises,
While NMOSN7 becomes conductive,
PMOSP5 becomes conductive after a delay time of one stage of inverter circuit _I8 , but in order to compensate for this delay, BTQ2 is made conductive by the rising edge of the input signal, and complementary signal φ is raised. ing.

Next, when the input signal starts to fall from high level to low level, PMOSP7 becomes conductive and complementary signal φ starts to rise. Then, when the output of the inverter circuit _I8 changes from low level to high level, NMOSN5 becomes conductive and the complementary signal φ starts to fall. Furthermore, at the same time, BTQ3 becomes conductive and causes the complementary signal φ to rise.

FIG. 6 is a diagram showing a simulation result of complementary signals φ and φ with respect to the input signal in the circuit shown in FIG. As shown in FIG. 6, even in the circuit configuration shown in FIG.
It becomes possible to substantially match the potentials at the intersections of the respective rising and falling edges of φ, and the switching times can be made substantially the same. Furthermore, since bipolar transistors for raising the complementary signals φ and φ are provided at the output ends of the inverter circuits I ₉ and I ₁₀ , the high current drive capability of the bipolar transistors allows the complementary signals φ to be applied even under high loads. , φ can be sharpened.

FIG. 7 is a circuit diagram showing the configuration of a complementary signal output circuit according to still another embodiment of the present invention. The complementary signal output circuit shown in _{FIG .} BTQ4 and
BTQ5 is installed and inverter circuit _I8 is PMOSP10
and NMOSN10.
Furthermore, this complementary signal output circuit
is applied to the input of the inverter circuit I ₈ via the input circuit 11, so that a complementary signal φ having the opposite phase to the input signal is obtained from the output of the inverter circuit I ₉ , and a complementary signal φ having the opposite phase to the input signal is obtained from the output end of the inverter circuit I ₁₀ . A complementary signal φ is obtained.

The input circuit 11 includes PMOSP11, P12,
It is composed of NMOSN11, N12 and BTQ6, and when the input signal goes from high level to low level, PMOSP11, P12 and BTQ6 become conductive and give a high level complementary signal to the input of inverter circuit _I8 . Also, when the input signal goes from low level to high level, NMOSN11,
N12 becomes conductive and provides a low-level complementary signal to the input of the inverter circuit _I8 . That is,
The input circuit 11 provides a signal obtained by inverting the input signal to the input of the inverter circuit _I8 .

BTQ4 is connected between the output end of the inverter circuit I ₉ and the ground, and its base terminal is connected to the connection point of NMOSN13 and N14 connected in series between the output end of the inverter circuit I ₈ and the ground. There is. NMOSN13 is controlled to be conductive by the output of the inverter circuit _I8 , and NMOSN14 is controlled to be conductive by the output of the input circuit 11.

BTQ5 was connected between the output end of the inverter circuit I ₁₀ and the ground, and its base terminal was connected in series between the inverter circuit I ₁₀ and the ground.
Connected to the connection point of NMOSN15 and N16. The conduction of NMOSN15 is controlled by the output of the input circuit 11, and the conduction of NMOSN16 is controlled by the output of the inverter circuit _I8 .

In such a configuration, the basic operation is similar to that shown in FIG.
At the falling edge of , BTQ4 and BTQ5 operate to speed up the falling speed of complementary signals φ and φ.

That is, when the input signal rises from low level to high level, NMOSN5 becomes conductive, and at the same time as the complementary signal φ starts to fall,
NMOSN13 becomes conductive and NMOSN14 becomes non-conductive. This prevents the load (not shown) from
A current flows to the base of BTQ4 via NMOSN13, BTQ4 becomes conductive, and the falling speed of the complementary signal φ is accelerated.

Also, when the input signal falls from high level to low level, NMOSN7 becomes conductive.
Complementary signal φ starts to fall, NMOSN15
is in a conductive state, and NMOSN16 is in a non-conductive state.
As a result, BTQ5 becomes conductive in the same manner as described above, and the fall speed of the complementary signal φ is increased.

Therefore, by adopting such a configuration, in addition to being able to obtain the same effect as that obtained in the complementary signal output circuit shown in FIG. 5, the complementary signals φ, The rising and falling waveforms of φ can be sharpened.

FIG. 8 is a circuit diagram showing the configuration of a complementary signal output circuit according to still another embodiment of the invention. The feature of this embodiment is that in the complementary signal output circuit shown in FIG.
Conduction is controlled by an input signal between NMOSN5 and ground in order to prevent through current from flowing to ground via NMOSN5.
This is due to the insertion of NMOSN17.

When the input signal falls from a high level to a low level, BTQ2 becomes conductive due to the high level output of the input circuit 11.
NMOSN5 becomes non-conductive after a delay time corresponding to one stage of inverter circuit _I8 of the output of input circuit 11. Therefore, BTQ2 and NMOSN5 temporarily become conductive at the same time. Therefore, when the input signal falls from high level to low level,
NMOSN17 is made non-conductive before BTQ2 becomes conductive to prevent through current.

Note that in the above embodiments, the inverter circuit is not limited to a CMOS configuration consisting of PMOS and NMOS, and may be configured, for example, of NMOS and resistor or only NMOS. Of course, even with such a configuration, similar effects can be obtained. Therefore, the present invention is not limited to the above embodiments, but can be implemented in other embodiments by making appropriate design changes.

[Effects of the Invention] As explained above, according to the present invention, the transistor connected between the output terminal of the even-numbered inversion circuit and the power supply and the output terminal of the odd-numbered inversion circuit and the power supply By one or both of the transistors connected between
Since the switching operation of one or both of the complementary signals is supplemented, it is possible to make the switching time of each complementary signal to the input signal comparable with a simple configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a complementary signal output circuit according to an embodiment of the present invention, FIGS. 2 and 3 are circuit diagrams showing a specific configuration of the complementary signal output circuit shown in FIG. 1, and FIG. 5, 7, and 8 are circuit diagrams showing the configuration of complementary signal output circuits according to other embodiments of the present invention, and FIG. 6 is the operating waveform of the complementary signal output circuit shown in FIG. 5. 9 is a diagram showing a configuration of a conventional complementary signal output circuit, and FIG. 10 is an operation waveform diagram of the complementary signal output circuit shown in FIG. _I1 to _I10 ...Inverter circuit, Q1 to Q6...Bipolar transistor.

Claims (1)

[Claims] 1. An input signal is received by the first inverting circuit among multiple inverting circuits connected in series, a complementary signal in phase with the input signal is applied to the output terminal of the even-numbered inverting circuit, and a complementary signal is applied to the output terminal of the even-numbered inverting circuit, and A complementary signal output circuit that provides a complementary signal with the opposite phase to the input signal at the output terminal,
A transistor whose conduction is controlled by a signal in phase with the input signal and connected between the output terminal of the even-numbered inversion circuit and the power supply, and/or a transistor whose conduction is controlled by a signal in phase opposite to the input signal. A complementary signal output circuit comprising a transistor connected between an output terminal of the odd-numbered inversion circuit and a power supply.