JPH0434333B2 - - Google Patents

Description

[Detailed description of the invention]

[Summary] In order to decode multiple types of systematic codes with different constraint lengths by one sequential decoder, the effective number of stages of the delay circuit of the internal encoder can be selected according to the constraint length of the received signal. did. [Industrial Application Field] The present invention relates to an improvement in a sequential decoder for decoding a systematic code, which is a type of convolutional code having an error correction function and used in satellite communications. [Prior Art] Fig. 4 is for explaining a systematic encoder that generates a systematic code, and its configuration consists of a delay circuit consisting of, for example, four shift registers connected in cascade and each delaying one bit period. 41-44 and 2
It is equipped with two Modulo 2 adders 45 and 46, and the transmission signal is transmitted bit by bit to the delay circuit 41 at the first stage.
and its output is sent out as a signal bit. On the other hand, parity bits are generated from the transmitted signal delayed by the delay circuit to correct errors occurring during the transmission of signal bits on the receiving side. ”, delay circuits 41, 42 and 4 are used to perform modulo 2 addition of the signal bit, the previously transmitted signal bit, and the previously transmitted signal bit.
Adders 45 and 46 perform modulo 2 addition of the output bits of 4. The table below shows the parity bits based on the above generation matrix generated by adding the transmitted signals delayed by the respective delay circuits and the modulo 2 adders 45 and 46.

[Problem that the invention seeks to solve]

In the transmission method that performs the above processing,
When the transmission speed on the line is low, the time available for data processing in the decoder is long, so there is no possibility that a large amount of unprocessed data will overflow in the buffer, and the error correction ability will be reduced. It is possible to reduce the overall error rate by using a long code with a large constraint length, but when the transmission speed is high, the number of path searches per decoded data must be reduced because it is necessary to increase the data processing speed. Therefore, there are many decoding errors, and each time an error occurs, it takes longer processing time to match the contents of the shift registers in the encoder and decoder, resulting in a significant overflow in the buffer register. , the overall error rate is lowered by using a code with a short constraint length, which makes it easier to match the contents of the shift register. The configuration of the internal encoder in a conventional sequential decoder uses only one pair of codes, as shown in Figure 4 quoted above, and minimizes the error rate in accordance with the transmission speed of the line. It was not possible to select the sign of the constraint length externally. The present invention makes it possible to use codes with different constraint lengths, such as using a code with a long constraint length when the transmission speed of the line is low, and a code with a short constraint length when the transmission speed of the line is high. The present invention aims to provide a sequential decoder capable of decoding codes having different constraint lengths. [Means for solving the problem] FIG. 1 is a diagram showing the principle of the present invention, and shows a bidirectional shift register 1 consisting of a plurality of registers 1 ₁ , 1 ₂ , ... 1n, and a parity generation matrix. In a sequential decoder including an internal encoder equipped with a modulo 2 adder 2 that adds the outputs of stages selected from each stage of this shift register 1 in accordance with the formula 2, this shift register receives a plurality of types. The output from the delay circuit defined by the parity generation determinant in the 1-bit time delay circuit, which has the number of stages equal to the maximum constraint length in the systematic code and has the number of stages corresponding to the constraint length of the received signal, is expressed as above. Addition is now performed in the MODULO2 adder. As a mode of implementing this configuration, the output from the stage determined by the parity generation determinant in the bidirectional shift register whose number of stages corresponds to the constraint length of the received signal is supplied to this adder via the opening/closing means 23. or modulo 2 adder 3
3 ₁ , 33 ₂ , ... are provided to perform modulo-2 addition corresponding to the respective constraint lengths and determinants of the signals to be received, and the outputs of these modulo-2 adders are selected and output. can do. [Operation] The first stage register 11 of the bidirectional shift register 1 consists of registers 1 ₁ , 1 ₂ , . . . _1n whose number of stages corresponds to the maximum constraint length of the systematic code to be decoded. Register 1 ₂ ...1n
The previously decoded data are respectively stored in the register 11, and when correct decoding is performed, these data are sequentially shifted to the right in the figure, and the next received data is stored in the register ₁₁ . If the decoded data is incorrect, the last stage 1n of this shift register is loaded with previously decoded data from the path memory 5 that stores the decoded data, and stored in other stages. The data is sequentially shifted to the left of the diagram. For example, if the constraint length is 3 and the generation determinant is "111", the data from registers 1 ₃ , 1 ₂ , 1 ₁ is supplied to the modulo 2 adder. and modulo 2 addition is performed to generate parity bits.
Note that the signal bit received this time is output from the register ₁₁ . If the constraint length of the systematic code to be decoded is 4, registers 1 ₁ , ~ of bidirectional shift register 1
The data from the register at the position where "1" stands in the generation determinant from ₁₄ is modulo-2 added by the modulo-2 adder 2 to generate a parity bit. In the present invention, since a bidirectional shift register with a number of stages equal to the constraint length of the systematic code having the longest constraint length among the systematic codes to be decoded is used, a systematic code having a constraint length equal to or shorter than that is used. There is no need to separately prepare a bidirectional shift register for decoding. [Embodiment] FIG. 2 shows an embodiment of the present invention, in which the bidirectional shift register 21, path memory 22, and EOR circuit 27 are the bidirectional shift register 1, path memory 2, and modulo 2 addition shown in FIG. 1, respectively. In this figure, the bidirectional shift register 1, which corresponds to the device 2, is composed of five stages of registers 21 ₀ to 21 ₄ so as to be able to decode a systematic code with a constraint length of 5 or less. The data stored in the first-stage register ₂₁₀ is always supplied to one input terminal of the EOR circuit 27, assuming that "1" is used in the parity bit generation determinant, and is supplied to one input terminal of the EOR circuit ₂₇ .
The data from ~ ₂₁₄ is sent to this EOR circuit 2 via AND circuits ₂₃₁ to ₂₃₄ , which are opening/closing means.
7 other input terminals. The other input terminals of the AND circuits 23 ₁ to 23 ₄ that are not connected to the register 21 are applied with a potential corresponding to “1” from the power supply 26 via the resistors 25 ₁ to 25 ₄ , respectively. The input terminals are set to a ground potential corresponding to "0" by dip switches 24 ₁ to 24 ₄ so that the AND circuit 23 can be selectively turned off. The illustrated connection state of the deep switch 24 shows a case where the constraint length is 4 and the generation determinant is "1011", the most significant digit of which corresponds to the register ₂₁₄ , which is the constraint of the systematic code to be decoded. If the length and the generating determinant are different from this, by selectively closing the switch 24, shown as a dip switch, from the registers ₂₁₁ to ₂₁₄ .
Data supplied to the input terminal of the EOR circuit 27 can be selectively turned on or off by the AND circuit 23 to generate parity bits for the systematic code to be decoded. FIG. 3 shows another embodiment of the present invention, in which a bidirectional shift register 31 and registers ₃₁₀ to ₃₁₄ constituting this shift register are similar to the bidirectional shift register 21 and register 21 in FIG.
₀ to ₂₁₄ , and the path memory 32 is also the same as the path memory 22 in FIG. In this example, two EORs are used to generate parity bits for two types of systematic codes.
Circuits 33 ₁ and 33 ₂ are provided, and a first
The EOR circuit 33 ₁ is the register 31 ₃ , 31 ₁ , 31 ₀
The second EOR circuit ₃₃₂ generates parity bits for the systematic code of constraint length 4 and generation determinant "1011" using the data from register 3.
Using the data from 1 ₄ , 31 ₂ , 31 ₁ , and 31 ₀ , parity bits are generated for the systematic code of constraint length 5 and generation determinant "10111". The parity bits output from these EOR circuits 33 ₁ and 33 ₂ are obtained by selecting the output of the EOR circuit 33 that generates parity bits for the systematic code that is actually being decoded by the selector 34. It will be done. [Effects of the Invention] According to the present invention, the number of stages of the registers constituting the bidirectional shift register is equal to the constraint length of the systematic code having the maximum constraint length among the systematic codes that may be decoded. Moreover, since the parity bits can be obtained by selectively adding modulo 2 to the data stored in these registers, there is no need to prepare separate decoders for each systematic code with a different constraint length. effect can be achieved.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIGS. 2 and 3 are diagrams showing different embodiments of the present invention, and FIG.
The figure shows an example of a systematic encoder. 1 is a bidirectional shift register, 2 and 33 ₁ ,
33 ₂ is a modulo 2 adder, and 23 is an opening/closing means.

Claims (1)

[Claims] 1. A bidirectional shift register 1 including multiple stages of registers 1 ₁ , 1 ₂ , . . . , and an output of a stage selected from each stage of this shift register in accordance with a parity generation determinant. In a sequential decoder including an internal encoder equipped with a modulo-2 adder 2 that adds modulo-2 with modulo-2, the bidirectional shift register is constructed by cascading registers with a number of stages corresponding to the maximum constraint length in the systematic code to be decoded. In order to select the output from the register of the stage determined by the parity generation determinant in this bidirectional shift register and supply it to the modulo-2 adder, an output opening/closing means of the register of each stage of this shift register is provided. 23. A sequential decoder characterized in that the sequential decoder is supplied to the modulo-2 adder via 23. 2 Bidirectional shift register 1 including multiple stages of registers 1 ₁ , 1 ₂ , . . . and outputs of stages selected from each stage of this shift register corresponding to the parity generation determinant are added using modulo 2. In a sequential decoder including an internal encoder equipped with a modulo-2 adder 2, the stages determined by the parity generation determinant in a bidirectional shift register consisting of registers with the number of stages corresponding to the maximum constraint length in the systematic code to be decoded. Modulo-2 adders 33 ₁ and 33 ₂ that add the outputs from the registers in modulo-2 are provided corresponding to the respective constraint lengths and generation determinants of the systematic code to be decoded, and the outputs of these modulo-2 adders are A sequential decoder comprising an internal encoder configured to selectively output.