JPH0435777B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an arithmetic processing method, and particularly to a decimal addition/subtraction processing method.

Decimal data is usually expressed as an absolute value, that is, a combination of an absolute value and a sign, and the absolute value is expressed as a binary code 10
It is assumed that the base number and code are made up of 4-bit codes.

Further, when two operand data are added with the same sign or subtracted with different signs, it is called real addition, and when two operand data are subtracted with the same sign or added with different signs, it is called real subtraction.

Conventional decimal addition/subtraction processing consists of the following steps. In the first step, add and add the signs of both operands.
Depending on the type of subtraction, it is determined whether it is a real addition or a real subtraction. In the second step, the first
The absolute value of the operand (hereinafter abbreviated as X) and the absolute value of the second operand which is the addition (subtraction) number (hereinafter referred to as Y)
(abbreviated as ), the operation of X+Y is executed for substantial addition, and the operation of X-Y is executed for substantial subtraction. In the third step, the sign of the result is determined from the signs of both operands and addition/subtraction examined in the first step, and the operation result obtained in the second step, and a sign code is generated. Furthermore, when it is a real subtraction and X<Y, the result of the second step operation
(This processing is called re-correction processing), and the steps for performing this processing are extra long.

In this way, conventional decimal addition/subtraction processing has been difficult to speed up because the processing is performed sequentially from the first step to the third step, or if re-correction is required, to the fourth step. .

An object of the present invention is to shorten the processing that required three steps from the first step to the third step in the conventional method, and to perform high-speed processing of decimal addition/subtraction instructions without the need for re-correction processing. possible and
The purpose of this invention is to provide an arithmetic processing method with a simple structure.

In order to achieve the above object, the arithmetic processing method of the present invention distinguishes between real addition and subtraction based on the signs of both operands and the distinction between addition and subtraction in the first step in decimal addition and subtraction processing, and at the same time identifies the magnitude of the absolute value. Execute the X-Y operation to compare the
Furthermore, in the same first step, the sign code of the result is determined by checking whether the result of X-Y is all zeros and whether one of X or Y is all zeros, and in the second step, According to the results of the investigation, when there is real addition, X+Y, when there is real subtraction and X≧Y, there is X-Y, and when there is real subtraction and X≧Y, there is X-Y.
When Y, -X+Y is executed, and the sign code determined in the first step is further generated and added to the absolute value of the result.

Embodiments of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, the arithmetic processing device of the present invention comprises an
and a Y-register 2, an adder 3 for performing binary addition, a Z-register 4 for storing the result, and ancillary circuits 11 and 1 for performing decimal operations using the binary adder.
2, 13, 14, 15, 16, and additional circuits 5, 6, 7, 8, 9, for performing decimal addition control.
It consists of 10, 17, and 18.

The adder/subtractor that performs decimal operations includes circuits 11, 12,
It consists of 13, 14, 15, 16 and 3. The decimal addition and subtraction operations will be explained below. The summand or subtractive X is transferred to the X-register 1 via line 101.
Then, the addend or subtrahend Y is set via line 102 into the Y-register 2, respectively, with the sign code at the right end. Also, line 100 is set to "0" for addition and "1" for subtraction.

In decimal addition and subtraction, the first step is to determine the type of operation to be performed on the sign and absolute value of the result, i.e., X+Y or
-Y or -X+Y is determined, and in the second step, the calculation is executed to generate a sign code. This operation will be specifically explained below.

In the first step, the following processing is performed. The 4-bit code for the summand (subtraction) and addition (subtraction) is as follows:
Decoders 7 and 8 via lines 1B and 2B respectively
sent to. Decoders 7 and 8 each have line 7
A and 8A are set to "0" when the sign code is positive and "1" when it is negative. In circuit 18, lines 100 and 7
The exclusive OR of A and 8A is taken and outputted to line 18A. Therefore, when the sum of two operands with the same sign or the difference between two operands with opposite signs is required (in real addition), line 18A becomes 0, and the difference between two operands with the same sign or the difference between two operands with opposite signs is required. When you need the sum of two operands (actual subtraction)
The line 18A becomes 1. In this manner, circuit 18 detects whether a substantial addition or subtraction is required. The absolute values of the addend (subtraction) and addition (subtraction) are transmitted to circuits 5, 11, and 14 via lines 1A and 2A, respectively.
and is sent to circuits 12, 13, and 15. The absolute value is 2
It is an evolved decimal number, that is, 4 bits represent one decimal digit (hereinafter simply referred to as a digit). In the zero detection circuit 5, the line 5A is set to "0" if all the lines 1A are "0", that is, X=0, and is set to "1" otherwise. Complement circuits 11 and 12 are connected to lines 1A and 2A, respectively.
NOT (inversion) is performed, that is, the respective 1's complement numbers are output on lines 11A and 12A. Addition circuit 13
adds 6 to each digit of the absolute value of addition (subtraction) number Y so that decimal addition can be performed using binary adder 3,
Output to line 13A. Note that since it is a binary coded decimal number, adding 6 will not cause a carry to the upper digit. 14 is a selector that selects either line 1A or 11A and outputs it to line 14A, and is controlled by line 9B. When the line 9B is "0", the line 1A is selected, and when the line 9B is "1", the line 11A is selected. 15 is line 2A,1
A selector selects one from 2A and 13A and outputs it to line 15A, and is controlled by lines 9A and 9B.
When line 9A is “0”, line 13A is applied regardless of the value of line 9B, when line 9A is “1” and line 9B is “0”, line 12A is applied, and when line 9A is “1” and line 9B is When it is "1", line 2A is selected. In the first step, lines 9A and 9B are forced to "1" and "0", respectively, and lines 1A and 12A are output to lines 14A and 15A, respectively. That is, X is input to the line 14A, and the one's complement of Y (written as) is input to the line 15A.
The result is binary addition and output on line 3B. At this time,
The value on line 9A is used as is as the initial carry input to the bottom of adder 3, and the final carry obtained from the top is output on line 3A. That is, the line 3A is the final carry of X-Y performed by the adder 3, and indicates that when "0", X<Y, and when "1", X≧Y. Now, since line 9A is "1", when this and the value on line 15A are added in adder 3, the two's complement of Y is obtained, and in the end, adder 3 executes the operation of X-Y. become. However, since decimal addition is performed using the binary adder 3, correction is necessary, and the correction circuit 16 uses the line 3B
For each digit in the adder 3, digits for which a carry has occurred to the upper digit are left unchanged, and 6 is subtracted for digits for which no carry has occurred, and a line is drawn. 1
Output to 6A. Note that since this correction method is a known technique, further explanation will be omitted. The X-Y result appears on the line 16A and is sent to the zero detection circuit 6. Zero detection circuit 6 is line 6A
is set to "0" if all lines 16A are "0", and set to "1" otherwise. The lines 3A and 18A are input to the arithmetic control circuit 9, and the lines 3A, 18A, 7A, 5A, and 6A are input to the sign determination circuit 10.
(Fig.) is latched. The above is the first step processing.

The processing of the second step is shown below. Details of the arithmetic control circuit 9 are shown in FIG.
The contents of line 8A are output as line 9A, and the latched contents of line 3A are inverted and the contents of line 18 are ANDed and output as line 9B. That is, when the line 9A is "1", it indicates that it is a real subtraction to find the difference in absolute values, and when the line 9B is "1", it is a real subtraction and X<Y. Therefore, - X
This indicates that +Y operation is required. The sign determination circuit 10 also uses the results of the investigation in the first step, that is, a line 7A indicating the sign of X, a line 3A indicating the magnitude of X and Y, and a line 18 indicating the sum or difference of absolute values.
Determine the sign to be added as a result from the line 5A indicating whether or not A, Outputs “0” or “1”. The basics of determining the sign are that when the sum of absolute values or X>Y and the difference in absolute values, the sign of X is the same, and when X<Y and the difference in absolute values, the sign of When the value is zero, the sign should be positive. Whether or not the absolute value of the result is zero is determined by whether or not line 6A is 0 when calculating the difference in absolute values (when line 18A is 1), and by whether line 6A is 0 when calculating the sum of absolute values (when line 18A is 1).
When A is 0), line 6A is 0 and line 5A is 0.
Judgment will be made based on whether or not. For this purpose, the sign determining circuit 10 is constructed as shown in FIG.

FIG. 3 will be briefly explained. The line 18A indicating whether or not it is a real subtraction and the carries from the adder 3, that is, X and Y
AND with the inversion of line 3A, which represents the magnitude of the absolute value of
When the line 10AA is "1", it indicates a substantial subtraction and X<Y. In other words, line 1
When 0AA is "1", it means that the operation -X+Y is performed. Furthermore, between this and line 7A
The line 10AC, which is AND, has the same value as the line 7A representing the sign of X when the line 10AA is "0", that is, the calculation of X±Y, and is the inverse of the line 7A when the line 10AA is "1". The above is the main code determination logic, and the remaining part is the logic for forcibly setting the code to 0 when the result is all 0. line 10AB
When is “0”, it indicates that X+Y and X=0, and when line 10AD is 0, the result is all 0.
It shows that. Line 10AC and line 10
By ANDing AD, the normal line 10AC is output from the line 10A, and when the result is all 0, it is forced to 0. Lines 9A and 9B are selectors 14,
Sent to 15th. The selector 14 outputs a line 1A corresponding to X when the line 9B is "0", and outputs a line 11A corresponding to X when the line 9B is "1". Selector 15
is line 13A which corresponds to +Y when line 9A is “0”
, when the lines 9A and 9B are "1" and "0", the corresponding line 12A is when the lines 9A and 9B are "1" and "1"
When , line 2A corresponding to Y is output. Adder 3
Then, binary addition is made to the outputs of selectors 14 and 15 using line 9A as an initial carry, and the output line 3B is
is corrected by the correction circuit 16 and set in the Z register 4. In the end, the signals 9A and 9B are 0, 0
When , X+Y is 1, and signals 9A and 9B are 1,
When it is 0, X-Y and signals 9A and 9B are
When it is 1,1, Y-X is obtained. At this time, two's complement circuits 11 and 12 are provided, and selectors 14 and 15 select the input of this adder from among these outputs and the original operand, thereby performing various operations in step 2 and step 1. The above-mentioned subtraction can be performed. On the other hand, a line 10A indicating the sign of the result is sent to an encoder 17. The encoder 17 generates a 4-bit sign code, which is positive if the line 10A is "0" and negative if it is "1", and outputs it to the line 17A. line 17A
is set in Z-register 4. The absolute value and sign of the result thus obtained in the Z-register are stored in a memory or the like via line 104. The above is the second step processing.

In this embodiment, by providing zero detection circuits 5 and 6 and reflecting the result in the sign determination circuit 10, it is possible to perform decimal addition and subtraction processing in two steps even when minus zero is not allowed in the result of decimal addition and subtraction. .

According to the present invention, in decimal addition/subtraction processing, there are two steps: a step of determining the sign of the result and the division of operations to be performed on the absolute value, and a step of performing the actual operation and generating the sign code of the result. Since the process can be completed in just 3 steps, the process that conventionally required three steps can be shortened, and at the same time, the re-correction process that was conventionally required in actual subtraction can be eliminated. Furthermore, since it can be realized using one adder, the circuit becomes extremely simple.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a circuit implementing the arithmetic processing method of the present invention, FIG. 2 is an example of the arithmetic control circuit of FIG. 1, and FIG. 3 is a diagram showing an example of the code determination circuit of FIG. 1.

Claims (1)

[Claims] 1. First and second operands that are composed of an absolute value and a sign and that generate the complements of the respective absolute values of the first and second operands to which addition or subtraction operations are to be performed. a complement circuit; an adder circuit; first selection means for selecting which of the absolute value of the first operand and the output of the first complement circuit should be input to the adder circuit; and the second operand. a second selection means for selecting which of the absolute value of and the output of the second complement circuit should be input to the addition circuit; and whether or not the operation is an addition to the absolute value of the first and second operands. means for identifying the first and second operands based on the signs of the first and second operands, and means for controlling the first and second selection means, the control means first selecting the The absolute value of one of the first and second operands is compared with the absolute value of the other such that the comparison between the absolute values of the first and second operands is performed in parallel with the identification by the identification means. The complement generated by either the first or second complement circuit is selected by the first or second selection means, whereby the comparison is performed in parallel with the identification by the identification means. Then, depending on the combination of the carry output of the adding circuit and the output of the discriminating means when the adding circuit performs the comparison, (a) the absolute value of the first and second operands is determined. (b) select the absolute value of the first operand and the second operand for subtraction of the absolute value of the second operand from the absolute value of the first operand; or (c) select the output of the complement circuit of the first operand from the absolute value of the second operand.
controlling the first and second selection means to select the output of the first complement circuit and the absolute value of the second operand for subtraction of the absolute value of the operand; When the adding circuit compares the absolute values of the first and second operands, the sign of the resultant data of the operation is determined by the combination of the carry output of the adding circuit and the output of the identifying means. An arithmetic processing method with additional means.