JPH043597B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sense amplifier used in integrated memories and the like.

[Prior Art] In a one-transistor random access memory (hereinafter referred to as RAM), the charge stored in the storage capacity of a memory cell is transferred to a digit line via a switching transistor, which is a selection gate. A method is used in which a signal is amplified by a highly sensitive sense amplifier and sent out as an output signal, and at the same time, the amplified signal is rewritten into the memory cell concerned.

Conventional examples of sense amplifiers include, for example, the International Solid State Circuits Conference held in February 1934 (1984 IEEE
INTERNATIONAL SOLID−STATE
Digest of CIRCUITS CONFERENCE)
of technical papers (ISSCC)
DIGEST OF TECHNICAL PAPERS) No. 278
~Page 279 (distributed at the same time as the February 1984 conference) “Sub-100 nsec 256K using CMOS technology
DRAM (“A Sub 100 ns 256K DRAM in
It was introduced in a paper by Roger I. Kung and others titled ``CMOS Technology''.

Figure 3 shows the configuration of the C-MOS sense amplifier introduced in the above paper. That is, sense amplifier A
(indicated by a broken line in the figure) are n-MOS transistors Q ₁ and Q ₂ and p-MOS transistors Q ₃ and
It consists of a flip-flop circuit consisting of _Q4 , and the output points N1 and _N1 of the flip-flop circuit
_N2 is connected to the digit lines _D1 and _D2 of the memory circuit, respectively, and the load capacitances of both are made equal. When one memory cell 5 of the memory cells connected to digit line D ₁ is read out, the memory cell 6 connected to the other digit line D ₂ is not read out, but instead,
Memory cell information “1” and “0” from dummy cell 8
A reference potential intermediate between and is applied to the digit line _D2 . Conversely, when the memory cell 6 is read out,
A reference potential is supplied from the dummy cell 7 to the digit line _D1 . Transistor _Q7 is for precharging both digit lines to the same potential before the information in the memory cell is read out onto the digit line.

FIG. 4 shows operating waveforms of the conventional circuit shown in FIG. 3.

The operation of the conventional circuit shown in FIG. 3 will be explained below using the waveforms shown in the same figure.

Digit lines D ₁ and D ₂ are precharged to equipotential through transistor Q ₇ by time t ₁ . At time _t1 , the voltage on clock signal line _φ3 drops from high level to low level, and then at time _t2 , if word line 9 is selected by the address signal, the voltage on word line 9 goes to high level. Then,
Information in memory cell 5 is read out onto digit line _D1 . On the other hand, the digit line _D2 is given a potential intermediate between the cell information "1" and "0" by the dummy cell 3. As a result, a potential difference of about 0.1V is generated between the digit lines _D1 and _D2 before time _t3 . At time _t3 , when the voltage on the clock signal line _φ1 is set to a high level and the n-MOS transistor _Q5 is made conductive to activate the sense amplifier A, the positive feedback effect of the transistors _Q1 and _Q2 causes the digit line _D1 to become high. as well as
Of D ₂ , the one with the lower potential falls below the threshold voltage of the transistor V _th sooner, suppressing the potential drop of the digit line on the high level side. Next, at time _t4 , the voltage of the clock signal line _φ2 is dropped from a high level to a low level, and the p-MOS transistor _Q3 is turned on. At time _t5 , the high level side digit line reaches the power supply voltage _Vcc. The potential difference between both digit lines becomes maximum. During this time, the signal on the digit line is transmitted to the outside, and is rewritten into the memory cell, completing reading from the memory cell.

[Problem that the invention seeks to solve]

By the way, in the conventional sense amplifier as shown in FIG. 3, when the high-level side digit line _D2 , for example, is raised to the power supply voltage _Vcc at time _t5 , the gate and drain of the cross-coupled transistor _Q2 , 0V, _Vcc , and 0V are applied to the source electrodes, respectively. Therefore, as integrated memories become more highly integrated and the transistors in sense amplifiers are made to have shorter channels, it becomes necessary to maintain the power supply voltage _Vcc at 5V, which is TTL compatible.
The withstand voltage between the drains decreases and the withstand voltage becomes lower than the power supply voltage V _cc
If it is below, hot carriers will be injected into the gate oxide film, changing the threshold voltage or current characteristics of transistor _Q2 , causing deterioration of transistor characteristics. In particular, the cross-coupled transistors Q ₁ and Q ₂ handle minute signal differences during the amplification operation following signal readout from the memory cell, so if the transistor characteristics of Q ₁ and Q ₂ deteriorate, the other transistors will deteriorate. There is a greater risk of malfunction than when To prevent this phenomenon, cross-coupled transistors
It is necessary to take measures to avoid applying high voltage between the source and drain of Q ₁ and Q ₂ .

SUMMARY OF THE INVENTION An object of the present invention is to provide a sense amplifier in which characteristic deterioration due to a decrease in source-drain breakdown voltage does not occur even when the MIS transistors constituting the sense amplifier are short-channeled.

[Means for solving problems]

The sense amplifier of the present invention includes a first MIS transistor having a gate coupled to a second terminal, a source coupled to a third terminal, a drain coupled to a fourth terminal, and a gate coupled to the first terminal and a source coupled to the third terminal. a second MIS coupling the drain to the fifth terminal, respectively;
a first clamping MIS transistor having a gate coupled to the clamp signal line, a source coupled to the fourth terminal, and a drain coupled to the first terminal; and a gate coupled to the clamp signal line;
The source is connected to the fifth terminal, and the drain is connected to the second terminal.
MIS for the second clamp that connects to the terminals of
The clamping MIS transistor includes at least a transistor and a means for charging or discharging the third terminal, and when the clamp signal line consisting of binary levels is at the first voltage level, the clamping MIS transistor
Sensing characterized in that the clamping MIS transistor operates in the polar region and in the case of a second voltage level, the clamping MIS transistor having its drain coupled to the first or second terminal operates in the pentode region. It's an amplifier.

[Effect]

A sense amplifier according to the invention is used in an integrated memory with a first terminal coupled to one digit line and a second terminal coupled to another digit line. Here, when reading memory cell information and during initial amplification of the sense amplifier, the voltage of the clamp signal line is set to a high level in the case of an n-channel transistor, and the clamp MIS transistor is operated in the triode region, and the voltage of the sense amplifier is set to a high level. After initial amplification, the voltage on the high-level side of the digit line is increased from the precharge level to the power supply voltage, so-called when pulling up the digit line, the level is set to low, and the drain is connected to the digit line on the high-level voltage side for clamping.
The MIS transistor is operated in the pentode region. In this way, when reading the memory cell and during initial amplification of the sense amplifier, the first and second signals are used for signal amplification.
The same potential as each digit line is applied to the drain of the MIS transistor, but when pulling up the digit line, the MIS transistor for signal amplification connects the drain to the high-level digit line via the clamping MIS transistor. A potential obtained by subtracting the threshold voltage from the low level voltage of the clamp signal is applied to the drain of the transistor, and the drain is connected to the low level side digit line via another MIS transistor for clamping. The same potential as the low level digit line is applied to the drain of the digit line. Therefore, when the digit line is pulled up, the potential of the digit line becomes a high level such as the power supply voltage _Vcc , and
Even if the source potential of the MIS transistor for amplification becomes 0V, a potential that is a certain voltage lower than the potential of the digit line is applied to the drain of the MIS transistor for amplification. Therefore, the source-drain breakdown voltage of the MIS transistor for amplification is lower than the power supply voltage V _cc
By effectively reducing the digit line voltage using the clamping MIS transistor, the source-drain voltage applied to the amplifying MIS transistor can be maintained at a low voltage even if the digit line voltage is lower than that due to hot carriers, etc. Configures a sense amplifier because it prevents deterioration of transistor characteristics.
The advantages include the ability to shorten the channel length of MIS transistors, miniaturize them, and realize integrated memories that are less likely to malfunction.

〔Example〕

EXAMPLES Hereinafter, in order to better understand the present invention, the present invention will be explained using examples.

FIG. 1 shows one embodiment in which the sense amplifier of the present invention (circuit block A surrounded by a broken line in the figure) is applied to an integrated memory. MIS transistor for amplification
Q ₁ has the gate to terminal N ₂ and the source to terminal N ₃ ,
The drains are respectively coupled to terminal N ₄ for amplification.
MIS transistor _Q2 has its gate coupled to terminal _N1 , its source coupled to terminal _N3 , and its drain coupled to terminal _N5 . MIS transistor QC ₁ for clamping
clamps the gate to the signal line φ _c , and connects the source to the terminal
The clamping MIS transistor QC ₂ has its gate coupled to the clamp signal line _φc , _its source coupled to the terminal _{N5 ,} and its drain coupled to the terminal _N2 . MIS transistor _Q3 has its drain connected to terminal _N3 , its gate connected to clock signal line _φ1 , and its source connected to zero potential power supply GND.
are connected to each other. Circuit blocks P ₁ and P ₂ respectively coupled to terminals N ₁ and _{N 2}
This is a pull-up circuit that raises the potential of N2 and _N2 from a low level to a high level.
The p-MOS transistor Q ₃ shown in the conventional example in the figure,
Can be replaced by Q ₄ . Transistors Q ₁ , Q ₂ , Q ₃ , QC ₁ , QC ₂ and pull-up circuits P ₁ and P ₂ surrounded by broken lines constitute the sense amplifier A of the present invention. In the circuit diagram of FIG. 1, the circuit elements other than the above-mentioned sense amplifier A are:
This is the same as the conventional example shown in FIG. 3, and the same components are given the same numbers and their explanation will be omitted.

The circuit operation of this embodiment will be explained using the operating waveforms shown in FIG. However, the discussion will proceed assuming that the high level voltage of the clamp signal line φ _c is the power supply voltage V _cc and the low level voltage is V _cc /2.

Digit wires D ₁ , D ₂ and terminals N ₁ , N ₂ , N ₄ ,
N ₅ is precharged to an equipotential of V _cc /2 by time t ₁ . For this purpose, the MIS transistor _Q7 shown in the conventional example of FIG. 3 may be used. Here, the high level voltage V _cc of the clamp signal is applied to the gates of the clamping transistors QC ₁ and QC ₂ , and the voltage V _cc /2 is applied to the sources and drains, so it is assumed that both transistors are in a conductive state. .
When the voltage on word line 9 or 10 goes high at time _t2 , the information in memory cell 5 or 6 is read onto digit line _D1 or _D2 . The other digit line is given a potential intermediate between cell information "1" and "0" by dummy cell 8 or 7. As a result, a small potential difference occurs between the digit lines _D1 and _D2 before time _t3 . At time _t3 , the voltage of clock signal line _φ1 is set to high level, and MIS transistor _Q3
When the sense amplifier A is activated by conducting, the potential difference between the digit lines D ₁ and D ₂ is transmitted through the terminals N ₁ and N ₂ and between the gates of the transistors Q ₂ and _{Q 1 .} Due to the positive feedback effect of QC ₁ , Q ₂ , and QC ₂ , the one with lower potential among terminals N ₁ and N ₂ quickly falls below the threshold voltage V _th of amplification transistors Q ₁ and Q ₂ , and the higher potential side Reduce potential drop at terminals. Next, at time _t4 , the voltage of the clamp signal line _φc is lowered from the high level _Vcc to the low level _Vcc /2,
When the pull-up circuits P ₁ and P ₂ are activated at time t ₅ , the potential of the higher potential terminal of the N ₁ and N ₂ terminals is raised to the power supply voltage V _cc at time t ₆ .
The voltage difference between N ₁ and N ₂ terminals becomes maximum. For example, if the potential of terminal N ₂ is on the high level side and the potential on terminal N ₁ is on the low level side, the potential of terminal N ₂ is the power supply voltage V _cc and the potential of terminal N ₁ is the ground voltage GND.
becomes. Regarding the potential of terminals N ₄ and N ₅ at this time, since the gate voltage of clamping transistors QC ₁ and QC ₂ is V _cc /2, the potential of terminal N ₄ on the low potential side is ground voltage GND. On the other hand, the potential of the terminal _N5 on the high potential side becomes _Vcc /2- _Vth , where _Vth is the threshold voltage of the transistor _QC2 . At this time, the terminal
Since the potential of N ₃ is the ground voltage GND, the source-drain voltage of the amplification transistor Q ₂ is V _cc /
2−V _th , the voltage between the source and drain of the clamping transistor QC ₂ is V _cc /2+V _th , and the third
The maximum source-drain voltage V _cc of the cross-coupled transistor shown in the figure is
The source-drain voltage of Q ₂ becomes low. or,
As shown in the voltage waveforms at terminals N ₄ and N ₅ in Figure 2, the potential at terminals N ₄ and N ₅ is always below V _cc /2, so the voltage between the sources and drains of amplifying transistors Q ₁ and Q ₂ is In this embodiment, the voltage is at a maximum of V _cc /2. Therefore, even when the sense amplifier of this embodiment is configured with miniaturized short channel MIS transistors, the source-drain voltage applied to the amplifying MIS transistors Q ₁ and Q ₂ can be maintained at a low voltage.
This has the advantage of preventing deterioration of transistor characteristics due to hot carriers and the like.

In the sense amplifier of this embodiment, the clamp signal line φ _c
The high and low level voltages of _Vcc and _Vcc /2 have been explained, but depending on the precharge voltage of the digit line,
The high level voltage can be set to any voltage above V _cc and the low level voltage to any voltage below V _cc , but at least the clamping MIS transistors QC ₁ and QC ₂ are triode transistors during memory cell readout and sense amplifier initial amplification. When the high level side voltage of the digit line is pulled up after the initial amplification of the sense amplifier, the clamping MIS transistor coupled to the high level side digit line operates in the pentode area. effect is demonstrated.

In all of the above explanations, it has been assumed that the sense amplifier of the present invention is made of n-channel type MIS transistors, but the sense amplifier is essentially the same even if it is made of p-channel type MIS transistors.

〔Effect of the invention〕

As explained above, according to the present invention, a sense amplifier is obtained that can maintain the source-drain voltage applied to the amplifying MIS transistor at a lower voltage than the conventional example, and the MIS transistors are miniaturized. Even if the channel is shortened, the transistor characteristics are not easily deteriorated, so that a sense amplifier with a wide operating margin can be realized. Furthermore, compared to the case where the clamp signal line is held at a constant voltage, the reading and sensing speed of the memory signal when the clamp signal line is at a high level becomes faster, and when the clamp signal line is at a low level, the drain of the cross-coupled transistor This has the advantage of lowering the voltage applied to it.

[Brief explanation of drawings]

1 and 2 are a circuit diagram of a sense amplifier showing an embodiment of the present invention and a waveform diagram for explaining its operation, respectively. FIGS. 3 and 4 are a circuit diagram of a conventional sense amplifier and a waveform diagram for explaining its operation, respectively. The symbols in the diagram are Q ₁ , Q ₂ , Q ₃ , Q ₄ , Q ₅ , Q ₆ ,
Q ₇ , QC ₁ , QC ₂ are MIS transistors, φ ₁ , φ ₂ ,
φ ₃ is the clock signal line or its potential, P ₁ ,
P ₂ is the pull-up circuit, N ₁ , N ₂ , N ₃ , N ₄ ,
N ₅ is the circuit terminal or its potential, D ₁ and D ₂ are the digit lines or their potential, φ _c is the clamp signal line, V _cc is the high potential power supply, GND is the zero potential power supply, t ₁ ~ t ₆ is the time, 5 and 6 are the memory cells,
7 and 8 are dummy cells, 9 and 10 are word lines,
Each is shown below.

Claims (1)

[Claims] 1. A first circuit that connects the gate to the second terminal, the source to the third terminal, and the drain to the fourth terminal, respectively.
a second MIS transistor having a gate coupled to the first terminal, a source coupled to the third terminal, and a drain coupled to the fifth terminal; the gate coupled to the clamp signal line; and the source coupled to the fourth terminal. a first clamping MIS transistor having a drain coupled to the first terminal, a gate coupled to the clamp signal line, a source coupled to the fifth terminal, and a drain coupled to the second terminal. It includes at least a second clamping MIS transistor and a means for charging or discharging the third terminal, and when the clamp signal line consisting of binary levels is at the first voltage level, the clamping MIS transistor When the MIS transistor operates in the triode region and at a second voltage level, the clamping MIS transistor having its drain coupled to the first or second terminal operates in the pentode region. Features a sense amplifier.