JPH0436015B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention is a multi-channel X-ray detector that performs image reconstruction based on projection data collected by installing an X-ray tube and a multi-channel X-ray detector across a subject. The present invention relates to an X-ray tomography apparatus (hereinafter referred to as a CT apparatus) that includes a high-speed calculation processor (hereinafter referred to as FPU) and a back projector dedicated to back projection (hereinafter referred to as BPU).

(Prior Art) Conventionally, X-rays are scan-irradiated onto a subject from multiple angular directions to collect a large amount of projection data, and a tomographic image of a desired region is created by image reconstruction calculation processing based on the projection data. CT that displays images on CRT etc.
The device is well known.

Data processing in such a CT apparatus basically consists of preprocessing, reconstruction calculation processing, and postprocessing steps. In preprocessing, the output of the X-ray detector is subjected to amplification, integration, analog-to-digital conversion, logarithmic conversion, etc., and correction regarding projection data (correction of X-ray intensity, radiation quality effect, scattered radiation, etc.). In the reconstruction calculation processing step, an image reconstruction calculation using a Fourier method, a convolution method, etc. based on the preprocessed projection data, and a back projection calculation for allocating the projection data to a two-dimensional pixel plane are performed. That is, data for displaying a tomographic image on a CRT is created by the reconstruction calculation process. Pixel values (pixel data) supplied for image display are modified through post-processing into a form suitable for storage on a recording medium.

With the above CT equipment, image reproduction is always precise and
Moreover, it is required to be performed at high speed.

Various products have been developed to meet these demands. For example, there is a structure shown in Japanese Patent Application No. 61-189426 and shown in FIG. The former uses one FPU that performs high-speed reconstruction calculations and one FPU that performs only back projection.
The latter is configured with an additional BPU, and the latter has one FPU1
It is configured by connecting multiple BPUs _{2 1} , 2 ₂ , ..., 2 _o . In addition, in an attempt to perform data processing at even higher speeds, a so-called parallel processing method, which is a system including a plurality of means each consisting of an FPU and a BPU, as shown in FIG. 4, has been realized. In either case, the FPU is equipped with a main memory that stores preprocessed projection data and a calculation unit that performs image reconstruction, and the BPU is equipped with a calculation unit that independently performs back projection and corresponds one-to-one with each pixel of the image. It is equipped with an image memory consisting of addresses, a back projection adder, etc.

On the other hand, recently, an improved version of the CT apparatus seen in the above-mentioned Japanese Patent Application No. 189426/1983, that is, a CT apparatus equipped with a back projection calculation means as shown in FIG. 5, has been developed. The back projection calculation means includes one BPU 11 and two FPUs 12 and 13 connected thereto. The BPU 11 includes two backprojection execution units that receive data necessary for backprojection independently in parallel from each FPU, an image memory that can be accessed from either FPU, an adder, a control unit, etc. , the backprojection of the same pixel of interest in each preprocessed view is performed simultaneously, and the backprojection data is stored in the image memory.

In such a CT device, a predetermined back projection calculation process is executed under the control of the control unit, so that
The intended purpose is achieved. Furthermore, the CT in Figure 5
As for the apparatus, there is an advantage that the configuration of the back projection calculation means of the parallel calculation processing type is simplified.

By the way, the control unit that controls the back projection operation of the CT apparatus shown in FIG.
It is connected to the FPU 12 and receives control-related data (data representing selection of the shape of the image reconstruction area, setting of the number of operating FPUs, etc.) from the FPU 12 to the control register of the BPU 11. That is, the control section
It operates with FPU12 as the master and FPU13 as the slave.

(Problem to be solved by the invention) Therefore, if the master FPU 12 fails,
There is a problem that normal back projection calculation cannot be performed.

The present invention has been made in view of the above, and its purpose is to provide a CT device that can perform back projection calculations even if the master FPU among multiple FPUs that perform parallel processing fails. is to provide.

(Means for Solving the Problems) The C device of the present invention that achieves the above object has a BPU
However, there is a control unit that controls the operation of each part based on the data related to backprojection control supplied from the FPU that is selected and specified in advance, and the same number of FPUs are prepared, and the backprojection of the same pixel of interest in each view is executed simultaneously. The first step is to add the outputs of the back projection execution unit and only the back projection execution unit connected to the normal FPU.
an adder, an image memory that is accessed from each FPU, and a first adder that adds the data read from the image memory and the output of the first adder and stores it at the address of the read data. It consists of two adders.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a BPU of a CT apparatus according to an embodiment of the present invention. BPU11 is the 5th
As in the case shown in the figure, it is connected to the FPUs 12 and 13 (omitted in Fig. 1). The back projection execution units 14 and 15 are provided in correspondence with the number of FPUs connected to the BPU 11, and in this embodiment, there are two units. The back projection execution unit 14 includes an address generation unit 17 connected to the FPU 12 via a general-purpose bus 16.
and a data memory 18. The back projection execution unit 15 also includes an address generation unit 20 and a data memory 21 connected to the FPU 13 via a general-purpose bus 19.
has. Control registers 22 and 23 also have individual
It is installed corresponding to the FPU and accepts control data transfer from each FPU. The control section 24 controls the operation of each section based on the contents of the control register connected to the FPU selected and designated by the switch 25. Buffer amplifiers 27 and 28 that output "1" or "0" under the control of the control section 24 are connected to the input port of the adder 26, and the back projection execution section 14
The configuration is such that the data corresponding to the same pixel outputted from and 15 are added. The image memory 29 has addresses in one-to-one correspondence with each pixel of the image, and has ports connected to the general-purpose buses 16 and 17, respectively. Adder 30 is image memory 2
The data read from adder 9 and the data from adder 26 are added, and the result is stored at the address of the read data.

In the above configuration, first, FPU12 and 13
A case where both are normal and back projection calculation is performed using the FPU 12 as the master (when the switch 25 is on the FPU 12 side) will be explained. At this time, control data from FPUs 12 and 13 are transferred to control registers 22 and 23, respectively, but FPU 1
2 as the master, the control unit 24 controls the backprojection calculation based on the contents of the control register 22. Further, each output of the buffer amplifiers 27 and 28 is "1", and the adder 26 is in a state where normal addition is possible, that is, the outputs of the back projection execution units 14 and 15 are added together and output. In this state, the FPU
12 preprocesses the i-view projection data shown in FIG. At the same timing as the FPU 12, the FPU 13 preprocesses the projection data of the j view shown in FIG. The backprojection execution units 14 and 15 perform backprojection focusing on the same pixel 31 (see FIG. 2). That is, the address generators 17 and 20
generates addresses of data memories 18 and 21, respectively, in which data corresponding to the pixel of interest 31 in i-view and j-view are stored.
Then, projection data corresponding to the pixel of interest 31 in the i-view and j-view is read out from the data memories 18 and 21. The two read data are added by the adder 26 and then stored in the image memory 2.
9 is added to the previous backprojection data read from the address corresponding to the pixel 31 of current interest, and is written again to the same address. As a result, the back projection of the pixel of interest 31 in the i-view and the j-view is performed simultaneously. The above operation is performed over all pixels of all views and the backprojection is completed. After the series of backprojection operations is completed, the FPUs 12 and 13 access the image memory 29 and perform parallel processing as necessary.

On the other hand, both FPU12 and 13 are normal, and FPU
13 as the master, the switch 25 is switched to the FPU 13 side, and the control unit 24
controls the backprojection calculation based on the contents of the control register 23. The only difference from the above example is this point, and the basic operations of other parts are performed in the same manner as in the above case, and the predetermined back projection calculation is completed.

Next, a case will be described in which either one of the FPUs 12 or 13, for example, the FPU 13 is in failure and the FPU 12 is normal. At this time, since FPU12 has no choice but to become the master, switch 25 is set.
Set it to the FPU12 side. The control section 24 controls the operation of each section based on the contents of the control register 22. Under this control, only the back projection execution section 14 is driven, and the buffer amplifiers 27 and 28 receive "1" and "0".
are input respectively. Therefore, the output of the adder 26 becomes the output of the backprojection execution unit 14 itself. The operations in the adder 30 and the image memory 29 are as described above.
This is the same as when both FPUs 12 and 13 are normal.

Also, on the contrary, FPU12 is broken and FPU1
If 3 is normal, back projection calculation is performed using the FPU 13 as the master (the switch 25 is switched to the FPU 13 side). That is, control is executed based on the contents of the control register 23, and the back projection execution unit 1
5 is driven, and the buffer amplifier 27 receives “0”.
"1" is applied to each buffer amplifier 28.
Therefore, the output of the adder 26 becomes the output of the backprojection execution unit 15 itself. Further, the operations in the adder 30 and the image memory 29 are the same as in the case of the failure of the FPU 13 described above.

As mentioned above, in the configuration shown in Figure 1, one
Even if the FPU fails, back projection can be continued using the normal FPU as the master by switching the switch 25.

In the above example, the explanation is that switching the switch is done manually, but the FPU
A switch drive may be provided which is driven by a signal indicative of a failure in the switch for automatic switching.
In addition to the mechanical configuration as in the embodiment, the switch may also be configured as a software switch mapped to the address of a computer that constitutes the main part of the CT apparatus. In this case, the computer can be provided with a function of detecting an abnormality in the FPU using a self-diagnosis program or the like at the time of system startup, and selecting and designating the FPU to be the master. Further, although the above embodiment shows an example of two FPUs, the CT apparatus may include more FPUs. In this case, as shown in FIG. 3, the BPU includes back projection execution units 32 ₁ , 32 ₂ , . . . , 32 _o connected to each FPU, and an adder 33 having n input ports. The configuration is such that the output of the adder 33 is given to the adder 30.

(Effects of the Invention) As described above, according to the CT device of the present invention, a master FPU is selected and designated in advance, and the FPU and The same number of backprojection execution units are prepared to simultaneously perform backprojection of the same pixel of interest in each view, and the outputs of only the backprojection execution units connected to a normal FPU are added together and sent to the image memory. Therefore, in parallel processing, even if the master FPU fails, backprojection calculations can be connected. Therefore, FPU
The CT device itself will not go down due to a failure.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing a back projector (BPU) according to an embodiment of the present invention, FIG. FIG. 4 is a block diagram showing a back projector in an embodiment, FIG. 4 is a block diagram showing a conventional reconstruction calculation means, and FIG. 5 is a conceptual diagram of a parallel processing type reconstruction calculation means. 1, 12, 13...High speed processor (FPU), 2 ₁ , 2 ₂ , ~, 2 _o , 11... Back projector (BPU), 14, 15, 32 ₁ , 32 ₂ , ~, 32 _o
... Back projection execution unit, 16, 19 ... General purpose bus, 1
7, 20... Address generation unit, 18, 21... Data memory, 22, 23... Control register, 24
...Control unit, 25...Switch, 26, 30, 3
3... Adder, 27, 28... Buffer amplifier,
29... Image memory.

Claims (1)

[Scope of Claims] 1. In an X-ray tomography apparatus in which a back projector dedicated to back projection is added to a plurality of high-speed calculation processors that perform image reconstruction based on preprocessed projection data, the back projector a control section that controls the operation of each section based on data related to backprojection control supplied from a high-speed arithmetic processor to be selected and specified; A backprojection execution unit that independently receives the data necessary for backprojection and simultaneously performs backprojection on the same pixel of interest in each view, and the output of only the backprojection execution unit that is connected to a normal high-speed arithmetic processor. a first adder that adds 1 to each pixel of the image;
An image memory having a one-to-one address and accessed by any of the high-speed arithmetic processors; and adding the data read from the image memory and the output of the first adder, and adding the result to the readout processor. 1. An X-ray tomography apparatus comprising: a second adder for storing the data at the address of the received data.