JPH0436497B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a system for detecting faults occurring in highways and their transmission/reception circuits.

[Prior art]

With the development of digital technology, efforts are being made to introduce time-division switching equipment that accommodates highways that multiplex digital signals and performs switching using digital signals.

Figure 1 shows an example of a highway format, in which 32 digital signals obtained by quantizing data sampled at a sampling period of 8 kHz to 8 bits are multiplexed to form one frame. The highway shown in this example has 256 bits of data in one frame of 125 μs, and the transmission speed is
It is 2.048Mb/s. Also, the beginning of each frame
1 bit is a frame signal necessary for phase synchronization. Each device constituting the time division switch accommodates a plurality of highways as shown in FIG. 1, and has the function of exchanging digital signals and detecting failures occurring in the accommodated highways and their transmitting/receiving circuits.

FIG. 2 shows an example of failure detection in a conventional time division switch. This example shows an example in which a fault detection circuit is installed in a time division connector device TDC that connects a highway HW and a time switch TSW.

In FIG. 2, REC is a receiving circuit that receives data D, clock C, and frame F from highway HW. DET is a frame synchronization monitoring circuit that monitors whether or not frame F is periodically added to the highway. Frame synchronization monitoring circuit
DET outputs highway failure information ERR when frame F is not detected in a predetermined period.
FF is a storage memory for failure information ERR.

Conventionally, as shown in FIG. 2, a frame synchronization monitoring circuit DET was installed for highways to detect failures. Even in this case, in a time division switch that has a high data multiplicity of highways and accommodates a small number of highways, the amount of hardware for the failure detection circuit is relatively small. However, in a time-sharing exchange that has low data multiplicity on highways and accommodates a large number of highways, installing a frame synchronization monitoring circuit DET for highways as shown in Figure 2 requires a significant increase in hardware, resulting in a compact and economical system. This poses an obstacle to configuring a time-division switch.

[Purpose of the invention]

An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, reduce the ratio of time-division highway failure detection circuits in a time-division exchange that accommodates a large number of time-division highways, and provide the same ability as conventional failure detection. An object of the present invention is to provide a time-division highway fault detection method having the following methods.

[Summary of the invention]

The present invention provides a system for accommodating a plurality of highways by sharing a frame synchronization monitoring circuit and sequentially drawing clock and frame signals received from a plurality of time-division highways into the frame synchronization monitoring circuit. This system is designed to detect faults in the following cases.

[Embodiments of the invention]

FIG. 3 shows an embodiment of the time-division highway fault detection method according to the present invention.

Here, DET is the frame synchronization monitoring circuit,
Commonly installed for multiple highways.
SEL is a selection circuit, and the frame synchronization monitoring circuit DET sequentially selects the clock C frame F of each highway.
to draw into. DEC or distribution circuit, which is a retention memory FF installed to support the highway that monitors the failure information ERR output by the frame synchronization monitoring circuit DET.
Send to. TIM is a timing circuit that creates the timing necessary to control the selection circuit SEL, distribution circuit DEC, and frame synchronization monitoring circuit DEL.
Further, HW is a highway, TDC is a time division connector device, TSW is a time switch, and D is data, which are the same as in FIG.

FIG. 4 shows an embodiment of the frame synchronization monitoring circuit DET shown in FIG. 3, and FIG. 5 shows a time chart showing an example of the operation of FIG. 4.

In FIG. 4, BITCNT is a bit counter that counts the number of clocks C included in one frame of the highway. CO is a carry out and is output when the bit counter BITCNT reaches a predetermined value. ERCNT is an error counter and counts the number of detected failures. Q is the error counter output, and the error counter
Output when ERCNT reaches a predetermined value. EN
is output enable and controls the output of fault information ERR. S is a set signal, and frame F
If it is not detected in a predetermined period, it is output as a failure and the error counter ERCNT is activated.
R is a reset signal, and when frame F is detected at a predetermined period and the bit counter
It is output when frame F is drawn into BITCNT and resets the error counter ERCNT.

Below, the transmission speed 2.04Mb/s explained in Figure 1
The fault detection method will be explained in detail by taking as an example a device that accommodates four highways.

Detection of a fault on each highway is performed by sequentially drawing the clock C and frame F into the frame synchronization monitoring circuit DET by the selection circuit SEL. The monitoring time for each highway is set to be, for example, 1 ms (equivalent to 8 frames), which is sufficient to distinguish between fixed failures such as highway disconnections and intermittent failures such as bit errors due to noise.

The frame synchronization monitoring circuit DET shown in Fig. 4 is
Fault detection is performed using the time chart shown in FIG. 5 and the procedure described below.

(1) Pull in frame F and start the bit counter.
Reset BITCNT and error counter ERCNT.

(2) The bit counter BITCNT counts the number of clocks C, and outputs a carry-out CO when it reaches a predetermined value (256 in this example).

(3) Monitor the match between carry-out CO and frame F, and perform the following processing.

) If they match, output a reset signal R and reset the error counter ERCNT.

) If they do not match, output the set signal S and operate the error counter ERCNT.

(4) When the error counter ERCNT reaches a predetermined value (2 in this example) and outputs Q, it is regarded as a fixed failure and failure information ERR is output. Also, the next frame F is pulled in, and the state returns to (1).

The fault information ERR is sent by the distribution circuit DEC to the holding memory FF installed corresponding to the monitored highway.

The time chart in Figure 5 shows an example of detection when a fault occurs during highway monitoring, but even if a fault occurs outside the monitoring time, the fault will be detected during the next monitoring time. It has the same fault detection ability as when a frame synchronization monitoring circuit DET is installed.

As explained above, by installing the frame synchronization monitoring circuit as shown in FIG. 4 in common for multiple highways as shown in FIG. 3, and monitoring the frame synchronization of each highway in turn, ,
It is possible to detect fixed faults that occur on each highway.

In the above example, the highway transmission speed is
2.048Mb/s, 4 highways with 256 bits per frame, frame synchronization monitoring circuit DET
Although the description has been made assuming that the highway transmission speed, the length of one frame, and the number of highways that share one synchronization monitoring circuit are different from the above example, the present invention is limited to the above example. It is clear that this is not the case.

〔Effect of the invention〕

As described above in detail, according to the present invention,
Since a single frame synchronization monitoring circuit can detect failures of multiple time-division highways, it is possible to economically construct a failure detection circuit for a time-division switch that accommodates and replaces a large number of time-division highways. This effect can be obtained.

[Brief explanation of drawings]

FIG. 1 is a format diagram of an example of a time-division highway, FIG. 2 is a block diagram of an example of a conventional time-division highway fault detection method, and FIG. 3 is an embodiment of a time-division highway fault detection method according to the present invention. FIG. 4 is a block diagram showing an example of the frame synchronization monitoring circuit shown in FIG. 3, and FIG. 5 is a time chart showing an example of the operation of the circuit shown in FIG. HW...Time division highway, REC...Reception circuit, D...Data, C...Clock, F...Frame, DET...Frame synchronization monitoring circuit, ERR...
...fault information, FF...holding memory, TDC...time division connector device, TSW...time switch, R...
...Reset signal, BITCNT...Bit counter,
ERCNT...Error counter, EN...Enable signal, S...Set signal, CO...Carry out, Q...Error counter output.

Claims (1)

[Scope of Claims] 1. A time division switching system comprising a plurality of highways, a time switch, and a time division connector connecting the highways and the time switch, provided corresponding to each highway, a frame synchronization monitoring circuit that monitors whether or not the highway frame is periodically added, and outputs failure information if not added. a selection circuit that sequentially draws the clocks and frames of each of the receiving circuits to the frame synchronization monitoring circuit; and a plurality of holding memories provided corresponding to each of the highways that monitors failure information of the frame synchronization monitoring circuit. , a distribution circuit that distributes failure information of the frame synchronization monitoring circuit to the plurality of holding memories, and a timing circuit that creates timing necessary for controlling the selection circuit, the distribution circuit, and the frame synchronization monitoring circuit. Time-division highway fault detection, characterized in that the clocks and frames of each of the highways are drawn into the frame synchronization monitoring circuit by the selection circuit, and the frame synchronization monitoring circuit sequentially monitors the synchronization of each of the highways. method. 2. The frame synchronization monitoring circuit counts the number of clocks included in one frame of the highway, and when the count reaches a predetermined value, a bit counter that outputs a carry out; An error counter that counts and outputs an error counter signal when the counted value reaches a predetermined value, and a carry-out of the bit counter, and when the above frame is received and the frame is not detected in a predetermined period, the error counter outputs the error counter signal. a circuit for outputting a set signal for setting a counter and a reset signal for resetting the error counter when a frame is detected at a predetermined period and when a frame is drawn into the bit counter; and an error counter signal for the error counter. and a circuit for receiving the output enable and controlling the fault information, according to claim 1.