JPH0437517B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a refresh address circuit in a memory circuit.

[Prior art] Fig. 4 shows addresses 0-n to 0-n.
FIG. 2 is a circuit diagram showing an example of a conventional refresh address circuit that extends a refresh address to address +1.

For convenience of explanation, the following explanation will be given using the well-known microprocessor Z80 (μPD780C/D) as an example.

In this example, in the initial state, a reset signal is inputted to the clear terminal CLFAR of the n+2 bit binary counter 13 via the inverter 12. Therefore, the refresh signal is passed through the inverter 11 to the binary counter 1.
After the binary counter 13 performs a counting operation, the output Q and the memory access address A _o+1 given from the program counter built into the processor (not shown) are given to the multiplexer 14.

On the other hand, the refresh signal is also input to the select terminal of the multiplexer 14,
The multiplexer 14 distributes the above-mentioned input data, and the above-mentioned memory access address A _o+1 is
It is assigned to the output C _o+1 of the multiplexer 14.

In the refresh process when the above-mentioned refresh signal is "0", the refresh addresses A ₀ to A _o given from the program counter in the processor (not shown) are supplied to the multiplexer 15, and A ₀ along with C _o+1 are supplied to the multiplexer 15. Constructed as an address extended with ~A _o .

The multiplexer 16 receives this address and the other address A ₍₀₎ , which is also given from the program counter in the processor (not shown) mentioned above.
A(1), . . . , A _(o+1) are switched according to the input state of the multiplexer switching signal, and one of them is output.

Therefore, this multiplexer switching signal
Multiplexer 15 controlled by MUX
One of the above addresses is supplied to the address input terminal of the memory 16 as the memory addresses MA ₀ , MA ₁ , ..., MA _o+1 via , are taken into memory 16.

The multiplexer switching signal, row address strobe signal, reset signal, and refresh signal explained above are all output from a microprocessor (Z80=μPD780C/D), not shown, as is well known. , details are omitted here.

[Problems to be Solved by the Invention] From the above, in the refresh process where the refresh address size is fixed, from the row pulse width of the row address strobe signal,
If the panel width of the refresh signal is fixed at a small timing, when the row address strobe signal transitions from high level to low level, memory address MA _o+1 as part of the refresh address is not valid, and the memory The problem was that it malfunctioned. (References:
ELECTRONICS, MAY.22, 1980) Therefore, an object of the present invention is to smoothly supply addresses, increment the refresh address whose refresh address size is fixed, and use the low address strobe signal during the refresh process.
Refresh signal from RAS low pulse width
An object of the present invention is to provide a refresh address circuit that does not cause any trouble in forming a refresh address even at a timing when the RFSH low pulse width is small.

Further, the present invention uses the machine cycle signal ₁ as the gate signal and uses A ₀ to A _o as the address.
By using a signal created by this method, an extended refresh address is supplied to the memory after a reset, and there is no problem in memory access, and the issue of refresh address supply failure after a reset is solved. It is characterized by what it did.

[Means for Solving the Problems] That is, the refresh address circuit of the present invention includes at least a program counter, and thereby the first address A ₀ , A ₁ , . . . , A _o and the second address A set consisting of A _o+1 and a third address A ₍₀₎ , A(1), consisting of the same number of bits.
..., A _(o) and A _(o+1) , as well as machine cycle signal ₁ , memory request signal, refresh signal, reset signal, multiplexer switching signal, and row address strobe signal. The memory has (n+1) address input terminals and receives one of the memory access addresses upon input of the row address strobe signal.

Further, the refresh address circuit of the present invention further includes a first inverter that inverts the memory request signal, and a first inverter that inverts the memory request signal.
Input the second inverter that inverts RFSH, the outputs of the first and second inverters, and the first address A ₀ , A ₁ , ..., A _o given from the program counter built in the processor. a D-flip-flop which takes the reset signal as its clear input, takes the output of the NAND circuit as its clock input, and takes its inverted output as its own data input, and takes the machine cycle signal ₁ as its input. A one-shot multivibrator, and a first gate which outputs the non-inverting output Q given from the D-flip-flop by being supplied with the non-inverting output F of the one-shot multivibrator, and a first gate of the one-shot multivibrator When the inverted output G is supplied, the second address (A _o +1) given from the program counter built in the processor is outputted, and the output of the first gate and the outputs are connected. By inputting the outputs of the second gate and the first and second gates as the fourth address C _o+1 , the above address is combined with the first address A ₀ , A ₁ , ..., A _o It constitutes one of the two sets of memory access addresses, and the third address A ₍₀₎ ,
By configuring A(1), ..., A _(o) , A _(o+1) as the other memory access address, the above two sets of memory access addresses are formed, and one or the other of these memory access addresses is The multiplexer selectively outputs any one of the following to the (n+1) address input terminals of the memory in accordance with the supply of the multiplexer switching signal.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. For convenience of explanation, the following explanation will be given using an example using the same well-known microprocessor as exemplified in the explanation of the prior art.

FIG. 1 is a circuit diagram showing an embodiment of the refresh address circuit of the present invention (including memory).
It is.

First, the first inverter 1 inverts the memory request signal. Further, the second inverter 2 inverts the refresh signal.

The NAND circuit 3 receives first addresses A ₀ , A ₁ , ..., A _o given from a program counter built into a microprocessor (not shown), and outputs A and C of the first and second inverters 1 and 2. and enter
Outputs signal B.

The one-shot multivibrator 4 inputs a machine cycle signal ₁ given from a microprocessor (not shown), outputs a non-inverting output F from a non-inverting output terminal OUT, and outputs an inverting output G from an inverting output terminal.

In the D-flip-flop 5, the output signal B of the NAND circuit 3 is input to the clock terminal CK, and the reset signal is input to the receiver terminal CLR. This D-flip-flop 5 outputs a signal D from its non-inverting output terminal Q, and inputs an output signal E from its inverting output terminal to its own data input terminal D.

The first gate 6 receives the output signal D of the D-flip-flop 5, and when the non-inverted output F of the one-shot multivibrator 4 is "0", it passes the input signal D as is.

The second gate 7 receives the most significant bit of the memory access address given from the program counter built into the microprocessor (not shown), that is, the second address A _o+1 , and receives the inverted output G of the one-shot multivibrator 4. 0'', this second address A _o+1 is passed through as is.

The output sides of the first and second gates 6 and 7 are short-circuited at a point H.

Although the details will be described later, the signal appearing at the connection point H between the first and second gates 6 and 7 is defined as the fourth address C _o+1 .

Multiplexer 8 receives two sets of input addresses from a program counter built into a well-known microprocessor (not shown).

That is, the input addresses of one set are the above-mentioned first addresses A ₀ , A ₁ , . . . , A _o and the fourth address C _o+ appearing at the connection point H between the first and second gates 6 and 7. It consists of ₁ .

Also, as the input address for the other set,
Similarly to the above, the third input signal is supplied from the program counter built into the microprocessor (not shown).
Addresses A ₍₀₎ , A(1), ..., A _(o) , A _(o+1) are given.

This selection switching between one input address and the other input address is performed by a multiplexer switching signal also applied from a microprocessor (not shown).

Multiplexer 8 is a multiplexer switching signal
When MUX is “1”, the first address mentioned above
One set of input addresses consisting of A ₀ , A ₁ , ..., A _o and the fourth address C _o+1 is output to the output terminal Y ₀ ,
Output from Y ₁ , ..., Y _o+1 .

Further, when the multiplexer switching signal is "0", the multiplexer 8 selects the third address A ₍₀₎ , which is the input address of the other set mentioned above.
A(1), ..., A _(o) , A _(o+1) are output terminals Y ₀ , Y ₁ , ...
..., output from Y _o+1 .

The memory 9 is connected to the output terminal Y ₀ of the multiplexer 8,
By applying the low address strobe signal to the signal output from Y ₁ , ..., Y _o+1 , the memory address MA ₀ , MA ₁ , ..., MA _o+1
be taken in as.

Next, the operation of the refresh address circuit of this embodiment will be explained with reference to the time charts of FIGS. 2 and 3.

First, the reset signal is "0" and is input to the reserve terminal CLR of the D-flip-flop 5. With the output signal D of the D-flip-flop 5 being "0", the refresh address circuit is It has been initialized.

After that, it is assumed that the reset signal becomes "1" at time _t1 .

After initialization, machine cycle signal M ₁ is (n+1)
Although it changes from "1" to "0" at the second time (that is, at time t ₂ ), the non-inverted output F of the one-shot multivibrator 4 remains "1" and the inverted output G remains "0". , the second gate 7 is opened and the first gate 6 is closed.

The previously mentioned program counter (not shown) is
The above-mentioned first addresses A ₀ , A ₁ , ..., A _o and the second
Address A _o+1 and third address A ₍₀₎ , A(1),...
..., A _(o) , and A _(o+1) are placed on an address bus (not shown), so the second address A _o+1 appears at point H.

Here, since the multiplexer switching signal is "1", the signal at point H, that is, the second address A _o+1 is the output terminal Y _o+1 of the multiplexer 8.
This is the memory address of memory 9.
It is given as MA _o+1 . This memory address MA _o+1 is the row address strobe signal
At edge time _t3 when RAS becomes "0", it is taken into the memory 9.

In other words, when the multiplexer switching signal is "1", the first address A ₀ , A ₁ , ..., A _o
, the fourth address C _o+1 becomes the output of multiplexer 8, and the memory address of memory 9 is changed at the falling edge of the row address strobe signal.
It is taken in as MA ₀ , MA ₁ , ..., MA _o+1 .

However, at this stage, in the well-known microprocessor (Z80), the memory address MA _o+1 is set to "0".

In the refresh process in the second half of the machine cycle (time t ₃ to t ₅ ), first, the machine cycle signal ₁ changes to "1" and the first addresses A ₀ , A ₁ , . . .
All A _o become “1”.

The non-inverting output F of the one-shot multivibrator 4 changes to “0” after an internal delay and is output to the first gate 6.
opens. As a result, the output signal D of the D-flip-flop 5 (D at this time is "0") appears at point H as it is. At this time, the multiplexer switching signal
Since MUX is "1", the signal at point H, that is, the signal "0" appears at the output terminal Y _o+1 of the multiplexer 8.

Therefore, the input of the multiplexer 8 includes the first
Since the addresses A ₀ , A ₁ , ..., A _o have already been supplied, the other output terminals Y ₀ , A o of the multiplexer 8
Y ₁ , ..., Y _o also has the first address A ₀ , A ₁ , ...,
A _o appears as it is, and at the falling edge of the row address strobe signal, MA ₀ , MA ₁ , ..., MA _o ,
MA _o+1 is fetched and memory 9 is refreshed. However, at this stage, the memory address
MA _o+1 is "0".

The next machine cycle shown in FIG. 3 (from time _t5 to
t ₆ ), in the first half, an address supplied from a program counter (not shown) is supplied to the memory address of the memory 9.

In addition, in the latter half, the machine cycle signal ₁ changes from "0" to "1", and the non-inverted output F of the one-shot multivibrator 4 becomes "0" after an internal delay, so the first gate 6 is opened. ,
The output signal D of the D-flip-flop 5 (signal D is "1" at this time) appears at point H.

On the other hand, since the inverted output G of the one-shot multivibrator 4 is "1", the second gate 7 is closed and the second address A _o+1 does not appear at point H. Also, since the multiplexer switching signal is "1", the output terminal of multiplexer 8
Y _o+1 is “1”.

Therefore, the row address strobe signal
On the falling edge of RAS, the memory address is
MA ₀ , MA ₁ , ..., MA _o , MA _o+1 (at this time
(MA _o+1 is "1") is taken into the memory 9, and the memory 9 is refreshed.

[Effects of the Invention] As explained above, according to the present invention, while supplying addresses for memory access smoothly,
A circuit that increments a refresh address with a fixed refresh address size is obtained, and even at a timing when the row pulse width of the refresh signal is smaller than the row pulse width of the row address strobe signal during the refresh process, it is difficult to form a refresh address. A circuit without

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the refresh address circuit of the present invention, FIGS. 2 and 3 are time charts thereof, and FIG. 4 is a circuit diagram of a conventional example of the refresh address circuit. . 1...First inverter, 2...Second inverter, 3...NAND circuit, 4...One-shot multivibrator, 5...D-flip-flop,
6...First gate, 7...Second gate, 8...Multiplexer, 9...Memory, ₁ ...Machine cycle signal,...Memory request signal,
RFSH...Refresh signal,...Reset signal,...Multiplexer switching signal,
RAS...Row address strobe signal, A ₀ ,
A ₁ , ..., A _o ... 1st address, A _o+1 ... 2nd address
Address, A ₍₀₎ , A(1), ..., A _(o) , A _(o+1) ...Third address, C _o+1 ...Fourth address, MA ₀ ,
MA ₁ , ..., MA _o , MA _o+1 ... memory address.

Claims (1)

[Scope of Claims] 1. At least a program counter is built in, whereby a set consisting of first addresses A ₀ , A ₁ , . . . , A _o and a second address A _o+1 and an equal number of The third address consisting of bits A ₍₀₎ , A(1),
..., A _(o) and A _(o+1) , as well as machine cycle signal ₁ , memory request signal, refresh signal, reset signal, multiplexer switching signal, and row address strobe signal. A refresh address circuit comprising: a microprocessor that outputs a memory access address as appropriate; and a memory having (n+1) address input terminals and receiving one of the memory access addresses upon input of the row address strobe signal. a first inverter that inverts the memory request signal; a second inverter that inverts the refresh signal; outputs of the first and second inverters and a program counter built in the processor; A NAND circuit whose inputs are the given first addresses A ₀ , A _{1 ,} . A D-flip-flop which takes the data input of the D-flip-flop, a one-shot multivibrator which takes the machine cycle signal ₁ as an input, and a non-inverting output F of this one-shot multivibrator are supplied, so that the data given from the D-flip-flop is A first gate that outputs a non-inverted output Q and an inverted output G of the one-shot multivibrator are supplied, so that the second address (A _o +1) given from a program counter built in the processor is read. a second gate which connects the output of the first gate and the outputs; and a fourth address for the output of the first and second gates.
By inputting as C _o+1 , the second address is combined with the first address A ₀ , A ₁ , ..., A _o
The third address A ₍₀₎ , A(1),
By _{configuring .} , a multiplexer that selectively outputs to (n+1) address input terminals of the memory in accordance with the supply of the multiplexer switching signal.