JPH0437672B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a control device for a pulse width modulation (hereinafter referred to as PWM) inverter. [Prior Art] There is a PWM inverter control device using a microprocessor as shown in FIG. In the figure, 1 transfers data stored in a memory 2 (described later) to first and second counters 4 and 5.
2 is a memory that stores data related to the time from a certain time reference point to the rising and falling points of a pulse train of a PWM pulse pattern; 3 is a memory that sequentially latches the data stored in memory 2 for a certain period of time; parallel I/O
Ports 4 and 5 are the first ports that respectively set data regarding the time to the rising and falling points of one pulse of the pulse train of the PWM pulse pattern latched by the parallel I/O port 3.
and a second counter 6 are RS flip-flops which input the output of the first counter 4 as a set signal and input the output of the second counter 5 as a reset signal. Note that the microprocessor 1, memory 2, parallel I/O port 3, first and second counters 4, 5, and
The pulse forming circuit 20 is composed of an RS flip-flop. 7 is an oscillator that generates a clock signal to be input to the first and second counters 4 and 5; 8 is a frequency divider that divides the output of the oscillator 7 to a desired carrier frequency and outputs a divided signal; 9 inputs the output of the frequency divider 8 to the first and second counters 4,
This timing signal generation circuit generates a load signal to be input to the microprocessor 5 and an interrupt signal to be input to the microprocessor 1. Next, the operation will be briefly explained with reference to the time chart in FIG. A time reference point is provided, for example, for each carrier period Tc', and data t ₁₁ , t ₁₂ , t ₂₁ , regarding the time from the reference point to the rise time and fall time of each of the above-mentioned pulses are provided.
t ₂₂ , t ₃₁ , and t ₃₂ are previously stored in the memory 2 in address order. Now, every time the interrupt signal E outputted from the timing signal generation circuit 9 at times T ₁ , T ₂ , T ₃ , and T ₄ rises, an interrupt is applied to the microprocessor 1, and for convenience, the microprocessor 1 is read out from the memory 2. Assuming that the first data to be processed is t ₂₁ , data t ₂₁ is transferred from time T ₁ to parallel I/O port 3 after the unique processing time θ of microprocessor 1 has elapsed due to interrupt signal E output at time T ₁ . The data t ₂₂ is then read out from the memory 2, and after the processing time θ has elapsed, the data t ₂₂ is latched at the I/O port 3. Data F output from this I/O port 3
(t ₂₁ ) and G(t ₂₂ ) are set in the first and second counters 4 and 5, respectively, when the load signal D output from the timing signal generation circuit 9 at time T ₂ becomes "H". In response to the clock signal A output from the oscillator 7, the first and second counters 4 and 5 start counting down from the falling edge of the load signal D, and when time _t21 is counted, the first counter 4 starts counting down the RS. A set signal is applied to the S input of the flip-flop 6, and the output Q of the flip-flop 6 becomes "H". In addition, the second counter 5
When the time _t22 is counted down, a reset signal is applied from the second counter 5 to the R input of the RS flip-flop 6, and the output Q of the flip-flop 6 is inverted from "H" to "L". That is,
During the period _t22 - _t21 , the output Q of the flip-flop 6 becomes "H", and a pulse (2) as shown at J in FIG. 6 is output. By the way, since the next interrupt signal E is output at time _T2 , data _t31 and _t32 are successively latched at I/O port 3 every processing time θ of microprocessor 1. These data F(t ₃₁ ) and G(t ₃₂ ) are respectively set in the counters 4 and 5 by the load signal D output at time T ₃ , and when each countdown is started by the clock signal A as described above, During the period t ₃₂ -t ₃₁ , the output Q of the flip-flop 6 becomes "H", and then a pulse (3) as shown at J in FIG. 6 is output. In this way, the data t ₁₁ and t ₁₂ are set to t ₁₂ by the load signal D output at time T ₁ .
In the period -t ₁₁ , the output Q of the flip-flop 6 becomes "H", and the pulse (1) as shown in J in Fig. 6 is output, and finally as shown in J in Fig. 6.
Pulse trains (1) to (3) are output. Note that the pulse width of the load signal D (interrupt signal E) is assumed to be very narrow. [Literature: Materials from the 57th Power Electronics Study Group (Problems in waveform improvement of high-frequency PWM inverters)] [Problems to be solved by the invention] In the above-mentioned device, an 8-bit general-purpose microprocessor is used as the microprocessor. When using a processor, the time θ for processing one piece of data stored in memory by this microprocessor is approximately
200 μs, and approximately 400 μs is required to process two pieces of data for one pulse, that is, data related to the time from a certain time reference point to the rise and fall points of the pulse. Therefore, because it is limited by the processing time of the microprocessor, conventional control devices cannot reduce the carrier period (hereinafter referred to as the unique carrier period Tc') to approximately 400 μs or less.
In other words, there is a problem that the carrier frequency cannot be increased to 2.5 KHz or higher. [Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention has the following features:
In the invention, a microprocessor, a memory for storing data relating to the time from a certain time reference point to the rising time and falling time of a pulse train of a PWM pulse pattern, or data relating to the time to the rising time or falling time of a pulse train of a PWM pulse pattern; A parallel I/O port that latches data of one pulse of a pulse train, first and second counters that each set two pieces of data latched by the parallel I/O port, and a first and second counter that each sets two pieces of data latched by the parallel I/O port. n pulse forming circuits with n=2 or more consisting of RS flip-flops whose outputs are input;
An OR circuit that ORs the outputs of n pulse forming circuits, an oscillator that generates a clock signal to input to the first and second counters, a frequency divider that divides the output of the oscillator, and an output from the frequency divider. An n-bit shift register operated by a frequency-divided signal, and an n-bit shift register that generates a load signal for inputting each output of the shift register to the first and second counters and an interrupt signal for inputting to the microprocessor. It consists of a timing signal generation circuit means. In the second and third inventions, one pulse forming circuit may use only one counter, and the other means are the same. [Operation] For example, when there are two pulse forming circuits, a time difference between an interrupt signal for the first microprocessor and an interrupt signal for the second microprocessor is generated by a 2-bit shift register, and the time difference between the interrupt signal for the first microprocessor and the interrupt signal for the second microprocessor is The time difference is set to 1/2 of the unique carrier period Tc′ which is limited by the processing time of the microprocessor, and the ON period of each pulse of the PWM pulse pattern is set to 1/2 of the unique carrier period Tc′.
The desired carrier period by
Tc can be set to Tc'/2. That is, the desired carrier frequency is equal to the unique carrier frequency 1/
It becomes twice as much as Tc′. Therefore, the number of pulses included in a half cycle of the inverter's output frequency can be doubled. [Example] Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the present invention, and the difference from FIG. 4 is that a second pulse forming circuit 21 is added to the first pulse forming circuit 20.
and first and second pulse forming circuits 20 and 21
An OR circuit 10 that ORs the outputs of
1 to the counters 4 and 5 of the first and second pulse forming circuits 20 and 21 and an interrupt signal to the microprocessor 1. This is because two timing signal generation circuits 12 and 13 are added. Note that the same components as in FIG. 4 are given the same reference numerals. Next, the operation will be explained with reference to the time chart in Fig. 5. Here, as shown by J in the figure, the number of pulses included in a half cycle of the inverter's output frequency is 6, These are H
A certain time reference point is provided, for example, for each unique carrier period Tc' as shown in I, and data regarding the time from that reference point to the rising and falling points of each of the above pulses t ₁₁ , t ₁₂ , t ₂₁ , t ₂₂ , t ₃₁ ,
t ₃₂ , t ₄₁ , t ₄₂ , t ₅₁ , t ₅₂ , t ₆₁ , t ₆₂ (however, t ₁₂ −
t ₁₁ , t ₂₂ −t ₂₁ , t ₃₂ −t ₃₁ , t ₄₂ −t ₄₁ , t ₅₂ −t ₅₁ , t ₆₂ −
Let t ₆₁ < Tc. ) of t ₁₁ , t ₁₂ , t ₃₁ , t ₃₂ ,
t ₅₁ and t ₅₂ are memory 2 of the first pulse forming circuit 20
Furthermore, t ₂₁ , t ₂₂ , t ₄₁ , t ₄₂ , t ₆₁ , and t ₆₂ are stored in advance in the memory 2 of the second pulse forming circuit 21 in address order. Now, preset the shift output C1 of the 2-bit shift register ₁₁ to "H" and the shift output _C2 to "L" between _T1 and _T2 , so that the frequency-divided signal B is transferred to the 2-bit shift register 11. , the respective outputs become as shown in C ₁ and C ₂ in FIG. 5, and the first timing signal generation circuit 1
2, the microprocessor 1 of the first pulse forming circuit 20 is interrupted every time the interrupt signal E ₁ is output at times T ₁ , T ₃ , T ₅ , and T ₇ .
The beginning of data read from the memory 2 of the first pulse forming circuit 20 is assumed to be t ₃₁ . Due to the interrupt signal _E1 output at time _T1 , data _t31 is latched at I/O port 3 after the processing time θ of microprocessor 1 has elapsed since time _T1 , and then data _t32 is read from memory 2. The data _t32 is latched at the I/O port 3 after the processing time θ has elapsed. These data F ₁ (t ₃₁ ) and G ₁ (t ₃₂ ) are transmitted to the first pulse forming circuit when the load signal D ₁ output from the first timing signal generating circuit 12 at time T ₃ becomes “H”. 20 counters 4 and 5 respectively, each starts counting down as described above, and when the time _t31 is counted, a set signal is applied from the counter 4 to the S input of the RS flip-flop 6, and the output Q of the flip-flop 6 becomes It becomes "H". Also, when the counter 5 counts down _t32 time, the counter 5 indicates the R of the RS flip-flop 6.
A reset signal is applied to the input, and the output Q of the flip-flop 6 is inverted from "H" to "L". That is, in the period t ₃₂ - t ₃₁ , the output Q of the flip-flop 6 becomes "H", as shown in H in FIG.
Pulse (3) is output. By the way, since the next interrupt signal _E1 is output from the first timing signal generation circuit 12 at time _T3 , the data _t51 is generated every processing time θ of the microprocessor 1 of the first pulse forming circuit 20 . , t ₅₂ consecutively to I/O port 3
This data F ₁ (t ₅₁ ),
G ₁ (t ₅₂ ) is set in the counters 4 and 5 by the load signal D ₁ output at time T ₃ , and when each starts counting down as described above, t ₅₂ −
During the period _t51 , the output Q of flip-flop 6 becomes “H”.
Then, a pulse (5) as shown at H in FIG. 5 is output. In this way the data t ₁₁ ,
For t ₁₂ , load signal D ₁ output at time T ₁
As a result, the output Q of the flip-flop 6 becomes "H" in the period t ₁₂ - t ₁₁ , as shown in H in FIG.
Pulse (1) is output. On the other hand, the second timing signal generation circuit 13 generates a signal that is delayed by Tc'/ ₂ from the interrupt signal E 1 outputted by the 2-bit shift register 11 at times T ₁ , T ₃ , and T ₅ . Interrupt signals output at times T ₂ , T ₄ , and T ₆
Every _E2 , an interrupt is applied to the microprocessor 1 of the second pulse forming circuit 21, and for convenience, the beginning of the data read from the memory 2 of the second pulse forming circuit 21 is assumed to be _t41 . Due to the interrupt signal _E1 output at time _T2 , the data _t41 is transferred to the I/O after the processing time θ of the microprocessor 1 has elapsed from time _T2 .
Data t42 is latched at O port 3, and then data _t42 is latched at I/O port 3 after processing time θ has elapsed. These data F ₂ (t ₄₁ ) and G ₂ (t ₄₂ ) are sent to the second pulse forming circuit when the load signal D ₂ output from the second timing signal generating circuit 13 at time T ₄ becomes “H”. When the counters 4 and 5 of the flip-flop 21 are set respectively and each starts counting down as described above, the output Q of the flip-flop 6 becomes "H" in the period t ₄₂ - t ₄₁ , and the output as shown in I in FIG.
Pulse (4) is output. In this way the data
For t ₆₁ , t ₆₂ and t ₂₁ , t ₂₂ , see I in FIG.
Pulses (6) and (2) as shown in the figure are output, and finally the pulse train of (1) to (6) as shown in J in the figure is output.
It is output from the OR circuit 10. Note that the data t ₁₁ up to the rise point mentioned above,
_{The fifth _ _ _ _ _ _ _ _ _ _ _}
If each pulse of the pulse train (1) to (6) as shown in J in the figure is made to be symmetrical with respect to the center of the desired carrier period Tc, t ₁ is Tc - T ₂ , or t ₂ is Tc
-t ₁ , the data group t ₁ or t ₂ is stored in the memory 2 of the first and second pulse forming circuits 20 and 21 . For example, t ₁₁ , t ₃₁ , t ₅₁ and t ₂₁ , t ₄₁ , t ₆₁ of data group t ₁ up to the rising time
are stored in advance in memory 2 in address order, as explained in FIG.
The data t ₃₁ read from is latched at the I/O port 3 after the processing time θ of the microprocessor 1 has elapsed, and then Tc - T ₃₁ is processed by the microprocessor 1, and the calculation result t ₃₂ =Tc −
It is sufficient if _t31 is latched at I/O port 3. The following description is omitted since it is the same as the case described above. FIG. 2 is a block diagram showing a second embodiment of the present invention, and the difference from FIG.
The first counter 4 of the pulse forming circuits 20 and 21 is no longer necessary, and the load signal (interrupt signal) output from the first and second timing signal generation circuits 12 and 13 is This is applied to the S inputs of the RS flip-flops 6 of the formation circuits 20 and 21 , respectively. Next, (1), (3), shown in H and I of Figure 5,
To explain using the data of each pulse in (5), (2), (4), and (6) as is, the ON period of each pulse shown in H in the figure is t ₁₂ −t ₁₁ = t ₁ a, t ₃₂ −t ₃₁ = t _3a ,
t ₅₂ - t ₅₁ = t _5a , and the ON period of each pulse shown in I in the figure is t ₂₂ - t ₂₁ = t _2a , t ₄₂ - t ₄₁ = t _4a ,
Since t ₆₂ −t ₆₁ = t _6a , the data t _1a , t _3a , t _5a and t _2a , t _4a , t _6a are stored in the memories 2 of the first and second pulse forming circuits 20 and 21 in the order of their addresses, respectively. Make sure to memorize it in advance. However, t _1a , t _3a , t _5a ,
Let t _2a , t _4a , t _6a <Tc. ) Now, for each interrupt signal E ₁ outputted from the first timing signal generation circuit 12 at times T ₁ , T ₃ , T ₅ , and T ₇ , the microprocessor 1 of the first pulse forming circuit 20 is For convenience, let t _3a be the beginning of the data read from the memory 2 when an interrupt occurs, and the interrupt signal E ₁ output at time T ₁ causes the data t _3a to be read out after the processing time θ of the microprocessor 1 has elapsed. Latched at I/O port 3. At time _T3 , the load signal _D1 output from the first timing signal generation circuit 12
(interrupt signal E ₁ ) is given to the S input of flip-flop 6, and the output Q of flip-flop 6 goes "H".
With this load signal D ₁ , the data F _a (t _3a )
is set in counter 5, starts the countdown as described above, and counts the time _t3a .
A reset signal is applied from the counter 5 to the R input of the flip-flop 6, and the output Q of the flip-flop 6 becomes "L". That is, from time T ₃ to t _3a
Until the end of the period, the output Q of the flip-flop 6 becomes "H", and a pulse (3) as shown at _J1 in FIG. 5 is output. In this way the data t _1a , t _5a
(1) and (5) as shown in J ₁ of Figure 5, respectively.
If the data read from the memory 2 of the second pulse forming circuit _{21 by the interrupt signal E 2 outputted} from the second timing signal generating circuit 13 at time T 2 is t _4a , then the pulse of , this data _t4a is latched at the I/O port 3 after the processing time θ of the microprocessor 1 has elapsed. time
When T ₄ is reached, the second timing signal generation circuit 1
The load signal D ₂ (interrupt signal E ₂ ) output from the flip-flop 6 is applied to the S input of the flip-flop 6, and the output Q of the flip-flop ₆ becomes " _{H "} . is set in counter 5. The following description is omitted since it is the same as the case described above. In this way the data t _2a , t _4a , t _6a
(2), as shown in J ₁ of Figure 5, respectively.
Pulses (4) and (6) are output, and finally a pulse train of (1) to (6) as shown at _J1 in the figure is output from the OR circuit 10. FIG. 3 is a block diagram showing a third embodiment of the present invention, which differs from FIG. 1 in that the second counter 5 of the first and second pulse forming circuits 20 and 21 is not required; Further, load signals (interrupt signals) output from the first and second timing signal generation circuits 12 and 13 are applied to the R inputs of the RS flip-flops of the first and second pulse forming circuits 20 and 21 , respectively. It is that you are. Next, using the data of each pulse shown in H and I in FIG. 5 as is, the OFF period of pulses (1) and (3) shown in H in the same figure is Tc-
If t ₁₂ + Tc + t ₃₁ = t ₃ b > Tc, and this t _3b is defined as the OFF period of the pulse in (3), then (1), (5) and
The OFF periods of each pulse (2), (4), and (6) are t _1b and t _5b, respectively.
and can be expressed as t _2b , t _4b , t _6b , so the data
t _1b , t _3b , t _5b and t _2b , t _4b , t _6b as the first and second
The pulse forming circuits 20 and 21 are stored in memory 2 in address order in advance (however,
t _1b , t _5b , t _2b , t _4b , t _6b > Tc). Now, for convenience, the beginning of the data read from memory 2 is
Assuming t _3b , data t _3b is latched at the I/O port by the interrupt signal E ₁ output at time T ₁ .
At time _T3 , the load signal _D1 (interrupt signal
E ₁ ) is applied to the R input of flip-flop 6,
The output Q of the flip-flop 6 becomes "L", data F _b (t _3b ) is set in the counter 4 by this load signal D ₁ , and when the countdown is started as described above and the time t _3b is counted, the data from the counter 4 is A set signal is applied to the S input of the flip-flop 6, the output Q of the flip-flop 6 becomes "H", and the load signal _D1 is output at time _T5 .
(Interrupt signal E ₁ ) causes the output Q of the flip-flop 6 to become "L". That is, from time T ₃ to t _3b
During the period from the time after the lapse of time to time _T5 , the output Q of the flip-flop 6 becomes "H", and a pulse (3) as shown at _J2 in FIG. 5 is output. In this way, for data t _1b and t _5b , the fifth
Pulses (1) and (5) as shown in _J2 in the figure are output. On the other hand, due to the interrupt signal E ₂ output at time T ₂ ,
Data _t4b read from the memory 2 of the second pulse forming circuit 21 is latched at the I/O port 3. At time T ₄ , load signal D ₂ (interrupt signal
E ₂ ) is applied to the R input of flip-flop 6,
The output Q of the flip-flop 6 becomes "L", and this load signal D ₂ (interrupt signal E ₂ ) causes the data F _b
(t _4b ) is set in counter 4. The following description is omitted since it is the same as the case described above. In this way, for the data t _2b , t _4b , and t _6b , pulses (2), (4), and (6) as shown in J ₂ of Fig. 5 are output, respectively, and finally the pulses shown in Fig. 5 are output. Pulse trains (1) to (6) as shown in _J2 are output from the OR circuit 10. In the above explanation, the desired carrier period Tc is set to 1/2 of the specific carrier period Tc′, but considering the variation in processing time of the microprocessor,
It is more preferable to allow a little margin for Tc'/2. [Effects of the Invention] As described above, according to the present invention, the time difference between each interrupt signal to the microprocessor of n pulse forming circuits can be reduced by the processing time of the microprocessor. carrier period of
By setting Tc' to 1/n or more and making the ON period of each pulse of the PWM pulse pattern 1/n or less of the unique carrier period Tc', the desired carrier period Tc' can be set to Tc'/n. can do. That is,
The maximum value of the carrier frequency can be made up to n times the inherent carrier frequency 1/Tc'. Therefore, a general-purpose microprocessor can calculate the number of pulses included in a half cycle of the inverter's output frequency by n.
Can be doubled. In other words, the larger the value of n, the more an AC output with a lower harmonic content can be obtained. In addition, in the first invention, since only data related to the time from a certain time reference point to the rising or falling point of each pulse of the PWM pulse pattern is stored in the memory, the memory capacity is smaller than that of the conventional device. storage capacity can be halved. Furthermore, in the second invention, in addition to the first effect, by setting the rising time or falling time of each pulse of the PWM pulse pattern at each unique carrier period Tc', the rising time or the falling time Since there is no need to count the time until the end, the pulse forming circuit can have only one counter.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the invention, FIG. 2 is a block diagram showing a second embodiment of the invention, and FIG. 3 is a block diagram showing a third embodiment of the invention. , FIG. 4 is a block diagram of the conventional device, FIG. 5 is an operation waveform diagram explaining the operation of FIGS. 1 to 3, and FIG. 6 is an operation waveform diagram explaining the operation of FIG. 4. 1...Microprocessor, 2...Memory,
4, 5...Counter, 6...Flip-flop,
7... Oscillator, 8... Frequency divider, 10... OR circuit, 11... n-bit shift register, 12, 1
3...n timing signal generation circuits, 20 , 2
1...n pulse forming circuits.

Claims (1)

[Scope of Claims] 1. A memory that stores data regarding the time of a pulse train of a PWM pulse pattern, and first and second counters that are set in accordance with data of one pulse of the pulse train read from the memory; n pulse forming circuits (where n≧2 is an integer) each consisting of a microprocessor that sends data stored in the memory to the counter, and a flip-flop that receives each output of the counter as input; an oscillator that generates a clock signal to be input to the oscillator, a frequency divider that divides the output of the oscillator to a desired carrier frequency, and an n-bit shift register that operates with the frequency-divided signal output from the frequency divider. , n timing signal generation circuits that input the n outputs of the shift registers to the counters and microprocessors of the n pulse forming circuits as load signals and interrupt signals, respectively; and the n pulse forming circuits. A control device for a pulse width modulation inverter equipped with an OR circuit that ORs the outputs of the circuit. 2. The pulse width modulation inverter according to claim 1, wherein the first and second counters are each set with data regarding the time from a certain time reference point to the rising and falling points of the pulse train. Control device. 3. The first counter is set with data regarding the time from a certain time reference point to the rising or falling time of the pulse train, and the second counter is set with data regarding the time from a certain time reference point to the rising or falling time. 2. The control device for a pulse width modulation inverter according to claim 1, wherein data regarding the time up to the falling point or the rising point calculated based on the pulse width modulation inverter is set. 4 A memory for storing data regarding the time of a pulse train of a PWM pulse pattern, a counter for setting data of one pulse of the pulse train read from the memory, and sending the data stored in the memory to the counter. n units (where n≧
2), an oscillator that generates a clock signal to be input to the counter, a frequency divider that divides the output of the oscillator to a desired carrier frequency, and a frequency divider that divides the output from the frequency divider into a desired carrier frequency. an n-bit shift register that operates with a frequency-divided signal, and outputs each of the n outputs of the shift register to the counter, microprocessor, and flip-flop of the n pulse forming circuits as a load signal, an interrupt signal, and a set signal, respectively. A control device for a pulse width modulation inverter, comprising n timing generation circuits that input as a reset signal, and an OR circuit that ORs the outputs of the n pulse formation circuits. 5 The data is for each pulse of the pulse train.
The control device for a pulse width modulation inverter according to claim 4, wherein the ON period time is the time of the ON period. 6 The data is for each pulse of the pulse train.
The control device for a pulse width modulation inverter according to claim 4, wherein the time is the OFF period.