JPH0439018B2 - - Google Patents

Description

[Detailed description of the invention]

[Field of Industrial Application] The present invention relates to a dividing circuit for a measuring device, and in particular,
Suitable for use in measurement devices that electrically measure relative displacement by converting linear displacement or angular displacement into electrical signals using a detector, multi-phase primary signals with different phases are connected to different resistance chains. applying it to a node to generate an out-of-phase secondary signal at another node, and connecting the nodes of the resistive chain with corresponding comparators to compare the primary or secondary signal with a reference level. The present invention relates to an improvement of a dividing circuit for a measuring device that outputs a count signal with a finer pitch than the 1 o'clock signal.

[Conventional technology]

In a wide range of fields such as machine tools, measuring instruments, and portable electronic measuring instruments, for example, a linear displacement measuring machine shown in FIG. 5 uses a two-phase detection signal ( Measuring devices that can digitally measure the amount of relative displacement by outputting a signal (1 o'clock signal) and processing the signal to generate a count signal including forward and backward information and inputting it to the counter 14 are in widespread use. In this measuring device,
Usually, the resolution is coarse at the pitch of the primary signal, so
A dividing circuit 12 is used to obtain subdivided pitch count signals. As the dividing circuit 12, for example, Swiss Patent No.
Divider circuits using resistive chains are well known, as shown in US Pat. No. 4,075,569. In principle, this dividing circuit is approximated by, for example, Asinθ, Acosθ (=Asin(θ+90°)) as the primary signals at the nodes at both ends of the resistance chain 16 consisting of resistors R1 and R2, as shown in FIG. If a signal is applied from the central node,
It takes advantage of the fact that a signal approximated by A'sin (θ+α) is generated. Here, the amplitude A' and phase difference α of the synthesized secondary signal are expressed by the following equations. A′=A√1 ² +2 ² /(R1+R2) ……(1) α=arc tan(R1/R2) ……(2) That is, by selecting the resistance values R1 and R2, the phase difference α
can be set to any value from 0° to 90°, and a signal having any phase between Asinθ and Acosθ can be obtained. Therefore, by outputting a count signal when this signal crosses the zero level, a count signal of finely divided pitches can be obtained. Note that if the detection signal is not a sine wave, any signal can be obtained by changing the resistance value accordingly. FIG. 7 shows an example of a conventional resistance divider circuit that can divide the pitch of the primary signal into 16. In the figure, 20A is a buffer amplifier for the primary signal Asinθ, 20B is a buffer amplifier for the primary signal Acosθ, and 22 is an inverting amplifier for applying the signal -Asinθ, which is the inverted output of the buffer amplifier 20A, to the node of the resistance chain 16. 24A to 24H are a total of eight comparators provided corresponding to each node of the resistance chain 16, 26 is a reference voltage setting device for supplying a reference voltage Vr for comparison to each comparator, and 28A to 28F. is the comparator 2
Exclusive OR to combine outputs from 4A to 24H
Gate 30 is a direction discrimination circuit, and 32 is an oscillator. In this dividing circuit 12, resistors R1, R
The values of 2, R3, and R4 are respectively 1:0.707:
The ratio is set to 0.707:1, and 180° is divided into 8, so 360° is divided into 16. This resistor divider circuit is covered by Swiss patent no.
Since it is disclosed in detail in the specification of No. 407569, detailed explanation will be omitted.

[Problems to be solved by the invention]

However, in the conventional resistance divider circuit shown in FIG. 7, the resistance chain 16, each node, and the comparators 24A to 24H are connected in a 1:1 ratio, so generally when dividing the pitch of the primary signal by 2N, requires N comparators, and the number of comparators increases in proportion to the number of divisions. Therefore, when the entire circuit including the comparator is integrated into an integrated circuit (IC), the characteristics of the comparator, such as the potential difference between the comparison input signal and the reference level when the output of the comparator is inverted, tend to vary, and the response speed deteriorates. Furthermore, it is necessary to add a hysteresis setting resistor to each comparator to prevent oscillation, so even if it is integrated, it will be larger compared to other circuits, so if the number of divisions becomes large, the overall size of the IC will increase. It had the following problems. In addition to IC implementation, circuits in which many comparators are arranged in parallel also have the problem of poor response continuity, such as erroneous counting when the primary signal changes instantaneously.

[Purpose of the invention]

The present invention has been made to solve the above-mentioned conventional problems, and the number of comparators is reduced.
It is suitable for IC implementation and has improved response speed.
Even if the next signal changes instantaneously, it can be followed, and furthermore, 1
It is an object of the present invention to provide a dividing circuit for a measuring device that does not output meaningless counting signals when the phase of the next signal does not change.

[Means to solve the problem]

The present invention applies multi-phase primary signals with mutually different phases to different nodes of a resistance chain to generate phase-shifted secondary signals at other nodes, and connects these nodes of the resistance chain to corresponding comparators. Each node of the resistance chain is connected to a dividing circuit of a measuring device that outputs a count signal that is finer in pitch than the primary signal by comparing the primary signal or secondary signal with a reference level. is connected to at least one of the two comparators via an analog switch to obtain a counting signal synchronized with the clock pulse when the outputs of the two comparators are simultaneously high or low, and The above object is achieved by providing a servo circuit which feeds back the counting signal and sequentially selects two analog switches connected to different adjacent comparators among the analog switches. In another embodiment of the present invention, each node of the resistance chain is connected to two comparators via an analog switch. Furthermore, in another embodiment of the invention, each node of the resistance chain is alternately connected to a different comparator via an analog switch.

[Effect]

In the dividing circuit of the measuring device, the present invention connects each node of the resistance chain to at least one of the two comparators via an analog switch, so that the outputs of the two comparators are simultaneously high or low. level, the servo controller obtains a count signal synchronized with the clock pulse, feeds back the count signal, and sequentially selects two analog switches each connecting adjacent nodes to different comparators. A circuit is installed. Therefore, the number of comparators is reduced, making it suitable for IC implementation. Furthermore, even if the primary signal changes instantaneously, it can be tracked and the response accuracy is improved. Furthermore, no meaningless count signal is output when the phase of the primary signal does not change. Furthermore, if each node of the resistance chain is connected to two comparators via an analog switch, the configuration of the servo circuit is simple. Alternatively, if each node of the resistance chain is alternately connected to different comparators via an analog switch, processing at the time of direction reversal is easy.

【Example】

Embodiments of the present invention will be described in detail below with reference to the drawings. The first embodiment of the present invention has the same 16
The present invention is applied to a dividing circuit, and the first
As shown in the figure, in a dividing circuit 12 having buffer amplifiers 20A and 20B, an inverting amplifier 22, a resistor chain 16, a reference voltage setter 26, and an oscillator 32, the resistor chain 16 is similar to the conventional example.
The nodes a to h are connected to two comparators 42A and 42B via corresponding analog switches 40A to 40P, respectively, and the comparators 42
When the comparison signals J1 and J2 of the outputs of A and 42B are simultaneously at high level or low level, the direction inversion circuit 44, the direction discrimination circuit 46, the AND gate 48A,
48B and latch circuit 48C, count signals (UP count pulse and DOWN count pulse) synchronized with the clock pulse CP output from the oscillator 32 are obtained, and the count signals are fed back to the adjacent analog switches 40A to 40P. Different comparators 42A,
An octal ring counter 50 is provided as a servo circuit for sequentially selecting two analog switches connected to 42B. The detection signal (primary signal) input from the detector may be a signal close to a triangular wave or trapezoidal wave, but for convenience, we will approximate it as a sine wave and explain it assuming a phase difference of 90°. . Therefore, it is considered that a primary signal of Asin θ, Asin (θ+90°)=Acos θ is output from the detector to the dividing circuit 12. Here, θ is the phase corresponding to the displacement. Primary signals Asinθ, Acosθ input from the detector
are inputted via buffer amplifiers 20A and 20B, respectively, and further inputted from Asinθ to an inverting amplifier 22.
The primary signal Asin (θ + 180°) with a phase shift of 180° = -
Asinθ is generated. The resistance chain 16 is composed of eight resistors in total, and primary signals are applied to nodes a, e, and i, respectively. The resistance values of resistors R1, R2, R3, and R4 are set so that the ratio thereof is 1:0.707:0.707:1.
The phase of the secondary signal generated at ~h is from node a to
It is set to gradually shift by 180°/8 = 22.5°. The signals at each node at this time are shown in FIG.
When the primary signal changes as shown in the figure in response to the displacement of the object to be measured, the secondary signal changes accordingly with a phase shift. In this first embodiment, the phase difference
Since 180° is divided into 8 equal parts, as will be explained later,
At 360°, it is divided into 16 equal parts, achieving 16 divisions. Note that if the detection signal is not a sine wave, this can be handled by adjusting the resistance value. The nodes a to h of the resistance chain 16 are connected to eight analog switches 40A and 40C provided correspondingly.
... connected to one input of the first comparator 42A via 40O, and the nodes b to i are connected to eight correspondingly provided analog switches 40B, 40
D...Second comparator 42B via 40P
The comparator 42 is connected to one input of the comparator 42.
A reference voltage Vr, in this case OV, is applied to the other input of A and 42B. As shown in the figure, the analog switches 40A to 40P are connected in pairs to the output of a reversible octal ring counter 50, which is a servo circuit. This ring counter 50 has an UP terminal or
When a counting pulse is input to the DN terminal, the output "1" rotates the output terminal to the right or left. Therefore, the analog switch is always 1.
Only one set of analog switches is selected and in a conductive state, and the other unselected analog switches are in a high input resistance state, ie, a state in which they are considered disconnected. For example, when terminal 1 of ring counter 50 is "1", analog switches 40A and 40B are selected and conductive, and the signal at node a is sent to comparator 42A, and the signal at node b is sent to comparator 42A.
2B, and when both of these signals are greater than the zero level, the comparison signals J1 and J2 both become "1". Output 1 and output 8 of the octal ring counter 50
is also input to the direction inversion circuit 44.
As will be described later, this will change from output 1 to output 8.
or vice versa, comparator 4
This is because since the comparison signals J1 and J2 of 2A and 42B are inverted, the inverted signal K is generated so that the determination of forward movement and backward movement is not inverted even if the comparison signals J1 and J2 are inverted. The direction inversion circuit 44 includes a pulse expander 44 to which the output 1 of the octal ring counter 50 is input.
A, a pulse expander 44B to which output 8 of the 8th ring counter 50 is input, an AND gate 44C that outputs the AND of the pulse expanders 44A and 44B, and 8 based on the output of the AND gate 44C. A T flip-flop 44D generates an inverted signal K whose level is inverted every time the output of the leading ring counter 50 changes from 1 to 8 or vice versa. Therefore, from this direction inversion circuit 44, the output of the octal ring counter 50 varies from 1 to 8.
When switching to or vice versa, an inverted signal K for identifying this is output. The direction discrimination circuit 46 includes the comparator 4
Comparison signals J1 and J2 input from 2A and 42B
and an AND gate 46A that outputs the AND of the inverted signal K inputted from the direction inversion circuit 44, and the negation of the comparison signals J1 and J2 and the inverted signal K.
an AND gate 46B that outputs the logical product of the negation of
An OR gate 46C outputs the logical sum of the AND gates 46A and 46B as an addition signal L1, and an exclusive logical sum of the comparison signals L1 and J2.

[Table] On the other hand, the output from the oscillator 32 is, for example, 500KHz.
Or a 4MHz clock pulse CP is supplied. Therefore, when the clock pulse CP is input when the addition signal L1 is "1", the UP counting pulse is output, and at the same time, the octal ring counter 50 is input to the DN terminal, so the output terminal rotates to the left.
Conversely, when the subtraction signal L2 is "1", DOWN
A counting pulse is output, and the output terminal of the ring counter 50 rotates to the right. This UP counting pulse and
The DOWN counting pulse constitutes the counting signal. Therefore, when a certain set of analog switches is selected and the values of the comparison signals J1 and J2 are different, in a stable state, both the addition signal L1 and the subtraction signal L2 become "0", and meaningless counting pulses are output. There is no. The operation of the first embodiment will be described below with reference to FIGS. 2 and 3. In Figure 2, the primary signal at node a is I → B → A → C →
FIG. 3 shows a time chart of the signals at each part of the dividing circuit 12 when the signal changes from N to E. First, assume that in state A, the terminal 3 of the ring counter 50 is "1" and the inverted signal K is also "1".
At this time, the contact c is connected to the comparator 42A, the node d is connected to the comparator 42B, and the second
From the figure, comparison signals J1 and J2 are respectively "0",
Since it is "1", the addition signal L1 and the subtraction signal L2 are both zero according to the truth table, so no count signal is output. After this, on the way from A to B, comparison signals J1 and J
2 are both "1" and only the addition signal L1 is "1", so when the clock pulse CP is input, the UP counting pulse, which is a counting signal, is output, and the feedback is sent to the DN terminal of the octal ring counter 50, which is a servo circuit. and the output "1" is rotated to terminal 2. Therefore, the nodes b and c of the resistance chain 16
are connected to the comparators 42A and 42B, respectively, and the comparison signals J1 and J2 are "0" and "1", respectively.
Therefore, no counting pulse is output, but when moving to B, an UP counting pulse is output. Next, when changing from B → A → C, both comparison signals J1 and J2 become "0" periodically, so
The subtraction signal L2 becomes “1” and becomes a count signal.
A DOWN counting pulse is output, and the output "1" of the ring counter 50 rotates in the order of terminals 2→3→... Next, the ring counter 50 is set before and after position 2.
When the output of is transferred from terminal 8 to terminal 1, direction inversion circuit 44 is activated, and inversion signal K becomes "0" at point KI in FIG. On the way from position N to position E, both comparison signals J1 and J2 are "1", but since the inverted signal K is "0", the subtraction signal L2 is "1" from the truth table,
DOWN counting pulse is output. At this time, due to the action of the direction reversing circuit 44, the ring counter 5
It can be seen that even if the output of 0 is transferred from terminal 8 to 1, the counting direction is maintained correctly. In this way, a pulse of 8 divisions is obtained at 180°, so 16 divisions are achieved at 360°C. Next, consider a case where the phase of the primary signal instantaneously changes by about 90 degrees. In this case, a counting pulse is output every time the clock pulse CP is input, and the output of the ring counter 50 is rotated until the outputs of the comparators 42A and 42B are inverted, and it is understood that the counting can be followed. Next, as a second embodiment of the present invention, FIG. 4 shows an example of a dividing circuit that outputs a count signal obtained by dividing the pitch of the detection signal (primary signal) into eight. In this second embodiment, in addition to a buffer amplifier 20A similar to the first embodiment and a buffer amplifier 22A that inverts the output, a buffer amplifier 20A is used.
A buffer amplifier 22B is added to invert the output of B, and the primary signals are Asinθ, Acosθ, −Asinθ, −
In addition to the fact that four types of signals Acosθ are applied to the resistance chain 16, Asinθ is applied to two nodes, and the servo circuit includes a 3-bit reversible binary counter 62 and a decoder 64. Furthermore, the output of the decoder 64 is connected to the OR gate 65.
Each analog switch 40A-4 is connected to select two analog switches simultaneously via A-65H.
This embodiment differs from the first embodiment in that it is connected to 0H and that the number of analog switches is halved. In addition, for 8 divisions, you only need to divide 90° into 2, so
The resistance values of the resistance chain 16 are all set to the same value R. Furthermore, the direction reversal circuit of the first embodiment is also omitted. This directly changes the phase of the primary signal from 0° to 360° by 8
Since the signal at each node of the resistance chain 16 is
0°, 45°, ...360° = 0°, so even if the output of the decoder 64 is switched from terminal 8 to terminal 1, the phase does not change, and a phase inversion signal is sent to the direction discrimination circuit 66. This is because there is no need to do so. In the direction discrimination circuit 66, the clock pulse CP is determined by logically ORing the comparison signals J1 and J2 and setting the addition signal L1 or the subtraction signal L2 to ``1'' depending on whether it is ``1'' or ``0''. A counting signal, UP counting pulse or DOWN counting pulse, is obtained at the input of . This counting pulse is part of the servo circuit 3
Feedback is provided to a bit reversible binary counter 62. Similarly to the first embodiment, this second embodiment also has a stable state in which no counting pulse is output when the outputs of the comparison signals J1 and J2 are "0", "1" or a combination of "1" and "0". becomes. In this second embodiment, there is no need to generate a phase inversion signal and a direction inversion circuit can be omitted, so the configuration is simple. In each of the above embodiments, the primary signal was a two-phase signal with a phase difference of 90°.
The number of primary signals and the phase difference are not limited to these, but 2
It is sufficient if it is equal to or higher than the phase. Further, although the number of divisions was 16 in the first embodiment and 8 in the second embodiment, the number of divisions is not limited to these, and may be any number of divisions greater than or equal to 2. Further, in the above embodiments, the primary signal is a sine wave, but the shape of the primary signal is not limited to this, and may be other shapes such as a triangular wave or a trapezoidal wave. Such a difference in shape can be easily accommodated by adjusting the resistance value of the resistance chain.

【Effect of the invention】

As explained above, according to the present invention, each node of the resistance chain is inputted to two comparators via an analog switch, so the number of comparators can be made smaller than the number of nodes of the resistance chain. It is particularly suitable for IC implementation. Further, since the counting signal is fed back by the servo circuit to select the analog switch, even if the primary signal changes instantaneously, it can be followed, and the response speed can be improved. Furthermore, when the phase of the primary signal does not change, there are excellent effects such as no meaningless count signal being output.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of a first embodiment of a dividing circuit of a measuring device according to the present invention, and FIG.
FIG. 3 is a diagram showing an example of the signal waveform at each node of the resistance chain in the embodiment. FIG. 4 is a diagram showing an example of the signal waveform at each part in the first embodiment. FIG. 5 is a block diagram showing an example of the overall structure of a measuring device to which the present invention is applied. FIG. 6 is a circuit diagram showing the principle of a dividing circuit using a resistance chain. , FIG. 7 is a circuit diagram showing an example of a conventional resistance divider circuit. 10...detector, 12...dividing circuit, 14...
Counter, 16...resistance chain, a to i...node,
32...Oscillator, CP...Clock pulse, 40
A~40P...Analog switch, 42A, 42
B... Comparator, J1, J2... Comparison signal,
50...octal ring counter, L1...addition signal, L2...subtraction signal, 62...binary counter,
64...decoder.

Claims (1)

[Claims] 1. Multi-phase primary signals with different phases are applied to different nodes of a resistance chain to generate phase-shifted secondary signals at other nodes, and the nodes of the resistance chain are In the dividing circuit of the measuring device, the resistance chain is connected to a corresponding comparator and outputs a counting signal that is finer in pitch than the primary signal by comparing the primary signal or the secondary signal with a reference level. each node is connected to at least one of two comparators via an analog switch, and when the outputs of the two comparators are simultaneously high or low, the count signal is synchronized with the clock pulse. and a servo circuit that feeds back the count signal and sequentially selects two analog switches each connecting adjacent nodes to different comparators from among the analog switches. split circuit. 2. A dividing circuit for a measuring device according to claim 1, wherein each node of the resistance chain is connected to two comparators via an analog switch. 3. A dividing circuit for a measuring device according to claim 1, wherein each node of the resistance chain is alternately connected to a different comparator via an analog switch.