JPH0439697B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION A. OBJECTS OF THE INVENTION [Field of Industrial Application] The present invention relates to a debugging device for a microprocessor for increasing the reliability of a program, and to improving its functions.

[Conventional technology]

Traditionally, when debugging a program,
Generally, a method (functional test) is adopted in which program test data is prepared and the contents of the input and output are compared and verified. However, in this case, even if there are paths that are not executed due to the structure of the program, they are often overlooked, which causes program errors and does not improve reliability.

As a method to solve this problem, at the same time as the above functional test, we measure all the execution paths existing on the program and the non-execution paths that are actually not executed when the program is running, and measure all the execution paths of the program. The percentage of routes that are actually executed has come to be used as a measure of a program's reliability. This is called test coverage.

A common way to measure test coverage is to divide a program into segments (a block of programs with no internal branches) and see what percentage of all segments are executed.

[Problem that the invention seeks to solve]

However, the conventional microprocessor analyzer as described above has the following problems.

FIG. 2 is a diagram showing the flow of a conditional branch instruction. Let C be the address where the conditional branch instruction is stored, B be the destination address when this condition is YES (when the condition is true), and A be the destination address when this condition is NO (when the condition is not true). and,
When processing A is performed, address B is reached.

Conventionally, when measuring the coverage of such a program, the branch address B of the conditional branch instruction is
Then, the execution address A when the condition is not satisfied is extracted, and a bit in the coverage memory corresponding to this address is set (eg, "1"). Then, in real time when the target processor is running,
The bit in the coverage memory corresponding to the executed address is cleared (for example, to "0").

In this way, the conventional method of measuring coverage is that, as shown in Figure 2, the branch address B of the conditional instruction is directly connected to the execution PASS A when the condition is not met.
There is a problem that it is not possible to check whether or not PASS B in Figure 2 has passed when the pass is within the range. To explain this in an easy-to-understand manner, if the condition is not satisfied (NO) in a conditional branch instruction, the process goes to address A (therefore, address A in the coverage memory is cleared), and then the process A is performed, and then the process goes to address B. (address B of coverage memory is also cleared). However, in this case, address B is also cleared even though PASS B has not passed, and as a result, a problem arises in that it is impossible to check whether or not PASS B has passed.

To solve the above problem, first, address C where the branch instruction is located, address B when the condition is met, and address A when the condition is not met are extracted, and only these addresses are stored in the trace memory when the target processor is executed. Then, after storing the above address in the entire trace memory, there is a method of breaking the target processor, stopping execution, sequentially analyzing the contents of the trace memory, and measuring coverage. However, this method has a problem in that some target processors cannot operate in real time.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to provide a debugging device for a microprocessor that can accurately measure test coverage in real time.

B "Structure of the Invention" [Means for Solving the Problems] In order to solve the above problems, the present invention provides a first memory that stores a predetermined signal "1" at an address where a conditional branch instruction is located. a second memory means that stores a predetermined signal "1" at an address when the condition is met and an address when the condition is not met; and a third memory means that stores the same content as the second memory means.
and circuit means for applying a write signal ( ) to the third memory means only at the next execution address of the conditional branch instruction, thereby making it possible to measure coverage in real time. This is how it was done.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.
FIG. 1 is a diagram illustrating a main part of a debugging device for a microprocessor according to an embodiment of the present invention. In the figure, 1 is a microprocessor to be debugged (hereinafter referred to as target CPU).
This target CPU 1 is connected to a target microprocessor application device (hereinafter referred to as a target system) via, for example, a probe (usually called a POD). And target CPU1
is the same microprocessor as the microprocessor built into the target system, and during testing, the microprocessor is removed from the target system (a socket is used and is removable), and the POD is inserted into the socket. The microprocessor (target CPU 1) on the POD operates the target system on its behalf. Reference numeral 2 denotes a coverage memory whose data is 1 bit wide, and the address of this memory is given via an address bus 3. To this address bus 3, an address from the target CPU 1 outputted to the address bus 5 is given via a 3-state buffer 4, or an address from the CPU 8 of the debug device outputted to the address bus 7 is given. 3-state
It is provided via buffer 6. Which address is given is determined by selectively controlling buffer 4 or 6 by CPU 8.

Further, the coverage memory 2 receives either logical "0" data provided via the 3-state buffer 9 or data from the CPU 8 provided via the bidirectional 3-state buffer 10. is input selectively.

The write command signal () to the coverage memory 2 is sent to the Q output of the JK flip-flop 15 and the target CPU 1 gated by the gate 14.
The CPU 8 is supplied with an instruction execution signal (OPC) from the CPU 8 or via a 3-state buffer 12.
Either the write signal (WR1) from The CPU 8 is capable of controlling the buffer 12 and the JK flip-flop 15 to provide either one of the write signals to the coverage memory 2.

Reference numeral 13 is a gate memory in which data is 2-bit wide. Its outputs D ₀ and D ₁ are connected to J and K of the JK flip-flop 15. In addition,
In the above description, the gate memory 13 and the coverage memory 2 are each physically divided into two memories, but one memory may be shared and the bit contents may be divided and used. . That is, a memory whose data is at least 3 bits wide is used, and 2 bits are stored in the gate memory 13.
The remaining 1 bit is used as coverage memory 2.

The operation in such a configuration will be explained next.

FIG. 3 is a diagram showing the contents between the gate memory 13 and the coverage memory 2 and their peripheral circuits to facilitate understanding of the operation of the device according to the present invention. However, since the buffer 11 does not affect the explanation of the operation, its illustration is omitted. FIG. 4 is a time chart, and the terminal names of each part in FIG. 3 corresponding to the waveforms are attached to the left side of each waveform.

(1) Gate memory 13 and coverage memory 2
The data in the gate memory 13 is 2-bit wide, and the stored contents are as shown in Figure 3.
Divide into A and B. That is, A and B are each 1 bit.

First, the gate memory 13 contains a large number of conditional branch instructions (P ₁ , P ₄ ,...) and addresses (P ₂ , P ₃ ,
P ₅ , P ₆ , ...) are set, and a predetermined signal "1" is applied to all addresses (P ₁ , P ₄ , ...) containing conditional branch instruction codes in the A part of the gate memory 13. The other parts of A that are not conditional branch instructions are set to "0".

B of the gate memory 13 contains addresses (P ₃ , P ₆ ,...) when all conditional branch instructions are established,
and set a predetermined signal “1” to the execution address (P ₂ , P ₅ , ...) when all conditions are not satisfied,
The other parts of B are set to "0". The number set to "1" in the B section of the gate memory 13 becomes the total number of segments.

The same contents as part B of the gate memory 13 are set in the coverage memory 2.

(2) Operation Target CPU 1 starts executing the program and issues a conditional branch instruction (for example, the address in Figure 3).
Suppose that P ₁ ) is executed. Therefore, the output _D0 of A of the gate memory 13 becomes 1, and the output Q of the JK flip-flop 15 becomes "1" due to the OPC.

Here, if the condition is not satisfied and the instruction at address _{P2 shown} in FIG. “0”
becomes.

The write signal of coverage memory 2 is
As can be seen from the time chart shown in the figure, the gate 14 outputs an output only when the output Q of the JK flip-flop 15 is "1". Therefore, in this case, "1" in the coverage memory 2 is changed to "0" only at address _P2 . This means that the segment at address _P2 has been executed.

Address _P3 may be executed even when the condition is not met, but if the output Q of the JK flip-flop 15 is not "1" as described above, the contents of the coverage memory 2 will change from "1" to "0". do not.

In this manner, after the test of the target program is completed, the contents of the coverage memory 2 are checked, and if there is still a "1", it is determined that it is an unhitched segment. It is also possible to measure the coverage rate for all segments.

In addition, in FIGS. 1 and 3, a conditional branch instruction is executed and the address of the condition is met or not met so that the coverage of a program written in a high-level language (for example, 16 bits) can be measured. The execution is
The configuration is such that the execution cycle does not have to be immediately following the conditional branch instruction.

In addition, gate memory 13 and coverage memory 2
Although the predetermined signal to be written to is "1" in the above description, it is not limited to "1" and may be a signal with another meaning.

FIG. 5 is a diagram showing another embodiment of the present invention, and the application is limited to assembler language.
The configuration is simplified compared to the devices shown in FIGS. 1 and 3. That is, in this case, immediately after the conditional branch instruction there is an execution cycle in which the condition is met or not met, so part B of the gate memory 13 as shown in FIG. 5 becomes unnecessary. Also, JK flip-flop 15 replaces D flip-flop,
Configuration becomes easier. The operation is such that data is stored in coverage memory 2 only in the next execution cycle of the conditional branch instruction.
The only difference is that the WE signal is output, and the rest is as described above.

Also, in the explanation so far, conditional branch instructions are
Although only two branches, taken or not taken, have been described, the present invention can also be applied to conditional instructions with multiple branches.

C. "Effects of the Present Invention" According to the present invention, accurate coverage can be measured in real time with a relatively simple configuration, resulting in great practical effects.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of a microprocessor debugging device according to the present invention, FIG. 2 is a diagram showing a flow including a conditional branch instruction, and FIG. 3 is a diagram showing the operation of the device shown in FIG. For easy understanding, the contents between the gate memory 13 and the coverage memory 2 and their peripheral circuits are shown, FIG. 4 is a time chart of the device shown in FIG. 1, and FIG. 5 is a debugging device for a microprocessor according to the present invention. It is a figure showing another example of composition. 1...Target CPU, 2...Coverage memory,
3...Bus, 13...Gate memory, 15...JK flip-flop.

Claims (1)

[Scope of Claims] 1. In a device equipped with a target CPU of a target system and for debugging a program executed by the target CPU, a first memory means A stores a predetermined signal at an address where a conditional branch instruction is located. and a second memory means B that stores a predetermined signal at an address when the condition is met and an address when the condition is not met.
and a third memory means 2 that stores the same contents as the second memory means B; and applying a write signal ( ) to the third memory means 2 only at the next execution address of the conditional branch instruction. A debugging device for a microprocessor, characterized in that it is equipped with circuit means for performing the following steps. 2. The microprocessor according to claim 1, wherein one memory is shared among the first, second, and third memory means, and the bit contents of this memory are divided and used. debugging equipment for 3. Delete the second memory means B, and delete the third memory means B.
2. A debugging device for a microprocessor according to claim 1, wherein the memory means 2 stores a predetermined signal at an address when the condition is met and an address when the condition is not met.