JPH0439773B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field] This invention relates to a shot gate type FET.
(MESFET) manufacturing technology, particularly technology that is effective for manufacturing gallium arsenide MESFETs with self-alignment structure.

[Background technology]

Gallium arsenide (GaAs) is said to be the next generation semiconductor material to replace silicon. This is because GaAs has material advantages such as higher electron mobility than silicon, and GaAs itself is semi-insulating, making isolation between elements easy.

In integrated circuits using GaAs as a substrate,
MESFET structures are mainly used. fast
When trying to obtain a MESFET, parasitic series resistance between the gate and source and between the gate and drain becomes a problem.

In order to reduce this parasitic series resistance and increase the speed of the FET, it is effective to form the gate, source, and drain in a self-aligned manner (for example, "Nikkei Electronics", November 1982). 8
(See Japanese issue, p105-127, especially p120-122).

[Object of the Invention] An object of the present invention is to provide a self-alignment technique that can form self-alignment between the gate, source, and drain of a MESFET.

Another object of the present invention is to form a low concentration region and a high concentration region in a semiconductor layer formed on one surface of an insulating substrate by utilizing the difference in implantation depth due to ion implantation. The goal is to provide technology.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in a typical example of the present invention, wiring is formed by lift-off processing, and the lift-off material layer for this is also used as a mask for ion implantation, and the GaAs formed on one surface of the insulating substrate is used as a mask for ion implantation.
Highly doped regions serving as a source and drain and a lightly doped region under the gate are formed in the semiconductor layer. Thereby, the purpose of forming the gate, source, and drain in a self-aligned manner is achieved.

〔Example〕

Hereinafter, the content of the present invention will be specifically explained based on the embodiments shown in FIGS. 1 to 5.

(Refer to Figure 1) First, on one side of the insulating substrate 1 such as sapphire.
Forming a semiconductor layer 2 made of a GaAs single crystal thin film,
A lift-off material layer 3 consisting of a silicon dioxide film 31 and a silicon nitride film 32 is entirely deposited thereon. The main body of the lift-off material layer 3 is the lower silicon dioxide film 31;
The thickness is considerably thicker than required for lift-off. However, the lift-off material layer 3 also needs to have a thickness that allows ions to be implanted into the underlying semiconductor layer 2 through it, and its thickness is determined by the balance between these two factors.

(See FIG. 2) Next, the portion of the lift-off material layer 3 where the gate is to be formed is selectively removed by normal photoetching. In this case, by side-etching the lower film 31 using the upper film 32 as a mask, the canopy structure 4 is formed at the etched end. This canopy structure 4 has the desirable function of facilitating the subsequent lift-off and reliably preventing electrical shorts between the gate and the source and drain.

(See FIG. 3) After the formation of the partial lift-off material layer, an N-type impurity, such as silicon, is entirely introduced into the semiconductor layer 2 on the substrate 1 by ion implantation. At this time, mainly by controlling the implantation energy, the implanted ions are made to reach the insulating substrate 1, which is mostly ungrounded in the gate region, and to enter the semiconductor layer 2 in other locations other than the gate. Do it like this. Therefore, by such ion implantation and subsequent annealing treatment,
The portion 21 of the semiconductor layer 2 under the lift-off material layer 3 is
The N ⁺ type high concentration region and the exposed portion 22 where a gate is to be formed can be respectively formed as an N ⁻ type low concentration region.

(Refer to FIG. 4) Next, when a gate metal material (for example, platinum or platinum silicide) is deposited by a highly directional deposition method such as sputtering, the eaves structure 4 Metal material 5
is formed with step breaks. Therefore, by etching the lift-off material layer 3, the portion of the gate metal material 5 that was attached to the layer 3 is removed together with the layer 3 (lift-off).
However, the gate metal material 5 can be left only on the N ^- type region 22. This partial portion becomes the gate metal film 51.

(Refer to FIG. 5) Then, after selectively removing the N ⁺ type region 21 outside the element by photoetching, a passivation film 6 made of silicon dioxide or the like is formed on the entire surface by CVD. . After making a connection hole 7 in the film 6, a source electrode 8 is formed using known vacuum deposition and photoetching techniques.
1. Drain electrode 82 and gate extraction electrode (not shown), and wiring between elements (not shown)
to complete the GaAs MESFET.

〔effect〕

Since the gate, source, and drain of the MESFET are self-aligned, the parasitic series resistance can be reduced and the device speed can be increased. In particular, since the lift-off material layer for forming interconnections is also used as a mask for ion implantation, the process is relatively simple.

Although the invention made by this inventor has been specifically explained above based on examples, it goes without saying that this invention is not limited thereto and can be modified in various ways without departing from the gist thereof. do not have. For example, tungsten, tungsten silicide, or the like may be used as the gate material. Furthermore, the N-type impurity to be ion-implanted may be other than silicon.

[Application field]

This invention is not limited to GaAs devices.
It can be widely used as a MESFET self-alignment technology. Furthermore, this invention
Application to MOSFET is also possible.

[Brief explanation of drawings]

1 to 5 are cross-sectional views showing an embodiment of the present invention in the order of steps. DESCRIPTION OF SYMBOLS 1... Insulating substrate, 2... Semiconductor layer, 3... Lift-off material layer, 4... Eaves structure, 5... Metal material for gate, 51... Gate metal film, 6... Passivation film, 7... Hole, 81... Source electrode, 82... drain electrode.

Claims (1)

[Claims] 1. A shot gate type consisting of the following steps:
FET manufacturing method. (A) A process in which the surface of a semiconductor layer formed on one side of an insulating substrate is covered with a lift-off material layer except for the area where a gate is to be formed. (B) By utilizing the difference in implantation depth due to ion implantation, the portion of the semiconductor layer under the lift-off material layer is made into a high concentration region, and the portion of the semiconductor layer where the gate is to be formed is made into a low concentration region. Each process. (C) After the step (B), a step of leaving the gate metal material only in the low concentration region by depositing the gate metal material and performing a lift-off process using the lift-off material layer. (D) A step of forming electrodes and wiring by using the gate metal material partially left in the step (C) as a gate metal film, and using each portion of the high concentration region located on both sides of the gate metal film as a source and a drain. 2. The method of manufacturing a shot gate type FET according to claim 1, wherein the lift-off material layer is composed of an upper and lower two-layer film, and the upper film can serve as a mask for side etching of the lower layer.