JPH0440799B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure for electrically detecting whether redundancy technology is applied in a semiconductor memory integrated circuit device to which redundancy technology is applied.

In semiconductor memory integrated circuit devices, as chips have become larger in recent years, the yield per wafer has decreased, and on the other hand, as component elements have become smaller, cell defects have occurred due to the effects of microscopic foreign particles and crystal defects, resulting in lower product yields. There is a tendency for it to decline further. Therefore, a redundancy technology is available in which spare memory cells and lines are placed in the same chip as the semiconductor memory integrated circuit device, and defective memory cells or lines are replaced with these, and the chip is used as a non-defective chip. Used in memory integrated circuit devices.

In conventional redundancy technology for semiconductor memory integrated circuit devices, spare memory cells, word lines, bit lines, or both are provided on the same chip as the semiconductor memory integrated circuit device.
If a defective cell or defective line is found on this chip, the defective portion is replaced with a spare cell or line to maintain the same address correspondence. In the conventional redundancy technology, there is no means for electrically determining whether the redundancy technology has been applied to a chip of a semiconductor memory integrated circuit device, and product selection cannot be performed in the manufacturing process. Furthermore, after the chip is sealed in a package, even if a defect occurs, it is not possible to analyze the defect because it is not known whether redundant technology has been applied or not.

In the present invention, in order to eliminate these drawbacks and to know whether redundancy technology is applied, a program storage element or a circuit including this program storage element is installed on the same chip as the semiconductor memory integrated circuit device to store application of the redundancy technology. The present invention is characterized in that it is provided with a detection section consisting of the following.

A basic reference example of the present invention will be explained with reference to FIG. A detection section 3 consisting of a program storage element for storing application of redundancy technology or a circuit including this program storage element, and measurement terminals 1 and 2 electrically connected to this detection section 3,
It is provided on the same chip as the semiconductor memory integrated circuit device. A redundancy technique is applied to this chip and at the same time it is stored in the program storage element of the detection section 3. For example, in a semiconductor memory integrated circuit device,
When the redundancy technology is applied and this application is memorized, a predetermined current flows between terminals 1 and 2, and when the redundancy technology is not applied and the application is not stored in the program storage element, a predetermined current flows between terminals 1 and 2. The configuration is such that no current flows through the Alternatively, the opposite method may be used. By comparing the current between terminal 1 and terminal 2 with respect to the memory of the programming storage element,
A distinction is made between whether or not redundant technology is applied.

Program memory elements that store whether or not redundancy technology is applied include elements that electrically fuse polysilicon wiring, elements that cut aluminum or polysilicon wiring by laser beam irradiation, and more recently, n ⁺ layer-i There are devices that lower the resistance of layer-n ⁺ layer type high-resistance polysilicon by irradiating it with laser light.

FIG. 2 is a diagram showing a first reference example of the present invention, in which the program storage element used in the detection unit 101 electrically connected to the measurement terminals 1 and 2 is made of electrically disconnectable material such as polysilicon. A conductive material is used. These terminals 1 and 2 and the detection unit 101
is provided on the same chip as the semiconductor memory integrated circuit device. When applying a redundancy technique based on the test results of a semiconductor memory integrated circuit device, the redundancy technique is applied by applying a voltage between terminals 1 and 2 and flowing a current to cut the polysilicon wiring of the detection unit 101. Remember the application. In order to determine whether or not the redundancy technique is applied, a voltage is applied to the terminals 1 and 2 by placing needles on them. As a result, if no current flows between terminals 1 and 2, this indicates that the program storage element of the detection unit 101 is disconnected.
It can be determined that this is a semiconductor memory integrated circuit device to which redundancy technology is applied.

FIG. 3 is a diagram showing a second reference example of the present invention. The program storage element of the detection unit 102 is made of a conductive material such as polysilicon or aluminum, and is electrically connected to the measurement terminals 1 and 2. These terminals 1 and 2 and the detection section 102 are provided on the same chip as the semiconductor memory integrated circuit device. When redundancy technology is applied to a semiconductor memory integrated circuit device, the detection unit 102
A laser beam 10 is emitted from the top of the program memory element of
3 is irradiated to cut the polysilicon or aluminum of the program storage element to store the application of the redundancy technology. In order to detect whether or not redundancy technology is applied to this semiconductor memory integrated circuit device, a voltage is applied to terminal 1 and terminal 2 of this embodiment. As a result, if no current flows between the terminals,
Since the program memory element is disconnected, it can be determined that this is a semiconductor memory integrated circuit device to which redundancy technology is applied.

FIG. 4 is a diagram showing a third reference example of the present invention. The detection unit 110 in FIG. 4 is a memory element for programming using high-resistance polysilicon of n ⁺ layer-i layer-n ⁺ layer type in which polysilicon 104 containing impurities is arranged on both sides of pure polysilicon 105 containing no impurities. and is connected to terminal 1 and terminal 2. This high-resistance polysilicon usually exhibits a high resistance value of 10 ⁹ Ω or more, but if the laser beam 103 is irradiated so as to cover part of the pure polysilicon 105 and polysilicon 104 containing impurities, it will cause a high degree of harm. Resistor polysilicon has a characteristic that the resistance value changes to a low resistance value of about 10 ³ to ^{10 5} Ω. Therefore, by providing the detection unit 110 using this high-resistance polysilicon as a program storage element and the terminals 1 and 2 connected thereto on the same chip as the semiconductor memory integrated circuit device, it is possible to determine whether or not redundancy technology is applied. be able to. Only when redundancy technology is applied to the semiconductor memory integrated circuit device, the detection unit 11
Laser light 103 is irradiated onto the high resistance silicon of 0 to change it to a low resistance value. In order to know whether redundancy technology is applied or not, a voltage is applied between the terminals 1 and 2. As a result, when redundancy technology is applied, the resistance of the high-resistance polysilicon is reduced, so the current between terminals 1 and 2 flows several orders of magnitude more than when redundancy technology is not applied. By comparing the current values flowing between the terminals, it can be determined whether the redundancy technique is applied to the semiconductor memory integrated circuit device.

Furthermore, due to manufacturing variations in the program memory element and fluctuations in laser energy during storage, it is difficult to control the resistance value of the program memory element after the application of redundancy technology has been memorized.
It is also possible that the resistance value becomes 10 ⁶ Ω or more.
In this case, the current flowing through the programming memory element is
It is difficult to measure as it is less than 1μA.

The fourth reference example of the present invention is an example applied to a case where the resistance value after memorizing the application of the redundant technology is 10 ⁶ Ω or more as described above, and FIG. 5 is a diagram of the reference example. It is. The detection section 3 having a measurement terminal 1 and a terminal 2 is constructed by connecting an n-channel MOS transistor 201, a program storage element 206, and a resistor 207 as shown. The program memory element 206 is, for example, n ⁺ layer - i layer - n ⁺
Using layered high-resistance polysilicon, the resistance values of the program memory element 206 and the resistor 207 are respectively
Try to maintain a ratio of about 10:1, about 10 ⁹ Ω and 10 ⁸ Ω. The detection unit 3 configured in this way is connected to the terminal 1.
and 2 are provided on the same chip as the semiconductor memory integrated circuit device. Terminal 2 on the chip
If the potential of terminal 1 is set to a high potential and the potential of terminal 1 is set to a low potential, the n-channel MOS transistor 201 will be in a cut-off state depending on the resistance ratio of the program storage element 206 and the resistor 207 before the redundancy technology application is memorized, and the terminal 1 and No current flows between terminals 2. Only when the redundancy technique is applied, the program memory element 206 is irradiated with laser light, and the resistance value of the program memory element 206 is changed to be about one digit lower than the resistance value of the resistor 207. In other words, the resistance value of the program storage element in which the application of the redundancy technique is stored may be 10 ⁷ Ω or less, which is about two orders of magnitude lower than the resistance value before the application is stored.

When detecting whether redundancy technology is applied in this semiconductor memory integrated circuit device, terminal 2 is set to a high potential, terminal 1 is set to a low potential, and the current between both terminals is measured. In the state where the application of the redundancy technique is memorized as described above, the n-channel MOS transistor 201
Since the gate potential of is biased to the high potential of terminal 2, a current flows between terminals 1 and 2 depending on the size of this MOS transistor. Therefore, even if there are manufacturing variations in the program memory element or variations in laser energy, a large current flows through the detection unit 3 of this embodiment, making it easy to measure, and this is useful as a redundancy technique in semiconductor memory integrated circuit devices. It is easy to distinguish whether it is applicable or not.

The detection devices shown in the first to fifth reference examples described above are embodiments used for semiconductor memory integrated circuit devices in a wafer state or for chips before being packaged. In a semiconductor memory integrated circuit device after being sealed in a package, external lead pins serve as electrical connections, but when each terminal in the above embodiment is connected to these external lead pins, a large current flows between the pins under normal usage conditions. Since the function of the lead pins in the integrated circuit device is impaired, it is not practically appropriate to use the detection device of the above embodiment to determine whether redundancy technology is applied to the semiconductor memory integrated circuit device after being sealed in a package.

Next, FIG. 6 shows an embodiment for detecting whether redundancy technology is applied in a semiconductor memory integrated circuit device after being sealed in a package. The detection unit 3 that detects whether redundancy technology is applied is configured as shown in the figure by a program storage element 206, a resistor 207, and n-channel MOS transistors 201 to 205, and is provided with terminals 1, 2, and 4. That is, in the detection unit 3 of this embodiment, the switching 7
Four n-channel MOS transistors, each with its source and gate short-circuited, are connected in series as a load to the source of a channel-type MOS transistor, and the voltage applied to both ends of this circuit is adjusted according to the resistance value of the programming memory element and the resistor. The voltage is divided and applied to the gate of the switching n-channel MOS transistor. Note that the substrate of each transistor is connected to the terminal 4. The program memory element 206 in the detection unit 3 described above is made of, for example, n ⁺ layer-i layer-n ⁺ layered high-resistance polysilicon, and the resistance value of the program memory element 206 is
10 ⁹ Ω, and the resistance value of resistor 207 is approximately 10 ⁸ Ω.
Keep the ratio around 10:1. The detection unit 3 having such a configuration, the terminals 1, 2, and the terminal 4 are provided on the same chip as the semiconductor memory integrated circuit device, and in this embodiment, the terminal 1 is connected to the power supply pin of the semiconductor memory integrated circuit device, and the terminal 4 is It is connected to a ground pin, and terminal 2 is connected to another clock pin or a blank pin, for example.

In normal operation of the semiconductor memory integrated circuit device, a power supply voltage is applied to the terminal 1 and the potential of the terminal 2 is lower than the power supply voltage, so that no current flows between the terminals 1 and 2. Also, even if a voltage of opposite polarity is applied by mistake, the potential at terminal 2 will exceed the sum of the threshold voltages of these transistors because the n-channel MOS transistors 202, 203, 204, and 205 are connected in series. Otherwise, no current will flow between terminals 1 and 2. Therefore, under normal usage conditions, the detection section 3 has no effect on the semiconductor memory integrated circuit device.

When redundancy technology is applied to this semiconductor memory integrated circuit device, the program storage element 206 in the detection unit 3 is irradiated with ^laser light to
The resistance value of layer −n ⁺ layered high resistance polysilicon is 10 ⁷ Ω.
Lower the resistance below.

In this way, when detecting whether or not redundancy technology is applied to a semiconductor memory integrated circuit device sealed in a package, unlike normal usage, terminal 2, which is the power supply bias pin, is grounded and to potential. When the redundancy technology is not applied, the programming memory element 206 is not irradiated with laser light, so the resistance value of the programming memory element 206 is higher than the resistance value of the resistor 207, and a high voltage is applied to the gate of the n-channel MOS transistor 201. Since no current is applied, no current flows between terminals 1 and 2. On the other hand, if redundancy technology is applied to the chip of this semiconductor memory integrated circuit device, the resistance value of the program storage element 206 is lower than the resistance value of the resistor 207, and the high potential of the terminal 2 is applied to the gate of the MOS transistor 201. Therefore, current flows between terminal 1 and terminal 2. Therefore, it is possible to easily determine whether redundancy technology is applied to the semiconductor memory integrated circuit device. When detecting whether redundancy technology is applied, the MOS transistor 20 is grounded by grounding terminal 1 and applying a high voltage to terminal 2.
The drains and sources of 1, 202, ... 205 act as sources and drains, so
MOS transistors 202...205 have gates and
Operates as a drain shorted MOS diode,
Current can flow from terminal 2 to terminal 1. On the other hand, in normal operation, the power supply voltage is applied to terminal 1 and a low voltage is applied to terminal 2, so the MOS transistors 201, 202...20
The respective drains and sources of 5 function as drains and sources as normal, so MOS transistors 202...205 with gate-source short circuits are used.
No current flows through these MOS transistors 201, 202, . The above example shows an example in which terminal 1 is grounded, but even if terminal 1 is kept at the potential of the power supply voltage, if terminal 2 is set to a high potential higher than the potential of the power supply voltage, the redundancy technique described above can be applied. Needless to say, it is possible to determine the

In this example, the n ⁺ layer −i used in the third reference example
Layer-n ⁺ layered high-resistance polysilicon is used as the program memory element, but even if this is replaced with the program memory element used in the first and second reference examples, the redundancy technology of the present invention will still work. A configuration for detecting the presence or absence of application can be easily realized.

Note that the n-channel type MOS transistors 202 to 205 connected in series in this embodiment are not limited to four stages, and the number of stages can be increased or decreased.
Furthermore, a p-channel transistor can be applied by reversing all the potential relationships in the embodiment.

Furthermore, although this embodiment shows a state in which the terminals of the detection unit are connected to the external lead pins of the semiconductor memory integrated circuit device, the detection unit and each terminal shown in this embodiment are provided on the same chip as the semiconductor memory integrated circuit device. Needless to say, it is possible to detect whether or not redundant technology is being applied by raising the measuring needle in this state.

Furthermore, by inserting a resistor at a suitable location between terminal 1 and terminal 2, it is also possible to reduce the power consumption of the detection part.

Since the present invention is configured as described above, it is possible to electrically easily detect whether or not redundancy technology is applied in a chip of a semiconductor memory integrated circuit device, and it is possible to select products during the manufacturing process. be. It is also used as a memory confirmation means to determine whether or not the memory indicating the application of redundancy technology to the program memory element has been accurately recorded.

Furthermore, a MOS transistor with its source and gate shorted is connected as a load to the source of the switching MOS transistor, and the voltage applied across this circuit is divided according to the resistance value of the programming memory element and the resistor, and the voltage is applied to the gate of the transistor. In a semiconductor memory integrated circuit device that has a detection section with an additional configuration and each terminal of the detection section is connected to an external lead pin, it is possible to electrically detect whether redundancy technology is applied from the outside even after the package is sealed. Therefore, it is possible to perform defect analysis even when a product defect occurs.

[Brief explanation of the drawing]

Figure 1 is a diagram showing a basic reference example of the present invention, Figure 2 is a diagram showing a basic reference example of the present invention.
3, 4, and 5 each show a reference example of the present invention, and FIG. 6 shows an embodiment of the present invention. 1, 2... terminal, 3, 101, 102, 110
...Detection unit, 103...Laser light irradiation state, 20
1 to 205...n-channel MOS transistor, 206...program memory element, 207...
…resistance.

Claims (1)

[Scope of Claims] 1. Redundancy technology can be applied to replace defective memory cells or defective lines with spare memory cells or lines arranged in advance on a chip, thereby making the chip a good product. A semiconductor memory integrated circuit device equipped with a program storage element for storing whether or not redundancy technology is applied, comprising a first terminal and a second terminal, and a drain of a switching MOS transistor connected to the first terminal. one or more connected with the gate and source shorted.
For said switching via MOS transistor
A source of the MOS transistor is connected to the second terminal, the program element and the resistor are connected in series between the first terminal and the second terminal, and the program element and the resistor are connected in common. By connecting a point to the gate of the switching MOS transistor, the potential of the common connection point is supplied to the gate, and the program element is programmed in advance, thereby applying the redundancy technique of the semiconductor memory integrated circuit device. When detecting the presence or absence of the switching MOS transistor, the potential of the common connection point is
A semiconductor characterized in that a state is such that a current flows or does not flow between the first terminal and the second terminal via drain-source paths of at least one MOS transistor. Memory integrated circuit device. 2. During normal operation of the semiconductor memory integrated circuit device, the first terminal and the second terminal are connected via source-drain paths of the switching MOS transistor and the one or more MOS transistors.
The potentials of the first terminal and the second terminal are set to a potential such that no current flows between the first terminal and the second terminal,
When detecting whether or not the redundancy technology is applied to the semiconductor memory integrated circuit device, the connection between the first terminal and the first The semiconductor memory integrated circuit according to claim 1, wherein the potentials of the first terminal and the second terminal are set to a potential such that a current can flow between the semiconductor memory integrated circuit and the second terminal. Device. 3. The one or more semiconductor memory integrated circuit devices whose gates and sources are short-circuited according to the potentials of the first terminal and the second terminal that are set when detecting whether or not the redundancy technology is applied to the semiconductor memory integrated circuit device. 3. The semiconductor memory integrated circuit device according to claim 2, wherein the MOS transistor operates as one or more MOS transistors whose gates and drains are short-circuited.