JPH0440888B2 - - Google Patents

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to hysteresis circuits.

[Prior art]

BACKGROUND ART In electronic circuits, especially integrated circuit devices, as constituent elements become smaller and lower voltages, noise resistance becomes weaker and the risk of malfunction due to noise increases. For this reason, various hysteresis circuits are used to prevent malfunctions.

Figure 1 shows an N-channel silicon gate MOS field effect transistor (hereinafter referred to as FET).
1 is a circuit diagram showing an example of a conventional hysteresis circuit using a hysteresis circuit.

In FIG. 1, FET 11 is a depletion type with its gate and source connected, its drain connected to a power supply (voltage V _D ) 18, and FETs 12, 13
have their gates connected in common to form an input terminal 19;
The source of FET11 and the drain of FET12 are connected to form a node 15, and the source of FET12 is
It is connected to the drain of FET 13 to form node 16, the source of FET 13 is connected to ground point 17 which is a reference potential, and the gate of FET 14 is connected to node 1.
5, the source is at node 16, and the drain is at power supply 18.
, and an output end 20 is taken out from the node 15. Note that FET12, 13,
14 is an enhancement type.

The operation of this circuit will be explained below with reference to the input/output characteristic diagram shown in FIG.

First, a case where the input voltage V _IN of the FETs 12 and 13 changes from a low level to a high level will be described. When V _IN is less than or equal to the threshold voltage V _T of the FET 13, the potential V ₁₅ at the node 15 is the working voltage V _D at a high level. Also, the potential V ₁₆ at node 16 is V _D −
It becomes V _T. At this time, FET12 and 13 are non-conductive,
The FET 14 is in a conductive state (but in a pinch-off state). When the input voltage V _IN reaches the threshold voltage V _T , FET 13 starts conducting, and the potential V ₁₆ becomes FET 1
It decreases according to the on-resistance ratio of 3 and 14. However, until the input potential V _IN reaches V ₁₆ +V _T , the FET
12 is non-conductive, the potential V ₁₅ is kept at V _D. When the input voltage V _IN increases and reaches V _IN =V ₁₆ +V _T , the FET 12 begins to conduct and the potential V ₁₅ begins to decrease. At this stage, the on-resistance of FET 14 increases while the on-resistance of FETs 12 and 13 decreases, so the potentials V ₁₅ and V ₁₆ further decrease, and as a result, the on-resistance of FET 14 further increases. As described above, the potentials V ₁₅ and V ₁₆ continue to decrease due to the positive feedback effect of the FET 14. And the potential V ₁₅ is
At V ₁₅ V ₁₆ +V _T , FET 14 becomes non-conductive, so the potentials V ₁₅ and V ₁₆ further decrease, and eventually FET 11,
The low level is determined by the on-resistance ratio of 12 and 13. The input voltage V _IN when the potential V ₁₅ becomes V ₁₅ =V ₁₆ +V _T is the input high level voltage V _IN of this hysteresis circuit.

Next, a case where the input voltage V _IN transitions from a high level to a low level will be described. Potential V ₁₅ , V ₁₆
increases according to the on-resistance of FETs 11, 12, and 13. Among the conditions that the potential V ₁₅ is V ₁₅ = V ₁₆ +V _T or the input voltage V _IN is V _IN =V ₁₆ +V _T ,
When the input voltage V _IN decreases to the higher side, FET14
conducts (the former condition), or the FET 12 becomes non-conductive, further increasing the potential V ₁₅ , which eventually makes the FET 14 conductive (the latter condition), thereby increasing the potential V ₁₆ . Once the FET 14 becomes conductive, the positive feedback action causes the potential V ₁₅ to rise to the power supply voltage V _D and the potential V ₁₆ to a value determined by the on-resistance of the FETs 13 and 14 . The input voltage at this point is the input low level voltage V _IL of this hysteresis circuit.

Now, what determines the value of the input high level voltage V _IN is mainly the on-resistance ratio of FETs 13 and 14, and in order to set the input high level voltage V _IN high,
The channel width of FET14 must be increased. Further, it is the on-resistance ratio of the FETs 11, 12, and 13 that determines the value of the input low-level voltage V _IL . In order to set the input low level voltage V _IL low, the channel width (more generally, mutual conductance gm, assuming the channel length is constant) of the transistors 12 and 13 must be increased. Therefore, an appropriate hysteresis width (|V _IN −
In order to have V _IL |), the channel width of the FET 14 must be set extremely large. Thus, the load capacity of node 15 is, in addition to FET 14,
Although other gates are added, the load of this hysteresis circuit is dominated by FET 14, and only extremely slow operation can be expected.

In addition, Fig. 3 shows the power supply voltage characteristics of the input low level voltage V _IL and the input high level voltage V _IH , and as mentioned above, the input high level voltage V _IH is
Since it is determined by the ratio of the on-resistance of

As described above, conventional hysteresis circuits have the drawbacks that they can only operate at low speeds and that their characteristics are highly dependent on the power supply voltage and lack stable operation.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a hysteresis circuit which operates at high speed and whose characteristics are stable with little dependence on power supply voltage.

[Structure of the invention]

The hysteresis circuit of the present invention includes a first field effect transistor that operates as a load element, and a second field effect transistor that is connected in series and performs an amplification operation with its gate as an input terminal.
and a third field effect transistor; a second amplifier circuit that inverts and amplifies the output of the first amplifier circuit and uses the output as an output terminal;
and a fourth field effect transistor for a feedback element, the gate of which is connected to the output of the second amplifier circuit, and the fourth field effect transistor is connected in parallel with the second field effect transistor.

[Explanation of Examples]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 4 is a circuit diagram of one embodiment of the present invention, and FIGS. 5 and 6 are characteristic diagrams of this embodiment.

According to FIG. 4, this embodiment includes a depletion type first FET 21 that operates as a load element, and a second FET 22 and a third FET 23 that are connected in series and perform an amplifying operation with the gate as an input terminal 30. a first amplifier circuit 32; the output of the first amplifier circuit 32 is inverted and amplified, and the output is sent to the output terminal 3;
1 and an inverter 27 as a second amplifier circuit.
and a fourth FET 24 whose gate is connected to the output of the inverter 27 and which is connected in parallel with the second FET 22 and operates as a feedback element.

Note that the FETs 22, 23, and 24 are of the enhancement type, and the first amplifier circuit 32 operates as an inverter, and the gate is connected to the input terminal 30 between the source of the FET 22 and the ground point 28 as a reference potential.
FET23 connected to is inserted. Also,
The connection point between the source of FET21 and the drain of FET22 forms a node 25, and the source of FET22 and the drain of FET22 form a node 25.
The connection point of the drain of 23 forms a node 26.

Next, the node potential V ₂₅ and inverter 2 shown in FIG.
The operation of this embodiment will be described with reference to the input/output characteristics of No. 7 (the output voltage V _OUT is the inverse of the node potential V ₂₅ ).

First, when the input voltage V _IN transitions from a low level to a high level, the following occurs. input voltage
When V _IN <threshold voltage V _T , the FETs 22 and 23 are non-conductive, so the potential V ₂₅ at the node 25 is kept at a high level (power supply voltage V _D ). Also, output voltage
V _OUT becomes low level. Therefore, FET 24 is also non-conductive. When the input voltage V _IN is the threshold voltage V _T , the FET 23 is conductive. No matter what value (0 to V _D −V _T ) the potential V ₂₆ at the node 26 is in the initial state, the potential V ₂₆ becomes a low level when the FET 24 starts conducting. As the input voltage V _IN increases, FET2
The potential V ₂₅ decreases according to the on-resistances of the transistors 1, 22, and 23. When the potential V ₂₅ becomes lower than the input low level voltage V _ILA of the inverter 27 (at this time, V _IN = V _IH ), the output voltage V _OUT becomes high level, and the FET 24
is conductive. As the FET 24 becomes conductive, the potential V ₂₅ further decreases, and a low level determined by the on-resistance of the FETs 21, 22, 23, and 24 is output.

Next, a case where the input voltage V _IN transitions from a high level to a low level will be described. Since the ratio of the on-resistance of FET 21 to the on-resistance of the part consisting of FETs 22, 23, and 24 is extremely large, when V _IN is lowered to a sufficiently low level V _IL , the potential V ₂₅ rises, and the input high level of inverter 27 Voltage (V _IHA )
When the output voltage V _OUT reaches a low level.
Then, the FET 24 becomes non-conductive, but the on-resistance ratio between the FET 21 and the other FETs 22 and 23 becomes smaller, so that the potential V ₂₅ further increases.

As described above, the circuit of this embodiment performs hysteresis operation. In this embodiment, the input high level V _IN is mainly determined by the on-resistance ratio of FET 21 and FETs 22 and 23, and in order to increase V _IH ,
The channel width of FETs 22 and 23 may be narrowed.
In addition, the input low level V _IL is mainly caused by FET21 and FET
It is determined by the on-resistance ratio of FETs 23 and 24, and in order to set V _IL low, FETs 23 and 24, especially FET 23
All you have to do is increase the channel width. In order to satisfy the requirements for both the input high level voltage V _IH and the input low level voltage V _IL , the channel width of the FET 22 is narrow, and the channel width of the transistors 23 and 24, especially the FET 23, is narrow.
All you have to do is increase the channel width. Also, the potential V ₂₅
In order to accurately detect changes in
It is necessary to increase the gain of 7. In this embodiment, unlike the conventional example shown in FIG. 1, the load on the node 25 is not caused by the feedback FET.
High-speed operation is possible. Further, in this embodiment, the feedback FET 24 is added to the output load of the inverter 27, but it is smaller than the conventional feedback FET, so the inverter 27 does not particularly impair high-speed operation. Also, input high level voltage V _IH
And the power supply voltage dependence of the input low level voltage V _IL is
The input high level voltage V _IH is connected to FET21 as mentioned above.
It is determined by the on-resistance ratio of FETs 22 and 23, and the input low level voltage is determined by the on-resistance ratio of FET 21 and FETs 23 and 24, so as shown in FIG. 6, it is small and can be applied to a wide range of power supply voltages.

In the above explanation, the N-channel silicon gate MOS type has been described, but it is clear that the same effect can be obtained with the P-channel MOS type or the CMOS type in which the load element and the amplification and feedback elements have different conductivity types. be. Furthermore, it goes without saying that the gate insulating film and electrode materials are not limited to oxide films and polysilicon, respectively, and the present invention is also applicable to insulated gate (MIS) type FETs.

〔Effect of the invention〕

As explained in detail above, the hysteresis circuit of the present invention is configured to drive the FET that operates as a feedback element with the output of the second amplifier circuit that inverts and amplifies the output of the first amplifier circuit that is the input stage. Therefore, it is not necessary to use a FET that operates as a feedback element as in the past, with a particularly large channel width (more generally, mutual conductance), and it is sufficient to use one with a small channel width. In addition to enabling high-speed operation, the input high-level voltage V _IH and input low-level voltage V _IL are both determined by the ratio of the on-resistance of the depletion type load FET and other FETs, so the hysteresis width is less dependent on the power supply voltage. It has the advantage of being very stable in operation with little turbulence.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of a conventional hysteresis circuit, FIGS. 2 and 3 are characteristic diagrams of the conventional example shown in FIG. 1, FIG. 4 is a circuit diagram of an embodiment of the present invention, and FIG.
6 and 6 are characteristic diagrams of this embodiment. 11-14...field effect transistor, 15,
16...Node, 17...Grounding point, 18...Power supply,
19...Input end, 20...Output end, 21-24...
...field effect transistor, 25, 26...node,
27... Inverter, 28... Grounding point, 29...
Power supply, 30...input end, 31...output end, V _IN ...
...Input voltage, V _OUT ...Output voltage, V _T ...Threshold voltage, V _IH ...Input high level voltage, V _IL ...Input low level voltage, V ₁₅ , V ₁₆ , V ₂₅ , V ₂₆ ... ...Nodal potential.

Claims (1)

[Claims] 1 a depletion type first insulated gate field effect transistor having a source-drain path connected between a first power supply terminal and a first node; Each sauce
second and third enhancement type insulated gate field effect transistors having drain paths connected in parallel; and an enhancement type insulated gate field effect transistor having a source-drain path connected between the second node and a second power supply terminal. a fourth insulated gate field effect transistor; means for commonly applying an input voltage to the gates of the second and fourth insulated gate field effect transistors; 1. A hysteresis circuit comprising: an inverter having an output connected to the gate of a gate field effect transistor; and an output voltage is extracted from the output of the inverter.