JPH0441510B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to highly integrated MIS type semiconductor devices, and particularly to a wiring layer structure for forming stable electrode wiring in miniaturized contact holes.

(b) Background of the Technology Aluminum or aluminum is a common wiring material used in the circuit construction of integrated circuit boards.
Silicon alloys are often used. Its major characteristics are that it has a low resistance value, has excellent adhesion to silicon and silicon oxide films, and can form ohmic contact with p-type and n-type diffusion layers. However, since aluminum causes a eutectic reaction with silicon, a eutectic alloy is created at the interface where aluminum and silicon layer (diffusion layer) meet during repeated heat treatments during the semiconductor process, creating deep etch pits in the diffusion layer and causing junction breakdown. This is well known. In particular, as semiconductor devices become more highly integrated and miniaturized, the problem becomes more serious as the diffusion region becomes narrower and shallower. For the above reasons, aluminum is used instead of aluminum in micro devices that require shallow junctions.
Uses silicon alloy. An aluminum alloy containing 1 to 2% silicon is used to suppress the solid solution of silicon from the silicon substrate, that is, the generation of etch pits. It is also an effective means to provide a barrier by interposing a high melting point metal compound as a barrier material between the aluminum wiring layer and the silicon layer.

(c) Conventional technology and problems Taking a MOS type semiconductor device, which is the mainstream of LSI, as an example, a conventional example in which polycrystalline silicon is used as the gate electrode and an aluminum-silicon alloy wiring layer is formed in the contact hole is explained using Figure 1. .

FIG. 1 is a process diagram showing a conventional n-channel silicon gate structure MOS transistor.
As shown in A in the figure, an oxide film (SiO ₂ ) 2 is embedded in a p-type silicon substrate 1, a gate oxide film 3 is formed by dry thermal oxidation, and then a polycrystalline silicon 4 for forming a gate electrode is deposited by CVD. The gate oxide film 3 is grown on the gate oxide film 3 by the method.

Next, as shown in (b), polycrystalline silicon 4 and gate oxide film 3 are removed by etching, leaving gate electrode 5 alone. Using this gate electrode 5 as a mask, sources and drains 6 and 7 are diffused and formed by ion implantation as shown in FIG. In this case, the implanted impurity is phosphorus P or arsenic As, which is diffused to form an n-type diffusion layer. Next, phosphorus silicate glass
After an insulating layer 8 such as PSG is grown by CVD, a contact area is opened as shown in the figure, and a melt process is performed to soften the shape of the stepped portion.
Next, as shown in (d), an aluminum-silicon alloy 9 is deposited on the entire surface of the substrate 1 by sputtering, and then (e) a wiring pattern is formed using a photo-etching technique and heat treatment is performed to make ohmic contact with the diffusion layer to form the source region 6. , a contact electrode 10 shown in the figure in the drain region 7, respectively.
11 is obtained.

However, in the contact wiring layer formed in this way, silicon exceeding the solid solubility limit in the aluminum silicon alloy film and at the alloy film-silicon interface may be formed during electrode contact formation or during heat treatment during the assembly process, especially in the case of fine contact holes, e.g., 2μ or less. There is precipitation. This precipitation occurs in large numbers around the contact hole, as in the case of the etching pit described above, and the precipitated phase is aluminum-doped p-type silicon, which can be in any orientation on the oxide film, but on the diffusion layer (silicon substrate). In this case, epitaxial growth is performed, and so-called solid-phase epitaxial growth is observed.
A specific example is shown in FIG. FIG. 2 is an enlarged view of a contact region showing an example of a silicon deposit layer deposited in a contact hole.

In the figure, the substrate 1 is subjected to repeated heat treatment.
A silicon precipitate layer 14 is grown on the contact electrode 13 in contact with the n ⁺ diffusion layer 12 as shown in the figure. For this reason, contact resistance increases and, in some cases, a disconnection state occurs. Moreover, the silicon precipitated layer 14 is aluminum-doped p-type silicon, and the contacting interface is n ⁺
There are problems such as affecting the semiconductor characteristics of the diffusion layer 12.

(d) Purpose of the Invention In view of the above-mentioned drawbacks, the present invention aims to suppress silicon precipitation in contact electrodes, provide a stable aluminum alloy wiring structure, and obtain an MIS type semiconductor device that is compatible with miniaturization. do.

(e) Structure of the Invention According to the present invention, the above object is a method of forming a wiring layer for a contact electrode on a substrate, the method comprising depositing an aluminum-silicon alloy containing 10% or more of silicon on the substrate. The method includes a step of forming a first wiring layer, and a step of depositing aluminum on the first wiring layer to form a second wiring layer. The average silicon content of the first wiring layer and the second wiring layer is 1 to 2.
%.

(f) Examples of the invention Examples of the invention will be described in detail below with reference to the drawings. FIG. 3 is a process diagram for forming a wiring layer in which an aluminum film is laminated on an aluminum silicon alloy film according to an embodiment of the present invention.

First, as shown in figure a, the insulating layer 22 on the substrate 21 is
After a contact window is opened in the window, a first wiring layer 2 made of a silicon-rich (silicon content of 10% or more) aluminum-silicon alloy is formed to cover this window.
form 3. Next, as shown in Figure b, a second wiring layer 24 made of pure aluminum is formed on the first wiring layer 23. The first wiring layer 23 and the second wiring layer 24 are formed by a continuous sputtering method. or,
After forming the first wiring layer 23 by a sputtering method, annealing is performed at 400 to 500°C for 30 minutes in a furnace with a clean atmosphere such as nitrogen gas or a mixed gas of nitrogen and hydrogen to improve the adhesion with the diffusion layer. After that, the second wiring layer 24 may be formed by a sputtering method. Next, as shown in figure c, the first wiring layer 23 and the second wiring layer 2 are formed.
4 to form contact electrodes 25, 2.
form 6.

The film thicknesses of the first wiring layer 23 and the second wiring layer 24 are determined depending on the silicon content of the first wiring layer 23, such that the average silicon content of both wiring layers is 1 to 1.
2%. That is, when the total thickness of both wiring layers is 1 μm, the thickness of the first wiring layer 23 is approximately 1000㎜, 95 if the silicon content is 10%.
If it is %, it should be about 100〓. By doing so, the specific resistance of the entire wiring layer can be suppressed to the same level as that of a conventional wiring layer made of a single layer of an aluminum-silicon alloy with a silicon content of 1 to 2%.

Note that when limiting the silicon content of the first wiring layer 23, contact electrodes formed by laminating a second wiring layer of pure aluminum on the first wiring layer with various silicon contents are annealed. I conducted an experiment. The data is shown below. All data are contact resistance values when annealed at 500℃, and from the left, before annealing, 30 minutes after, and 60 minutes after annealing.
The values after minutes, 90 minutes, and 120 minutes are shown in KΩ, and those in a non-ohmic state are marked as X. Total film thickness is approximately 1μm.

1% silicon: 0.5 1.3 X 4% silicon: 0.4 0.9 6.0 The increase in resistance was small and there was no disconnection. This is considered to be because the first wiring layer in contact with the substrate is silicon-rich, which suppresses the epitaxial growth of silicon on the substrate. Note that if the silicon content is 95% or more, the film thickness must be 100% or less, which is not practical.

Contact electrodes 25, 2 obtained as above
In No. 6, there is little increase in contact resistance due to heat treatment in subsequent steps, and there is no possibility of disconnection. Therefore, a device with high characteristics and reliability can be obtained.

(g) Effects of the invention As explained in detail above, the electrode wiring layer structure according to the present invention can be applied to MIS type semiconductor devices having miniaturized contact holes, and in particular, the reliability of device characteristics is improved. It has great effects such as stability.

[Brief explanation of drawings]

FIG. 1 is a process diagram showing a conventional n-channel type silicon gate structure MOS transistor, FIG. 2 is an enlarged view of a contact region showing an example of a silicon deposit layer deposited in a contact hole, and FIG. FIG. 3 is a process diagram for forming a wiring layer in which an aluminum film is laminated on an aluminum alloy film according to an example. In the figure, 1, 21... substrate, 2... oxide film, 3...
Gate oxide film, 4... Polycrystalline silicon, 5... Gate electrode, 6, 7... Source, drain region,
8, 22... Insulating layer, 9... Aluminum silicon alloy, 10, 11, 13, 25, 26... Contact electrode, 12... n ⁺ diffusion layer, 14... Silicon precipitation layer, 23... First Wiring layer, 24... second wiring layer.

Claims (1)

[Claims] 1. A method for forming a wiring layer for forming contact electrodes on a substrate, which method comprises depositing an aluminum-silicon alloy containing 10% or more silicon on the substrate to form a first wiring layer. and a step of depositing aluminum on the first wiring layer to form a second wiring layer, the film thickness ratio of the first wiring layer and the second wiring layer. A method for manufacturing a semiconductor device, characterized in that the first wiring layer and the second wiring layer have an average silicon content of 1 to 2%.