JPH0441512B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device in which a MOS field effect transistor and a protection diode for the gate of the MOS field effect transistor are integrally formed on the same semiconductor substrate.

Conventional structure and its problems The gate oxide film used in MOS field effect transistors is usually very thin, 250~1000~, and its breakdown voltage is only about 20V~70V, so the gate is easily destroyed by surge voltage. . Therefore, it is common practice to insert a protection diode that breaks down below the breakdown voltage of the oxide film between the gate and the source or between the gate and the drain.

The protection diode is usually integrally formed on the same substrate as the MOS field effect transistor. Although the gate oxide film was protected by the formation of the protective diode, the withstand voltage between the source and drain was significantly reduced due to the parasitic bipolar transistor effect, making it impossible to bring out the full performance of the MOS field effect transistor.

FIG. 1 is a half-process sectional view of a semiconductor device in which a conventional DSA (diffusion self-align) type MOS field effect transistor and a gate protection diode are integrally formed on the same substrate.

FIG. 1a shows a gate electrode 3 selectively placed on a gate oxide film 2 formed on the surface of an N-type semiconductor substrate 1.
This is a step of forming a P-type channel forming region 4 and a P-type base region 5 of a protection diode at the same time.

The P-type channel forming region 4 and the P-type base region 5 of the protection diode are 1×10 ¹³ to 1×10 ¹⁴
It is formed to a predetermined depth by ion implantation of B ⁺ or the like on the order of atms/cm ² and subsequent thermal diffusion.

FIG. 1b shows selectively opening the register 6;
This is the process of implanting ions such as As. As a result,
The N-type source injection region 7 of the MOS field effect transistor and the N-type emitter injection regions 8-1 and 8-2 of the protection diode are simultaneously formed. The implantation amount of ions such as As used here is 3×10 ¹⁵ atms/
It has a very high concentration of about cm ² and is necessary to sufficiently lower the source resistance.

FIG. 1c shows a step of forming an N-type source region 9 and an N-type emitter region 10-1, 10-2 by diffusion, a step of depositing Sio ₂ 11 on the surface by a method such as CVD, and selectively forming a contact window. The next step is to form the source electrode 12 and emitter electrodes 13-1 and 13-2. The emitter electrode 13-1 is connected to the source electrode 12, and the emitter electrode 13-2 is connected to the gate electrode 3, and operates as a protection diode.

Although not shown in FIG. 1c, the P-type channel forming region 4 and the N-type source region 9 are connected to have the same potential in order to keep the channel potential stable. G, S, and D in FIG. 1c indicate a gate terminal, a source terminal, and a drain terminal, respectively.

FIG. 2 shows a configuration diagram of a parasitic bipolar transistor using a protection diode. In this case, two parasitic bipolar transistors Tr ₁ and Tr ₂ are formed. Since the parasitic bipolar transistors Tr ₁ and Tr ₂ have the same shape, Tr ₁ will be taken as an example to explain the problem of reduced breakdown voltage caused by the parasitic bipolar transistors in a conventional semiconductor device.

When operating a MOS field effect transistor,
Normally, the source terminal S is grounded, and the gate terminal G is +
3V ~ around +10V, +40V ~ for drain terminal D
Add a bias of about 50V. Therefore, between the source terminal S and the drain terminal D in Fig. 2, there is a voltage of 40V to
50V bias is added. N-type emitter region 10
-1 as emitter, P type base region 5 as base, N
In the parasitic bipolar transistor Tr ₁ using the type semiconductor substrate 1 as the collector, the P type base region 5
BV _CBO is the breakdown voltage between the N-type emitter region 10-1 and the N-type semiconductor substrate 1 (when the N-type emitter region 10-1 is grounded).
BV _CEO , if the current amplification factor is h _FE , then A relationship is established. Therefore BV _CBO = 100V, h _FE
If = 40, BV _CEO = 39.8V, which is lower.
The breakdown voltage between the source and drain of the MOS field effect transistor should match BV _CBO (100V in this case), but by forming the protection diode, the breakdown voltage between the source and drain becomes 39.8V, which is higher than the original breakdown voltage. You can only get a value less than 1/2 of
It has been extremely difficult to operate MOS field effect transistors at high power.

OBJECTS OF THE INVENTION An object of the present invention is to provide an excellent semiconductor device in which a MOS field effect transistor and a gate protection diode are integrally formed on the same semiconductor substrate, and the withstand voltage does not decrease due to the protection diode.

Structure of the Invention The present invention provides a structure in which a MOS field effect transistor and a gate protection diode are integrally formed on the same semiconductor substrate, and the amount of impurity per unit area in the emitter region of a parasitic bipolar transistor generated by the protection diode is smaller than that in the base region. The amount of impurities per unit area of the material is below. Furthermore, the present invention provides that the amount of impurities per unit area in the source region of the MOS field effect transistor is
It is characterized in that the amount of impurities is greater than or equal to the amount of impurities per unit area in the emitter region of the protection diode.

DESCRIPTION OF EMBODIMENTS FIG. 3 is a half-step cross-sectional structural diagram showing an embodiment of the semiconductor device of the present invention. In Figure 3, the first
Components equivalent to those in the figures and FIG. 2 are designated with the same reference numerals and symbols.

In FIG. 3a, a gate oxide film 2, a gate electrode 3, a P-type channel forming region 4, and a P-type base region 5 are formed on an N-type semiconductor substrate 1 in exactly the same process as in FIG. 1A. The gate electrode 3 may be formed of polycrystalline Si, a high melting point metal material, or the like.

FIG. 3b shows a step of forming an opening in the resist 14 only in the source region of the MOS field effect transistor and forming an N-type source implantation region 7 by implanting AS ions or the like. The amount of implantation is as high as 3×10 ¹⁵ atms/cm ² in order to lower the source resistance and ion resistance. In this step, the implantation into the region where the emitter of the protection diode will be formed is performed using the resist 14.
It is not done at all because it is covered with

FIG. 3c shows the step of forming the N-type source region 9 by diffusion, forming an opening in the resist 15 in the region where the emitter of the protection diode is to be formed, and forming a low-concentration N-type source region 9.
The mold emitter implantation regions 16-1 and 16-2 are filled with As.
Alternatively, it is a step of forming by ion implantation of P or the like. The injection amount is a very low concentration of about 1×10 ¹² to 1×10 ¹⁴ atms/cm ² . In this case, when forming the low concentration N-type emitter implantation regions 16-1 and 16-2,
The resistor 15 above the N-type source region 9 is opened, so that N-type impurities may enter the N-type source region 9. Furthermore, the formation of the N-type source region 9 by diffusion is performed by forming the low concentration N-type emitter implantation regions 16-1 and 16-1.
This may be carried out after the formation of -2.

FIG. 3d shows the step of forming the low concentration N-type emitter regions 17-1 and 17-2 by diffusion and the step of forming the electrodes, in which the electrodes of the MOS field effect transistor and the protection diode are formed in the same manner as in FIG. 1c. are connected to each other.

According to the semiconductor device of the present invention shown in FIG.
Low concentration N type emitter regions 17-1, 17-2 and N
The concentration of the type source regions 9 is set independently, and the amount of impurity per unit area of the N type source region 9 is the same as that of the low concentration N type emitter regions 17-1 and 17-2.
1 to 3 orders of magnitude higher. Therefore, the source resistance and on-resistance of the MOS field effect transistor do not increase, and the original transistor characteristics can be brought out.

On the other hand, in the parasitic bipolar transistors generated by the protection diodes, the impurity amount per unit area of the low concentration N-type emitter regions 17-1 and 17-2 is 1×10 ¹² to 1×10 ¹⁴ atms/cm ² , and P Since the amount of impurities in the mold base region 5 is the same or an order of magnitude lower than the 1×10 ¹³ to 1×10 ¹⁴ atms/cm ² , the emitter injection efficiency is significantly lowered and the current amplification factor (h _FE ) cannot be reduced to 1 or less. can. When the current amplification factor (h _FE ) becomes 1 or less, there is no drop in BV _CEO due to h _FE as described above, BV _CEO BV _CBO is obtained, and there is no drop in breakdown voltage due to the addition of a protection diode. The amount of impurity implanted into the P-type base region 5 of the protection diode is 2×10 ¹³ atms/cm ² , and the amount of impurity implanted into the low concentration N-type emitters 16-1 and 16-2 is 1.
When formed at ×10 ¹³ atms/cm ² , the value of h _FE of the parasitic bipolar transistor could be made approximately 1.

As an embodiment of the semiconductor device of the present invention, a bidirectional protection diode that protects against both positive and negative voltages between the gate and the source has been described as an example. It is clear that a unidirectional protection diode that is not connected to the gate and protects only one direction between the gate and drain has the same effect. Although an N-channel NOS field effect transistor has been described as an embodiment of the semiconductor device of the present invention, it goes without saying that a P-channel MOS field effect transistor can also have similar effects.

Effect of the invention The present invention brings about the following effects.

(1) Since the current amplification factor of the parasitic bipolar transistor due to the protection diode can be made less than 1, there is no drop in breakdown voltage between the source and drain due to the addition of the protection diode.

(2) The source region of a MOS field effect transistor is
Since the concentration is set higher than that of the emitter region of the protection diode, there is no increase in source resistance and on-resistance.

[Brief explanation of the drawing]

FIGS. 1a to 1c are half-step cross-sectional views showing a conventional semiconductor device, FIG. 2 is a configuration diagram of a parasitic bipolar transistor using a protection diode, and FIGS. 3a to d show an embodiment of the semiconductor device of the present invention. It is a half-process sectional view. 1... N-type semiconductor substrate, 2... Gate oxide film,
3... Gate electrode, 4... P-type channel forming region, 5... P-type base region, 9... N-type source region, 10-1, 10-2... N-type emitter region,
14, 15...Resist, 16-1, 16-2...
...Low concentration N-type emitter implantation region, 17-1, 17
-2...Low concentration N-type emitter region.

Claims (1)

[Scope of Claims] 1. A semiconductor substrate of one conductivity type as a drain region, a channel formation region of an opposite conductivity type formed from the main surface of the semiconductor substrate, and a source region of one conductivity type formed in the channel formation region. , a MOS field effect transistor comprising a gate electrode adjacent to the source region and formed on the channel forming region via an insulating film; and a first diffusion region of an opposite conductivity type formed from the main surface of the semiconductor substrate. , a gate protection diode having a second diffusion region of one conductivity type formed in the first diffusion region and connected to the gate electrode of the MOS field effect transistor; The amount of impurity implantation of one conductivity type is equal to or less than the amount of impurity implantation of opposite conductivity type per unit area in the first diffusion region, and a parasitic bipolar region formed by the drain region, the first diffusion region, and the second diffusion region A semiconductor device characterized in that the h _FE of a transistor is 1 or less. 2. A patent characterized in that the amount of one conductivity type impurity implanted per unit area in the source region of the MOS field effect transistor is greater than or equal to the one conductivity type impurity implanted amount per unit area in the second diffusion region of the protection diode. A semiconductor device according to claim 1.