JPH0442825B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor testing device, and more particularly to a semiconductor testing device for probe testing pellets within a semiconductor wafer.

[Conventional technology]

In general, a marking device is added to a probing test for testing the characteristics of pellets within a wafer, and defective pellets are mechanically marked with a scratch or the like.

When a predetermined number of pellet failures occur consecutively, the testing device automatically stops at that point (hereinafter referred to as continuous failstop), and the operator then manually removes the marking device. The method used was to turn off the switch, turn on the exhaust signal switch to clear the data, and then restart the engine.

The pellet test data is recorded on tape and is also used for pellet quality analysis.

[Problem that the invention seeks to solve]

In the conventional semiconductor testing equipment described above, if continuous fail-stops are applied, the operating time of the expensive equipment will be reduced, and if continuous fail-stops are not applied, wafers that can be used for adjustment of manufacturing equipment will be destroyed as defective sample wafers. There was also the problem that it was not possible to analyze the quality of defective pellets.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor testing apparatus that can produce defective sample wafers for quality analysis without stopping unnecessarily in the case of continuous defective pellets.

[Means for solving problems]

The semiconductor testing device of the present invention comprises: (A) a probe portion having a prober that sequentially contacts a plurality of pellets under test in a semiconductor wafer; (B) one input terminal receiving a test start signal of the probe portion; (C) a testing/counting section whose output terminal outputs a signal indicating the test result; (C) whose input terminal outputs a signal indicating the test result; A marking signal is outputted to one output terminal only when the good/bad result signal is a bad result signal and the number of consecutive defects is smaller than a predetermined value, and the number of consecutive defects is counted. If the value exceeds a predetermined value, the marking signal is not output, and the data discharge signal is output from the other output terminal to the test/counting section to continue the test, and the test on the final pellet in the semiconductor wafer is completed. (D) a marking section whose input end receives the marking signal and whose output end supplies the marker signal to the probe section.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of the invention.

The semiconductor testing apparatus includes a probe section 1 having a prober that contacts a plurality of pellets under test within a semiconductor wafer W placed on a wafer stage WS.
Then, the input terminal receives the test start signal S _S from the probe section 1 and counts the number of good and bad pellets as a result of the test.
A test/counting section 2 whose output terminal supplies the test result signal S _R to the probe section 1, and an input terminal which receives the pass/fail result signal S _R from the probe section 1 and counts it, and the defect result signal indicates the number of continuous defects. If the number of consecutive defects is smaller than a predetermined value K, a marking signal S _M is output to one output terminal, and if the number of consecutive defects is greater than a predetermined value K, a marking signal is output.
Data discharge signal from other output terminal without outputting S _M
A control section 3 outputs S _D to the test/counting section 1, continues the test until the last pellet in the wafer while clearing the data, and then outputs a stop signal, and the input end receives the marking signal S _M , and the output end Marker signal S _n
The marking device 4 includes a marking device 4 that supplies markers M of the probe section 1 with the marking device 4.

FIG. 2 is a flow chart for explaining the operation of the block diagram of FIG.

First, before starting the test, a predetermined number of consecutive fail-stops is set to a predetermined value K.

Next, the test start signal S _S is output from the probe device to start the test.

If there is a pellet to be tested, the probe section 1 comes into contact with it, and determines whether it is good or bad based on the signal from the test/counting section 2.

Here, if the pellet under test is good, increase the number of good products on the counter in the test/counting section 2 by one, and set the number of defective products continuously displayed in the control section 3 to K.
Return to pellet movement for measurement preparation and repeat this flow.

If the pellet to be tested is defective, the number of defects on the counter in the test/counting section 2 is increased by one, and the number of consecutive defects in the control section 3 is added by 1 and marked.

If the control unit 3 determines that the continuous fail stop occurs, the process moves to another point A.

The probe unit 1 moves the pellet to prepare for measurement, determines whether there is a pellet to be tested, and if so, the test/counter unit 2 determines whether it is good or bad.

After that, the number of good and defective numbers is counted inside the test/counting section 2, but the marking and continuous fail-stop judgment is not performed and the control section 3 sends a signal S _D
Accordingly, the test/counting section 2 clears the data.

Then, after the test is repeated from the measurement preparation stage and all the pellets to be tested are completed, the process is stopped by an alarm.

Embodiment 2 FIG. 3 is a block diagram of a second embodiment of the present invention.

The semiconductor testing apparatus is similar to the semiconductor testing apparatus shown in FIG. 1, except that the control section 3a is different from the control section 3.

The control unit 3a has a gate G that receives a test start signal S _S from the probe unit 1, skips a predetermined number of times (k-1), and outputs a pseudo-good result signal S _G to the probe unit 1.
and a conversion gate C which receives the test result signal S _R from the test/counter section 2 and converts it into a good signal.

That is, the test start signal S _S output from the probe section 1 is set to a predetermined number k by the gate G, skipping (k-1) test start signals S'S, and only once for every k test start signals _S 'S.
is sent to the test/counting section 2, and the probe section 1
The test result signal S _R to be returned to is a pseudo-good signal
Becomes S _G.

In addition, the good/bad result signal S _R sent from the test/counting section 2 is all converted into a pseudo good result signal by the conversion gate C and judged, so the marking signal S _M
is not output.

FIG. 4 is a flow chart for explaining the operation of the block diagram of FIG.

The flowchart is a predetermined value k = 3 between points B and B'.
The flowchart is the same as the flowchart in FIG. 2, except that a test pellet number determination unit is provided.

In this case, after the number of consecutive failures exceeds the number of consecutive failstops K and the pellets enter the flow at point A, the pellets are tested every three pellets, that is, two pellets are skipped, so the number of pellets tested decreases and the alarm is raised. The top becomes faster.

[Effects of the Invention] As explained above, the present invention destroys pellets by continuing the test while discharging data from the test/counting section without automatically marking when a continuous fail stop occurs. You can easily create defective sample wafers that have not been
By being able to perform wafer failure analysis smoothly, it has the effect of quickly improving the quality of semiconductors.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of the present invention;
FIG. 2 is a flowchart for explaining the operation of the block diagram in FIG. 1, FIG. 3 is a block diagram of the second embodiment of the present invention, and FIG. 4 is a flowchart for explaining the operation of the block diagram in FIG. 3. This is a flowchart for 1...Probe part, 2...Test/counting part, 3,
3a...Control unit, 4...Marking unit, M...Marker, S _D ...Data discharge signal, S _M ...Marking signal, S _R ...Test result signal, S _S ...Test start signal, S _n ...Marker signal, W...Semiconductor wafer.

Claims (1)

[Claims] 1. (A) A probe portion having a prober that sequentially contacts a plurality of pellets under test in a semiconductor wafer; (B) One input end receiving a test start signal of the probe portion; (C) a test/counting section whose output end outputs a signal representing the test result by testing the pellets under test and counting the number of good/defective test results; and outputs a marking signal to one output terminal only when the pass/fail result signal is a fail result signal and the number of consecutive failures is smaller than a predetermined value, and the number of consecutive failures is equal to the predetermined value. In the above case, the marking signal is not output, and the data discharge signal is output from the other output terminal to the test/counting section to continue the test, and after completing the test on the final pellet in the semiconductor wafer. A semiconductor testing device comprising: a control section that outputs a stop signal; (D) a marking section whose input end receives the marking signal and whose output end supplies the marker signal to the probe section.