JPH0444286B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data format conversion method, particularly a method for inputting multiple parallel data, performing logical operations and rearranging between data bits, and outputting data. This paper relates to a data format conversion method.

[Conventional technology]

A circuit diagram of a conventional data format conversion circuit corresponding to an embodiment of the present invention is shown in FIG. First, a plurality of input 8-bit data is divided into upper 4 bits and lower 4 bits and held in the 4-bit memory circuit 6 for input data by control signals 101, 102, and 111 from the control signal generation circuit 10, respectively. Next, in order to convert the data format between input and output, the input data held in the 4-bit memory circuit 6 is taken into the 4-bit OR circuit 7 and the 4-bit switching gate circuit 8, and the data format is converted. Next, the data after data format conversion is converted into control signals 105 and 1 from the control signal generation circuit 10.
11 and 112, it is held in the 4-bit memory circuit 9 for output data. Then, the 4-bit gate circuit 11 is switched by the control signals 106, 113, and 114 from the control signal generation circuit 10 to output a plurality of output data in 8-bit units in a time-division manner.

In other words, the circuit configuration includes independent holding circuits on the input and output sides and an arithmetic processing circuit for converting the data format between the input and output, so the number of input and output data corresponds to the number of input and output data and the parallel data length. required a circuit.

[Problem that the invention seeks to solve]

The conventional data format conversion method described above requires a large number of circuits because it requires a holding circuit for each parallel input/output data, and has the disadvantage that the circuit configuration changes every time the combination of input/output data changes. It was hot.

An object of the present invention is to provide a data format conversion method that can reduce the number of circuits and can cope with changes in the combination of input and output data without changing the circuit configuration.

[Means for solving problems]

The data format conversion method of the present invention is a data format conversion method in which input data including at least two bit strings of a predetermined length in parallel is input as input data to be converted. (B) arithmetic processing means for executing a predetermined logical operation on a given bit string and outputting a new bit string obtained as a result of the logical operation; (C) a first storage means for temporarily storing a new bit string; (C) switching between the input data inputted from the outside and the new bit string obtained as a result of the logical operation, and storing the new bit string in the first storage means; (D) a second storage means for temporarily storing the first bit string of the two bit strings provided to the arithmetic processing means as the bit string used for the logical operation; (E) ) When the input data is input from outside,
The input data is selected through the switching gate means and stored in the first storage means, and when the arithmetic processing means requires two bit strings for the logical operation, the input data is selected and stored in the first storage means. The first bit string is selected from the bit strings stored in the means, read out and stored in the second storage means, and then the first bit string stored in the second storage means is read out. Another bit string on which the logical operation is to be performed is read from the first storage means, stored as a second bit string in the holding means built in the arithmetic processing means, and The first bit string and the second bit string
A new bit string obtained by the arithmetic processing means is stored in the first storage means via the switching gate means, and the format conversion of the input data is performed. When output data is to be output as subsequent data, the bit strings necessary to constitute the data after format conversion are sequentially selected from among the bit strings stored in the first storage means, and the bit strings are read out and output. Conversion control means.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention when n=4 bits. The embodiment shown in FIG. 1 includes a 4-bit switching gate circuit 1 for switching between input data and format-converted data, a 4-bit RAM circuit 2 for temporarily storing input (before conversion) data and output (after conversion) data, It is configured to include a 4-bit memory circuit 3, a 4-bit arithmetic processing and holding circuit 4, and a control signal generation circuit 5.

FIGS. 2 and 3 show explanatory diagrams and time charts of format conversion in the embodiment shown in FIG. 1.

The basic operation of the embodiment shown in FIG. 1 will be explained below. Four sets of 8-bit length input data (AB, CD,
EF, EF) are passed through the 4-bit switching gate circuit 1 by the switching signals 11 and 12 from the control signal generation circuit 5 in units of 4 bits, and are connected to the data bus 10.
1, and is stored in the area determined by the RAM address designation signals 15 to 18 from the control signal generation circuit of the 4-bit RAM circuit 2 by the write signal 19 from the control signal generation circuit 5. Next, the pre-conversion data A designated by addresses 15 to 18 is read out by the read signal 20 from the control signal generation circuit 5 and held in the 4-bit memory circuit 3 by the write signal 21 from the control signal generation circuit 5. Next, the pre-conversion data C designated by address designations 15 to 18 by the read signal 20 from the control signal generation circuit 5
is read from the 4-bit RAM circuit and transferred to data bus 1.
The data is inputted to the 4-bit arithmetic processing and holding circuit 4 via the 02.

Here, it is ORed with data A stored in the 4-bit memory circuit 3, and the result is held in the 4-bit arithmetic processing and holding circuit 4 by the write signal 22 from the control signal generation circuit 5. Then, the output is passed through the 4-bit switching gate circuit 1 by the switching signal 14 from the control signal generation circuit 5, and is further transferred to the 4-bit signal specified by addresses 15 to 18.
It is stored in the area of the RAM circuit 2 by the write signal 19. Here, as a result of the logical sum of the pre-conversion data A and C, data G is stored in the post-conversion memory area.

Next, in the same manner as above, the pre-conversion data E, E
As a result of the logical sum, the converted data I and K are 4.
The data is stored in the bit RAM circuit 2.

Next, the read signal 2 from the control signal generation circuit 5
0 reads the pre-conversion data B designated by addresses 15 to 18, and the write signal 21 reads 4.
It is held in the bit memory circuit 3. The output data is transmitted through the data bus 105 to 4 by the switching signal 13.
The write signal 1 passes through the bit switching gate circuit 1 and is sent to the area designated by addresses 15 to 18.
Store by 9. Next, address specification 15-1
Read the post-conversion data G specified by 8 and send the signal 2.
0 is output as the lower 4 bits via the read data bus 106, and at the same time, data B held in the 4-bit memory circuit 3 is sent out as the following 4 bits.

Next, the pre-conversion data D is read out in the same manner as described above and output as the lower 4 bits at the same time as the upper 4 bits of data G. That is, here, the upper 4 bits are output as the logical sum of data A and C, and the lower 4 bits are output as data that changes to data B or D depending on time.

Read the pre-conversion data F in the same way, and
By writing into the bit memory circuit 3 and then reading the converted data I, data I is output as the upper 4 bits and data F is output as the lower 4 bits.

Furthermore, the same applies to the case where data K is output as the upper 4 bits and data F is output as the lower 4 bits.

In this embodiment, n = 4 bits and all 4 arbitrary bits are ORed, but the same concept as in this embodiment can be applied even when the number of bits is other than 4 bits, or when the number of bits in the logical operation is not all bits. Data format conversion is possible.

In this embodiment, the bit configuration of input/output data is 8.
However, by simply changing the control signal generation circuit of this embodiment, format conversion of all input/output data that is an integral multiple of 4 bits can be realized with the same circuit configuration.

〔Effect of the invention〕

As explained above, the present invention allows input data to be constructed by selecting a necessary bit string from among a bit string constituting input data and a bit string obtained as a result of performing logical processing on that bit string. By configuring the data to be output as output data after converting the data format, all data format conversions can be performed using the same circuit, reducing the number of circuits and making it possible to maintain the same circuit configuration even when the combination of input and output data changes. There are effects that can be addressed without making any changes.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is an explanatory diagram showing an example of data format conversion, FIG. 3 is a time chart showing the operation of FIG. 1, and FIG. 4 is a block diagram showing an example of a conventional circuit. 1...4-bit switching gate circuit, 2...4-bit RAM circuit, 3...4-bit memory circuit, 4...
...4-bit arithmetic processing and holding circuit, 5...control signal generation circuit.

Claims (1)

[Claims] 1. A data format conversion method in which input data including at least two bit strings of a predetermined length in parallel is input as input data to be converted, (B) arithmetic processing means for executing a predetermined logical operation on a bit string and outputting a new bit string obtained as a result of the logical operation; a first storage means for temporarily storing the string; (C) switching for switching between the input data inputted from the outside and a new bit string obtained as a result of the logical operation and outputting the same to the first storage means; gate means; (D) second storage means for temporarily storing the first bit string of the two bit strings given to the arithmetic processing means as the bit string used for the logical operation; When the input data is input,
When the input data is selected and stored in the first storage means through the switching gate means, and the arithmetic processing means requires two bit strings for the logical operation, the input data is selected and stored in the first storage means. The first bit string is selected from the bit strings stored in the means, read out and stored in the second storage means, and then the first bit string stored in the second storage means is read out. Another bit string on which the logical operation is to be performed is read from the first storage means, stored as a second bit string in the holding means built in the arithmetic processing means, and The first bit string and the second bit string
A new bit string obtained by the arithmetic processing means is stored in the first storage means via the switching gate means, and the format conversion of the input data is performed. When output data is to be output as subsequent data, the bit strings necessary to constitute the data after format conversion are sequentially selected from among the bit strings stored in the first storage means, and the bit strings are read out and output. A data format conversion method comprising: conversion control means.