JPH044631B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is composed of a parameter table memory, an address control unit, and an output latch, and is capable of controlling the waiting of two input data values, reading and writing data memory, generating numerical sequences, and changing data values. qualification,
The present invention relates to an address generation circuit characterized in that transition is performed by address control of a data memory.

Conventionally, in data flow processing devices, memory has been distributed according to function, so there has been little regularity and a large amount of hardware has been required.

In cases such as image calculations, processing can often be performed at high speed by using memory in place of arithmetic circuits to modify and transition data values.
Functions such as the data value waiting function necessary for data flow control, the generation of numerical strings, and data value buffer memory were also essential.

An object of the present invention is to provide an address generation circuit that can be divided into multiple functions by controlling the address of one data memory, requires a small amount of hardware, has high hardware regularity, and is easy to manufacture. It's about doing.

The address generation circuit of the present invention provides an address for performing queue control for waiting two input data values, generation of a numerical string, data value modification, data value transition, reading and writing when used as a data value buffer, etc. It is characterized by generating a value, read/write control signal.

The address generation circuit of the present invention has the following characteristics: instruction type, address base, address size, internal state,
a parameter table memory that stores an address count; an address control unit that generates an address using a value read from the parameter table memory and an input data value; and an address value output from the address control unit and input data. It consists of an output latch that latches values and control signals in synchronization with the pipeline clock and sends them to the next stage data memory.

The present invention is disclosed in Japanese Patent Application No. 56-169152 (Japanese Unexamined Patent Publication No. 58-70360).
This is a part of the data flow processing device of the Japanese Patent Publication No.
This data flow processing device includes a transfer table memory for storing destination addresses of data, a parameter table memory for storing instructions, a data memory for temporarily storing input data for one side of a binary operation, and a transfer table memory for storing data destination addresses. A queue memory that waits for data from memory, a processor unit that performs binary operations or unary operations,
It is equipped with a ring-shaped pipeline bus that connects these and a bus interface that controls data input and output between the external bus and the external bus.

The present invention is co-located with the parameter table memory and generates the address of the data memory.

The configuration of the present invention has been described above, and its details will be explained with reference to embodiments shown in the drawings below.

FIG. 1 is a system block diagram of an address generation circuit according to the present invention. In the figure, 1 is an input latch, 2 is a parameter table memory, 3 is an address control section, 4 is an output latch, 5 is a data memory,
11 is a pipeline clock, 12 is a data identification number, 13 is an input data value, 14 is an input data type number, 15 and 16 are address counter value write signals, 17 and 18 are internal state write signals, 1
9-21 are address base and size, 22-21
23 is an internal state read value, 24 to 25 are address counter value read signals, 26 is an instruction code,
27 is an address value, 28 is a read/write control signal, 29 is a valid flag, 30 is an overflow flag, 31 is an address value of the data memory 5, 3
2 is a read/write control signal of the data memory 5, 33 is a write data value of the data memory, 3
4 is a valid flag, 35 is an overflow flag,
36 is the read data value of the data memory 5, 37
is a valid flag, 38 is an overflow flag, 3
9 is a valid flag, and 40 is an instruction selection signal.

The input latch 1 latches the data identification number 12 and input data value 13 sent from the previous stage of the pipeline in synchronization with the pipeline clock 11, and then latches the data identification number 12 and input data value 13 sent from the previous stage of the pipeline, and latches the data identification number 12 and input data value 13 sent from the previous stage of the pipeline.
and sends it to output latch 4. The parameter table memory 2 stores instruction codes, address bases, address sizes, internal states, and address counter values, and is accessed using the data identification number 12 from the input latch 1 as an address, and is accessed by the pipeline clock 11. internal state 17 in synchronization with
~18 and address counter value 15~16 are written, address base, size 19~
21, internal state read values 22 to 23, address counter value read signals 24 to 25, and instruction code 26 are read. The address control unit 3 outputs the address base and size 19 to 21 read from the parameter table memory 2, the address counter value reading signals 24 to 25, the instruction code 26, the internal states 22 to 23, and the input latch 1. Data identification number 12, input data value 1
3. Input the input data type number 14, output the address value 27, read/write control signal 28, and valid flag 29 to the output latch 4, and send the address counter values 15 to 16 and internal states 17 to 18 to the parameter table memory 2. Output to. Output latch 4
is the address value 2 output from the address control unit 3
7. Input the read/write control signal 28, the valid flag 29, and the input data value 13 output from the input latch 1, latch it in synchronization with the pipeline clock 11, and set the address value 3 of the data memory 5.
1. Read/write control signal 32 for data memory 5, write data value 33 for data memory 5,
A valid flag 34 and an overflow flag 35 are output to the data memory 5. The data memory 5 is accessed using the address value 31 of the data memory 5 sent from the output latch 4,
Data memory 5 read/write control signal 32
When the value is "1", the write data value 33 of the data memory 5 is written, and when it is "0", the read data value 36, the valid flag 37, and the overflow flag 38 are read from the data memory 5. is output to the next pipeline stage. The valid flag 37 and the valid flag 34 are logically the same. The overflow flag 35 and the overflow flag 35 are logically the same. When the overflow flag 38 is "1", an overflow error occurs and it is impossible to continue the program.

FIG. 2 is a diagram showing an example of field assignment to one word of the parameter table memory 2 in FIG. 1.

In the figure, 51 is an instruction code, 52 is a field A, 53 is a field B, 54 is a field C, 55 is a field D, 56 is a field E,
57 is field F, 58 is field G, 59
- 65 are bases, 66 - 72 are sizes, 73 are activation numbers, 74 are internal states A/B, 75 are internal states R/W, 75 - 85 are counters, and 76 are internal states D/W. The shaded fields are not used.

The parameter table memory 2 in FIG. 1 includes an instruction code 51, field A52, field B53, field C54, field D55,
It is divided into eight fields: field E56, field F57, and field G58. The instruction code 51 stores coded instructions for the address generation circuit of the present invention. Second
In the figure, a 4-bit binary representation is used.

When the instruction code 51 is "0"("0000" in FIG. 2), two input data are queued. This command stores the data that arrived first among the two input data in the data memory 5, and when the other data arrives later, reads the data memory 5 shown in FIG. This command performs queue control to combine data and send it to the next pipeline stage. The address value 27, which is the address of the data memory 5 in FIG. 1, is the sum of the value obtained by doubling the value of the base 59 and the value of the counter 77, modulo the value of the size 66. Further, the address value is incremented by 1, a counter 77 stores the current read address value, and a counter 78 stores the current write address value. The internal state A/B 74 stores the type of data that arrived first among the two input data A and B. If the A data arrived first, "0" is written, and the B data If it arrives first, "1" is written. Internal status R/W7
5 is written with "0" when data is already stored in the data memory 5 in FIG. 1, and "1" is written when no data is stored. Therefore, the read/write control signal 28 in FIG. 1 is generated by the value of the internal state R/W 75 of the internal state A/B 74.

When the instruction code 51 is "1"("0001" in FIG. 2), reading from the data memory 5 in FIG. 1 is performed. The effective read address at this time is
The value obtained by doubling the value of the base 60 and the value of the counter 79 are added together with the value of the size 67 modulo. Also, the read effective address is
The counter 79 is incremented by 1, and the current read address value is stored in the counter 79.

When the instruction code 51 is "2"("0010" in FIG. 2), reading from the data memory 5 in FIG. 1 is performed. The effective read address at this time is the sum of the value of the base 61 of the address multiplied by 32 and the value of the counter 80, modulo the value of size 68. Also, the read effective address is incremented by 1, and the counter 8
The current read address value is stored in 0.

When the instruction code 51 is "3"("0011" in FIG. 2), writing to the data memory 5 in FIG. 1 is performed. The effective write address at this time is
This is the sum of the value obtained by doubling the value of the base 62 of the address and the value of the counter 81, modulo the value of size 69. Further, the effective write address is incremented by 1, and the current write address value is stored in the counter 81.

When the instruction code 51 is "4"("0100" in FIG. 2), writing to the data memory 5 in FIG. 1 is performed. The effective write address at this time is the sum of the value of the base 63 of the address and the value of the counter 82, modulo the value of size 70. Further, the effective write address is incremented by 1, and the current write address value is stored in the counter 82.

When the instruction code 51 is "5"("0101" in FIG. 2), the value of data identification number 12 in FIG. 1 is output as the address value 27 in FIG. 1, and the read/write control signal in FIG. 28 is set to "0" and the data memory 5 in FIG. 1 is read. This instruction has an internal state D/W65, and if this value is "1" and the value of data type number 14 in FIG. 1 is "1", the first
The valid flag USE29 in the figure is set to "1".
When the valid flag USE29 is "1", this data becomes invalid and is discarded in the next pipeline cycle.

When the instruction code 51 is "6"("0110" in FIG. 2), when data whose data type number 14 in FIG. 1 is "0" is input, the stack 84 and the input data value 13 in FIG. The address value 27 in FIG. 1 is generated by the sum of the value obtained by doubling the value of the base 64 of the address, and the data memory 5 in FIG. 1 is read. Stack 84 stores the sum of the value of stack 84 and input data value 13 in FIG. When data whose data type number 14 in FIG. 1 is "1" is input, the stack 84 and address base 60 are
The address value 27 in FIG. 1 is generated by the sum of the multiplied value and the data memory 5 in FIG. 1 is written. "0" is written into the stack 84. The written data does not disappear and flows as is.

When the instruction code 51 is "7"("0111" in FIG. 2), a transition is made. When data whose data type number 14 in FIG. 1 is "0" is input, the value of the stack 85 and the input data value 13 in FIG.
The address value 27 in FIG. 1 is generated by the sum of the value and the value obtained by doubling the value of the base 65 of the address, and the data memory 5 in FIG. 1 is read. “0” is written into the stack 85. Data type number 14 in Figure 1 is “1”
When data is input, the sum of the value of the stack 85 and the input data value 13 in FIG. The written data will not be deleted.
It just flows.

FIG. 3 is a block diagram showing one embodiment of the address control unit 3 in FIG. 1 in detail. In the figure, 101 to 110 are multiplexers, 111 to 1
12 is a magnitude comparator, 113 to 115 are adders, 1
16 is an AND gate, 117 is a programmable logic array, 120 is the most significant bit of the instruction code 26, and multiplexers 101 to 106, 108
~110 is a 2-input, 1-output, multiplexer 107
is a multiplexer with 3 inputs and 1 output. The multiplexer 101 inputs and selects the signal 20 when the most significant bit 120 of the instruction code 26 is "1", and outputs the signal 25 as the selected signal 121 when it is "0". The multiplexer 105 inputs and selects the signal 20 when the signal 120 is "0", and selects the value "0" as the input when the signal 120 is "1".
Output to signal 122. The multiplexer 110 selects the signal 123 as an input when the signal 151 is "0", selects the value "0" as an input when the signal 151 is "1", and outputs the value as the signal 16. Multiplexer 102
selects the signal 24 as an input when the signal 152 is "1", selects the signal 25 as an input when the signal 152 is "0", and outputs it as the signal 124. multiplexer 10
6 selects the value "0" as the input when the signal 120 is "0", selects the signal 24 as the input when the signal 120 is "1", and outputs it as the signal 125. The multiplexer 108 selects the signal 125 as an input when the value 126 of the second bit from the most significant bit of the instruction code 26 is "0", selects the signal 127 as an input when it is "1", and outputs the signal 128. The multiplexer 103 outputs the signal 154 when the signal 153 is “0”.
is selected as an input, and when it is "1", the signal 13 is selected as an input and output as a signal 129. When the signal 153 is "0", the multiplexer 104 selects the signal 155 as an input, and when the signal 153 is "1", selects the signal 13 as an input and outputs the signal 130. Multiplexer 109 has signal 159 “0”
When , the signal 131 is selected as an input, and when it is "1", the value "0" is selected as an input and output as the signal 15. The multiplexer 107 selects the signal 132 as an input when the signal 157 is "0",
When “1”, select signal 13 as input, “2”
When , signal 12 is selected as input and output as signal 27. The magnitude comparator 111 compares the signal 121 and the signal 24, and sets the signal 133 to “1” when they are equal.
otherwise, it is set to "0". The magnitude comparator 112 compares the signal 21 and the signal 124, and sets the signal 134 to "1" when they are equal and "0" when they are not equal. Adder 113 adds signal 135 and signal 128, which are generated with signal 19 as the upper bit and signal 122 as the lower bit, and outputs a signal 132. Adder 114 adds signal 24, signal 129, and signal 136, and adds signal 136 to signal 136.
Output to 1. Adder 115 outputs signal 25 and signal 1
30 and outputs the sum as signal 123, and outputs the carry signal as signal 137.
Gate 116 ANDs signal 137 and signal 120 and outputs the result as signal 136. Programmable logic array 117 has signals 22, 23, 2
6, 14, 133, 134, 39, 40 are input, and output signals 152, 154, 155, 17, 28, 18,
30, 153, 29, 157, 151, 156 are generated. Signals 26, 19, 20, 21, 22,
23, 24, and 25 are fields 51 and 5 of the parameter table memory 2 in FIG. 1, respectively.
These are signals read corresponding to signals 2, 53, 54, 55, 56, 57, and 58, and signals 17, 18,
15, 16 are fields 55, 56, 57, 58
This is the write signal for . The operation in FIG. 3 is as described in the explanation of FIG. 2.

FIG. 4 is a diagram showing an example of input/output logic of the programmable logic array 117 in FIG. 3. In the figure, the input signals are 26, 22, 23,
14, 133, 134, and the output signal is 15
2,154,155,17,28,18,30,
153, 29, 157, 151, 156,
The lines written under the input signal names corresponding to each signal in FIG. A blank space indicates that the input may be low level or high level. When the input conditions are met, the output becomes high level. Since the signal 157 is a 2-bit output, the conditions for taking output values of "1" and "2" are shown. The signal 30 is a signal that becomes "1" when a queue overflow occurs during queue control, and is an error status signal.
Instruction code 26 is shown in 4-bit binary representation.

As explained above, the present invention provides a data flow processing device that performs the functions of waiting control of two input data values, reading and writing data memory, generating numerical sequences, modifying data values, and transitioning in one data memory. The feature is that the amount of hardware can be reduced by dividing the system and controlling its addresses.

Waiting control is one of the important control functions in data flow devices, and the fact that the functions of generating numerical sequences, modifying data values, and transitioning can be realized with one pipeline clock greatly contributes to improving the execution efficiency of calculations. . Reading and writing data memory are the basic functions necessary for table pickup processing and buffering, and these functions are
The fact that this could be achieved by sharing two data memories and simply switching their addresses helped improve the regularity of the hardware, reducing the circuit size and increasing performance.

[Brief explanation of drawings]

FIG. 1 is a system block diagram of the address generation circuit of the present invention, FIG. 2 is a diagram showing an example of field assignment to one word of the parameter table memory 2 in FIG. 1, and FIG. 3 is an address control diagram in FIG. 1. FIG. 4 is a block diagram showing a detailed embodiment of section 3, and FIG. 4 is a diagram showing an example of input/output logic of programmable logic array 117 in FIG. In the figure, 1 is an input latch, 2 is a parameter table memory, 3 is an address control section, 4 is an output latch, 5 is a data memory, 101 to 110 are multiplexers, 111 to 112 are comparators, 113
115 is an adder, 116 is a gate, and 117 is a programmable logic array.

Claims (1)

[Claims] 1 In the address generation circuit for the data memory of the data flow processing device, a parameter table memory that stores the instruction type, address base, size, internal state, and address count, and is accessed using the data identification number in the input data value as an address. Then, input the type of instruction, address base, size, internal state, address count, and input data value, and input control signals for data value waiting, data memory reading, writing, and passing, and the data memory address. and an address control unit that generates the address of the data memory by adding the base value and the address count value modulo the size, and divides the external data memory into a plurality of areas. Then, by using the start address as the base for each area, securing the size for each area, cyclically scanning each area, and storing the operand that arrived first, it is possible to wait for the arrival of both operands of a binary operation. , an address generation circuit characterized in that operands that arrive later can be sent to the next pipeline stage at the same time as they arrive.