JPH0446408B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a liquid crystal device, and particularly to a liquid crystal device for driving and controlling a display element whose threshold value is highly dependent on temperature. [Conventional example] Twisted using conventional Nematic liquid crystal
Nematic type or DSM type, as well as
The operating temperature range of the Cholesteric-Nematic phase transition type Gest-Host liquid crystal display element has expanded dramatically with the advancement of technology, and the problem of temperature compensation has been successfully reduced considerably. However, in the case of a ferroelectric liquid crystal element, the temperature dependence of the threshold value is large, as shown in FIG. Conventionally, when driving a ferroelectric liquid crystal element with such characteristics, the only option was to control the temperature of the cell itself, which resulted in a large device.
The situation was such that power consumption, etc., could not be ignored. [Objective] The object of the present invention is to eliminate the drawbacks of the above-mentioned conventional examples and to provide a liquid crystal device that performs drive control for displaying a temperature-dependent display element without using equipment such as a temperature controller. It is in. [Summary of the Invention] The present invention provides: a. A pair of electrodes disposed at a distance, and a pair of electrodes disposed between the pair of electrodes, which are arranged in either one orientation state or the other orientation state depending on the polarity of the applied voltage. a liquid crystal panel having a ferroelectric liquid crystal that produces an oriented state; b a driving means for applying one polarity voltage or the other polarity voltage between the pair of electrodes; c temperature detection for detecting the temperature of the liquid crystal panel and outputting temperature data. means, d an analog-to-digital converter for converting the temperature data into digital data; a memory for storing the temperature data converted to digital data;
The pulse width table is stored in the memory and determines the pulse width of the one polarity voltage or the other polarity voltage depending on the temperature, and the pulse width table is compared with the temperature data converted to the digital data. a pulse width selection means for outputting pulse width data according to the temperature of the liquid crystal panel; A feature of the liquid crystal device is that the liquid crystal device includes a control means for starting application of a voltage or a voltage of the other polarity between the pair of electrodes in response to a write command signal instructing the start of the application. [Example] In the display driving device of this example, the ferroelectric liquid crystal used as a display element whose threshold value is highly temperature dependent has a first optical stable state and a second optical stable state depending on the applied electric field. A substance that is in either a physically stable state, that is, a bistable state with respect to an electric field, and in particular a liquid crystal having such properties, is used. As the ferroelectric liquid crystal having bistability used in this example, chiral smectic liquid crystal having ferroelectricity is most preferable, and among these, chiral smectic liquid crystal having C phase (SmC*) or H phase (SmH
*) LCDs are suitable. Regarding this ferroelectric liquid crystal, please refer to “LE LOURNAL DE PHYSIOUE”.
LETTERS” 36 (L-69) 1975. “Ferroelectric
“Liquid Crystals”; “Applied physics Letters”
36 (11) 1980, “Submicro Second Bistable
Electrooptic Switching in Liquid Crystals”;
It is described in "Solid State Physics" 16 (141) 1981 "Liquid Crystal", etc., and the ferroelectric liquid crystal disclosed in these can be used in this embodiment. More specifically, examples of the ferroelectric liquid crystal compounds used in this example include decyloxybenzylidene-P'-amino-2-methylbutylcinnamate (DOBAMBC), hexyloxybenzylidene-P'-amino- 2-chloropropyl cinnamate (HOBACPC) and 4-O-(2-methyl)
-butylresolcylidene-4'-octylaniline (MBRA8) and the like. When constructing an element using these materials, the liquid crystal compound changes depending on the temperature. For example, in the case of DOBAMBC, the phase transition is from an isotropic phase to a smectic A phase at about 117°C and to a chiral smectic C phase at about 93°C. This chiral smectic C phase exhibits ferroelectricity, but at about 61° C. it transitions to a lower phase. There are documents that say that the phase below the chiral smectic C phase is the chiral smectic I phase, the chiral smectic F phase, or the chiral smectic H phase, but in any case, the phase is It has also been confirmed that ferroelectricity is exhibited in . The transition temperature from the smectic A phase to the chiral smectic C phase is the Curie point. Below this Curie point, DOBAMBC has its molecular dipoles aligned and has spontaneous polarization.
It is known that its physical properties vary considerably depending on temperature. For example, if we define the tilt angle θ as the angle between the liquid crystal molecules and the normal to the layer (the layer is the same as the definition for the smectic phase), θ tends to increase as the temperature decreases below the Curie point. . The spontaneous polarization value Ps also has a dependence on temperature. It has been confirmed that (increases as the temperature decreases). It is known that the elastic constant and viscosity coefficient are also a function of temperature, and the response speed (response of the molecular dipole to an external electric field) and the critical electric field required to unwind the helical pitch also differ. These are known to vary widely in different phases, but within the same phase (for example, within the chiral smectic C phase, the
Even in the temperature range of These problems are not limited to DOBAMBC but are common to so-called ferroelectric liquid crystals. Moreover, these phenomena are the same even in a thin gap where bistability occurs (for example, 1 μm to 2 μm), and appear as a change in the threshold value for switching between two stable states. We have discovered that the switching threshold is not simply given by the DC peak value, but is given by the pulse width and the peak value. Therefore, in such a case, the gist of the present invention is to compensate for the temperature change by changing the pulse width of the display drive signal. The arrangement of ferroelectric liquid crystals within a cell will be explained below. In this embodiment, a cell substrate coated with polyimide resin and subjected to a rubbing treatment is used. FIG. 7 schematically depicts an example of a ferroelectric liquid crystal cell. 1 and 1′ are In ₂ O ₃ , SnO ₂ and
A substrate (glass plate) coated with a transparent electrode such as ITO (Indium-Tin Oxide), between which a liquid crystal molecular layer 2 is oriented perpendicular to the glass surface.
SmC* phase liquid crystal is sealed. A thick line 3 represents a liquid crystal molecule, and this liquid crystal molecule 3 has a dipole moment (P⊥) 4 in a direction perpendicular to the molecule. When a voltage other than a certain threshold value is applied between the electrodes on the substrates 1 and 1', the helical structure of the liquid crystal molecules 3 is unraveled, and the liquid crystal molecules 3 are aligned so that all dipole moments (P⊥) 4 are directed in the direction of the electric field. Can change direction. The liquid crystal molecules 3 have an elongated shape and exhibit refractive index anisotropy in the long axis direction and the short axis direction. Therefore, for example, if polarizers are placed above and below the glass surface in a crossed nicol positional relationship with each other, polarizers can be placed above and below the glass surface. For example, a liquid crystal optical modulation element whose optical properties change depending on the polarity of applied voltage is
easily understood. Furthermore, when the thickness of the liquid crystal cell is made sufficiently thin (for example, 1μ), the helical structure of the liquid crystal molecules unwinds (non-helical structure) even when no electric field is applied, as shown in Figure 8, and its bipolar structure The child moment P or P' is either upward (4a) or downward (4b). As shown in FIG. 8, when an electric field E or E' of different polarity above a certain threshold value is applied to the cell for a predetermined period of time, the dipole moment will be directed upward 4a or 4a corresponding to the electric field vector of the electric field E or E'. The orientation is changed from the downward direction 4b, and accordingly the liquid crystal molecules are aligned in either the first alignment state 5 or the second alignment state 5'. There are two advantages to using such a ferroelectric liquid crystal as an optical modulation element. Firstly, the response speed is extremely fast, and secondly, the alignment of liquid crystal molecules has a bistable state. The second point will be explained with reference to FIG. 8, for example. When the electric field E is applied, the liquid crystal molecules are aligned in the first alignment state 5, and this state remains stable even when the electric field is turned off. Further, when an electric field E' in the opposite direction is applied, the liquid crystal molecules are aligned to the second alignment state 5' and the orientation of the molecules is changed, but they remain in this state even after the electric field is turned off. or,
As long as the applied electric field E does not exceed a certain threshold value, each orientation state is maintained. In order to effectively realize such fast response speed and bistability, it is preferable for the cell to be as thin as possible, and in general, 0.5μ to 20μ, especially 1μ to 5μ is suitable. . A liquid crystal-electro-optical device having a matrix electrode structure using this type of ferroelectric liquid crystal is disclosed in US Pat.
It is proposed in the specification of No. 4367924. Hereinafter, drive control of the ferroelectric liquid crystal in this embodiment will be explained in detail with reference to the drawings. First, FIG. 1 is a block diagram showing the overall configuration of a ferroelectric liquid crystal driving device according to this embodiment. In Figure 1, 10 is a one-chip microcomputer with a built-in A/D converter for control (hereinafter referred to as
The CPU 10 is composed of computer peripherals such as an A/D converter, RAM, and ROM. Reference numeral 11 denotes a keyboard for inputting character information or a character information input section of an external device to which character information is sent in a predetermined mode. 12 is an external RAM for storing character information displayed on the liquid crystal display, which is a display character memory. 13 is a driver section that drives the ferroelectric liquid crystal. 14 is a ferroelectric liquid crystal display section. Also, although not shown, the power supply for the CPU and the power supply for driving the ferroelectric liquid crystal are separate power supplies, and the main power supply is also not shown.
When the SW is turned on, power is supplied to the CPU and then to the ferroelectric liquid crystal drive in that order. FIG. 3 is a block diagram showing the configuration of the driver section 13. Reference numeral 13-1 is an address driver that determines the addresses of drivers 13-3 and 13-4 of the ferroelectric liquid crystal display 14. A column data circuit 13-2 outputs column data, which is image dot data, to the driver 13-3. The column data is CPU1
0 is output to the column data circuit 13-2. Next, FIGS. 4a, b, and c are diagrams showing memory maps of ROM and RAM, which are internal memories of the CPU 10. FIG. 4d shows a memory map of the display character memory 12. Figures 5a, b, and 6 are in this example.
This is a flowchart diagram showing the control operation of the CPU 10, which will be described below with reference to FIGS. 5a and 5b and FIG. 6. First, in step 501 of FIG. 5a, as the power (not shown) is turned on, the I/O port and internal
The RAM and display character memory 12 are initialized, and the memory areas shown in FIG. 4b, c, and d are cleared and initialized. Next, in step 502, the 8-channel (input) 8-bit A/D converter built into the CPU is activated. By the way, in the CPU 10 of this embodiment, there are four registers that automatically hold the results after A/D conversion, and the number of channels that are automatically held after A/D conversion is four, so for example, An0
~An3 and An4~An7 must be processed in software. Therefore, step502
First, A/D conversion of An0 to An3 is activated. Furthermore, since an interrupt occurs in this A/D conversion every four channels of conversion, the A/D interrupt is enabled in step 503. Next, although the explanation on the drawings is a little off topic, since the operation is continuous, we will now explain the A/D interrupt processing routine in FIG. 6. An A/D interrupt occurs every 200 μs, and the process shifts to the flowchart shown in FIG. Then, in step 601 of Fig. 6, the A/D converted channels are An0 to An3 or An4.
~Determine whether it is An7. If it is the first time, An0 to An specified in step 502 in Figure 5a.
Since there are 3 channels, the decision is yes and the 6th
Proceed to figure step 602. The A/D conversion results of An0 to An3 held in step 602 are transferred to memory areas ADR0 to ADR3 of the internal RAM shown in FIG. 4c. Next, in step 603, A/D conversion of An4 to An7 is started, and in step 604, A/D conversion is started.
Enable interrupts, execute a return instruction in step 605, and increment the value of the program counter before the interrupt occurs. In other words, the routine shown in FIG. 5 continues processing continuously. Also, the judgment in step 601 of Figure 6 is No.
, that is, an even-numbered interrupt occurs.
4 to An7 were selected. At this time, proceed to step 606, and the held An4 to An
Figure 4c shows the A/D conversion results of 7 in the internal RAM.
to the memory areas ADR4 to ADR7. Through these processes, all the temperature information of each point of the ferroelectric liquid crystal panel is retained in the memory areas ADR0 to ADR7 of the internal RAM shown in Figure 4c, and subsequent processing using the temperature information is possible. Become. Therefore, in step 607, in order to notify this, the A/D conversion completion flag (ADEF) of initial An0 to An7 of bit 0 of address 0 in the internal RAM shown in FIG. 4B is set to 1. Next, in step 608, A/D conversion of An0 to An3 is started, and each process of step 604 and step 605 is performed. Since these steps are repeated as long as the power for the CPU is turned on, the inside of Fig. 4c is
New temperature information is always held in memory areas ADR0 to ADR7 of the RAM. Next, we return to the explanation of FIG. 5a. First, Figure 5a
In step504, the fourth
The ADEF assigned to address 0, bit 0 of the internal RAM in FIG. b is checked, and the check is repeated until the flag is set. Then, by setting the flag, the process proceeds to the next step.
In step 505, the screen clear flag (CLF) assigned to address 0, bit 2 of the internal RAM in Fig. 4b is set, and in step 506, the clear flag (CLF) in Fig. 4b is set.
Sets the write flag (WRF) assigned to address 0, bit 1 of the internal RAM. By setting these two flags, the ferroelectric liquid crystal display element is initialized by a process described later. Next, between step 507 and step 512, the fourth
The contents of the external RAM display and character memory 12 shown in FIG. d are rewritten. In other words, in step 507 of Fig. 5a, the system waits until it receives a request from the keyboard or external device shown in Fig. 1 and starts inputting character information in a predetermined type, or receives a request to initialize the screen in steps 505 and 506. It is something. Therefore, if there is a request including the set state of the write flag of the internal RAM of FIG. 4b, address 0, bit 1, the process advances to the next step. In step 508, the screen clear flag (CLF) at address 0, bit 2 in the internal RAM shown in Figure 4b is checked, and if the CFL is set, the value 0 is stored in step 509 to clear the character information. ,the above
If CFL is not set, the process advances to step 510 while retaining the character information input in the predetermined type. In step 510, the column address data (ACD) of the ferroelectric liquid crystal matrix shown in FIG. 4c, which is the address data of the character data, and the row address data (ARD) of the ferroelectric liquid crystal matrix
is added, and in step 511, the character data is stored in the display character memory 12 at address ACD+ARD. Note that address data is expressed in hexadecimal notation. Next, in step 512, it is checked whether the address obtained by adding ACC + ARD is the end address 9C3 (9C3 = 2500, which corresponds to 50 characters x 50 characters) of the display character memory 12. If it is the end address, proceed to step 517, and the end address Otherwise, proceed to step 513. In step 513, add 1 to ACD, and in step 514, check whether input of character data has been completed for 50 characters by checking whether ACD is 32. If ACD is 32,
Proceed to step 515, and if ACD is not 32, return to step 507 to input character data. Clear ACD to 0 in step 515, step 516
Add 32 to ARD and return to step 507. After entering the character data for one screen of the ferroelectric liquid crystal display 14, proceed from step 512 to step 517.
Proceed to step 517 to ACD and step 518 to ARD
Clear to 0. This is to return the value to the top address for use as a reference address in the display character memory 12 of the external RAM (FIG. 4d) when writing in subsequent steps. Next, in step 519, to find the average temperature,
The peripheral temperature data of the ferroelectric liquid crystal display 14 is processed using ADR0 to ARD7 of the internal RAM shown in Fig. 4c, and the resulting average temperature data is stored in the memory area PD of the internal RAM shown in Fig. 4c. do. Also, in step 520, based on the average temperature data obtained in step 519 above, the internal temperature shown in Figure 4 a is
ΔT assigned to RAM address 800 to BFF
The time data for ΔT is extracted by referring to the timer code for
Store in. This temperature → ΔT conversion is performed with reference to the characteristic diagram showing the driving frequency and driving voltage at each temperature of the ferroelectric liquid crystal shown in Figure 2.A typical conversion example shown in Figure 2 is shown in Tube-1 below. Shown below.
This example is a conversion example when the drive voltage is constant at 70V. Also, the resolution of temperature detection is 0°C to 100°C.
Approximately 0.4
℃, and the resolution of the drive signal pulse width ΔT is
It is 1μsec, and the range is 1μsec ~
It can cover up to 65.5msec. next
In step 521, the character information is transferred from the address of the display character memory 12 of the external RAM shown in FIG.
Convert to the specified code while referring to the character code assigned to FFF. Next, in step 522, the above specified code is
10 is converted into column data, which is dot data, by the built-in glitter generator.
In step 523, the address data of ACD + ARD and the above column data are transferred to the address coder 1 in Figure 3.
3-1 and the column data circuit 13-2. Here, it is output to address decoder 13-1.
The address data of ACD+ARD is converted by the address decoder 13-1 into address data corresponding to column data. In other words, one character's worth of dots is composed of 32 x 32 dots, and the above
The address data of ACD + ARD is converted into dot row address data (ARD') and dot column address data (ARD'), which are address data of dots on the ferroelectric liquid crystal display 14 corresponding to the address of the display character memory 12, and ' is output to the driver 13-3, and ARD' is output to the driver 13-4. In addition, display 14
is composed of 8 dots/mm in both the vertical and horizontal directions. Next, in step 524, the write command pulse is
The CPU 10 outputs the address to the address decoder 13-1. The write command pulse is in step 520 above.
The pulse width of the ΔT time is set by the CPU 10 based on the time data stored in the ΔT. The address decoder 13-1 outputs a write signal having a pulse width of ΔT time to the drivers 13-3 and 13-4 in accordance with the write command pulse,
Write character data. Next, in step 525 of FIG. 5b, it is determined whether one character of column data has been written,
If one character has not been written yet, step 524
Returns to and outputs a write command pulse to the address decoder 13-1, and continues until writing of one character is completed.
Proceed to step 526. The judgment as to whether writing of one character is completed in step 525 above is made by the address decoder when the writing of column data for one character is completed.
This is done by checking the write end signal output to the write end signal. Next, in steps 526 to 530, the above
Like step512 to step516, it is address data.
Increment ACD and ARD. In this way, steps 519 to 530 are repeated until all the characters on one screen are written to the ferroelectric liquid crystal display 14, and when all the characters have been written, step 526
Proceed to step 531. In step 531, reset CLF, and in step 532
Reset WRF in step 533 and step 534.
The ACD and ARD are each cleared to 0, and the process returns to step 507 to wait until the next request is received. As described above, this embodiment detects the screen temperature of the ferroelectric liquid crystal display 14 and performs drive control by changing the pulse width of the write signal according to the temperature, so it is not necessary to use an external device such as a heater for temperature control. It is possible to simplify the equipment and reduce costs. Further, as an application of the present embodiment described above, it is also possible to divide the ferroelectric liquid crystal display into a plurality of blocks, detect the average temperature of each block, and perform drive control by changing the pulse width according to the average temperature. Therefore, as another embodiment, drive control of a ferroelectric liquid crystal based on the average temperature of each block will be described below. The overall configuration is the same as that of the present embodiment shown in FIGS. 1 and 3. The difference from this example is that the average temperature data of PDAn0 to An7 in FIG.
average temperature data), BPD3 (An0, An1, An
2 average temperature data), BPD4 (An2, An3,
An4 average temperature data), and the display character memory in Figure 4 d is shown in Figure 9 b.
It is divided into four blocks: BPD1, BPD2, BPD3, and BPD4. 10a and 10b are flowcharts showing the control operation of the CPU 10 when the ferroelectric liquid crystal display is divided into a plurality of blocks and the pulse width is changed according to the average temperature of each block to drive and control the ferroelectric liquid crystal display. It is a diagram. Step'510~step'518 is from step501~a in Figure 5a.
Since it is the same as up to step 518, the explanation will be omitted.
Also in the A/D conversion interrupt routine shown in FIG. 6 and in other embodiments, interrupts occur in units of 200 μs. In step'519, ADR of the internal RAM in Fig. 9a
Average value of temperature data of 0, ADR6, ADR7
Store it in BPD1 and in step'520, the inside of Figure 9 a
The average value of temperature data of ADR4, ARD5, and ADR6 of RAM is stored in BPD2, and the 9th temperature data is stored in step'521.
Store the average value of temperature data of ADR0, ADR1, and ADR2 of internal RAM in figure a to BPD3, and step'522
ADR2, ADR of the internal RAM in Figure 9a
3. Store the average value of temperature data of ADR4 to BPD4. Next, in step'523, the character data is set from the address data of ARD and ACD to the above BPD1~
Select which block of BPD4 it resides in,
In step '524, the average temperature data of the block in which character data exists is converted into time data and stored in ΔT, as in the case of this embodiment. The steps from step'525 to step'538 below are shown in Figure 5 a and b.
The same steps as steps 521 to 534 are performed, and the pulse width of the write signal is changed according to the average temperature data of the block, and the drive control of the ferroelectric liquid crystal display is performed. In this way, since the drive of the ferroelectric liquid crystal display is controlled by changing the pulse width of the write signal in accordance with the temperature data averaged for each predetermined region of the display surface, a display drive device with higher precision can be provided. In this example, a display element using a ferroelectric liquid crystal was explained as an example, but the switching threshold value is temperature dependent, and the pulse width of the write drive signal contributes to switching. are all applicable. [Effect] As explained above, the present invention eliminates the need for temperature control using a heater or the like when driving a display element whose threshold value is highly dependent on temperature.
Furthermore, since there is no need to change the voltage of the drive signal, the device can be simplified and costs can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of this embodiment. FIG. 2 is a characteristic diagram showing the driving frequency and driving voltage of the ferroelectric liquid crystal at each temperature shown. FIG. 3 is a detailed block diagram of the tribar section 13 of the ferroelectric liquid crystal. Figure 4 a, b, c are
3 is a diagram showing a memory map of internal ROM and RAM of the CPU 10. FIG. FIG. 4d is a diagram showing the display character memory 12. FIGS. 5a and 5b are flowcharts showing the control of the CPU 10 of this embodiment. FIG. 6 is a diagram showing an A/D conversion interrupt processing routine. 7 and 8 are conceptual diagrams of a ferroelectric liquid crystal. Figure 9a shows another embodiment.
3 is a diagram showing the memory contents of internal RAM of the CPU 10. FIG. FIG. 9b is a diagram showing a display character memory according to another embodiment. FIGS. 10a and 10b are flowcharts showing the control of the CPU 10 in another embodiment. 10 is a CPU, 11 is a character information input section, 12 is a display character memory, 13 is a driver section, 14 is a ferroelectric liquid crystal display, AN0
~AN7 is A/D conversion channel, Th1~Th8
is a temperature sensor.

Claims (1)

[Scope of Claims] 1 a A pair of electrodes arranged at a distance, and an orientation state of either one orientation state or the other orientation state, which is arranged between the pair of electrodes, depending on the polarity of the applied voltage. a liquid crystal panel having a ferroelectric liquid crystal that produces a ferroelectric liquid crystal, b. a driving means for applying one polarity voltage or the other polarity voltage between the pair of electrodes, c. a temperature detection means for detecting the temperature of the liquid crystal panel and outputting temperature data; d an analog-to-digital converter that converts the temperature data into digital data; a memory that stores the temperature data converted to digital data;
The pulse width table is stored in the memory and determines the pulse width of the one polarity voltage or the other polarity voltage depending on the temperature, and the pulse width table is compared with the temperature data converted to the digital data. a pulse width selection means for outputting pulse width data according to the temperature of the liquid crystal panel, and e. said one polarity having a pulse width changed according to the pulse width data output from said pulse width selection means A liquid crystal device comprising a control means for starting application of a voltage or a voltage of the other polarity between the pair of electrodes in response to a write command signal instructing the start of the application.