JPH0447503B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to an AD system in an engine control system.
This invention relates to a method of transmitting converted data.

[Conventional technology]

In an engine control system using an electronic control unit, the analog output of sensors placed in various parts of the engine is converted into AD and input to a processor (CPU).
The processor generates various signals using the input digital data and performs control, display, etc. There are various types of A/D (analog/digital) conversion, but for example, a successive approximation type is used. In this successive approximation type A/D converter, the conversion data obtained sequentially from the upper bit by successive approximation is used. The data is stored in a register and serially transmitted to the processor upon completion of conversion.

Figure 5 is a diagram explaining this.
The clock CLK is sent to the AD converter, and the AD converter shifts the above register with the clock to 1
Register data is serially transmitted through the main data line. The data line is initially at H (high) level, and becomes L (low) level at the start of transmission. This first 1 bit (LSB) at L level is a start bit, followed by a predetermined number of data bits, for example 8, and then returns to H level again (this H level becomes a stop bit). The processor takes in this data on the clock CLK. That is, data lines H and L are clock CLK.
The processor is synchronized with the falling edge of H,
Read L at the rising edge of CLK, 010110010 as shown.
etc. The first LSB is a start bit, not data, and the remaining 8 bits are data (register contents). Since the number of bits of serially transmitted data is known, the data reception completion flag goes up when this known number of bits is received (the first bit is not captured, so 8 bits are received), and this causes an interrupt to be received. Data processing takes place.

AD conversion requests are periodically sent from the processor to the AD converter at a cycle of, for example, 4 mS. In response to this, the AD converter starts AD conversion, performs the above-mentioned data transmission upon completion of conversion, and enters a standby state upon completion of transmission. The time required for AD conversion and transmission of converted data is, for example, 500 μS, and the remaining 3500 μS is a waiting period. The above AD conversion request is executed by the processor.
It is output by setting the signal line ₁ (see Figure 2) stretched between the SOUT terminal and the SIN terminal of the AD converter to L level, and the AD converter monitors the potential of this signal line. When it becomes L level, it is interpreted as an AD conversion request and its execution begins. AD converted data is serially transmitted through a signal line ₂ extending between the SO terminal of the AD converter and the SIN terminal of the processor.

[Problem that the invention seeks to solve]

This signal line ₂ is normally at H level, and when it goes to L level, transmission begins, and the first L level is a start bit. The processor monitors the level of this signal line ₂ , and the H level is the L level.
If the level changes, it will be treated as a start bit and data will be received by mistake. Of course, this received data is noise, and if it disappears quickly, it will be at the steady state H level, but the receiving operation will continue anyway.

The present invention improves these points, and the processor
The purpose is to receive only the converted data and not receive anything else.

[Means for solving problems]

The present invention includes a microcomputer 10 and an AD converter 20, and
Requests AD conversion to the AD converter, and the AD converter
The AD conversion data is serially transmitted after the first L level bit, and the microcomputer determines the first L level as the start of the serial transmission and receives the following data. In the transmission method of AD conversion data in the engine control system, the processor (CPU) of the microcomputer takes in the data, and sets a start bit flag (SBF) that is set when the AD conversion request occurs and is reset when the data is taken in by the interrupt. ), and the processor is characterized in that it takes in the data in a state in which the interrupt is raised and the flag is set.

[Effect]

According to this method, the processor can only take in AD converted data and avoid erroneous data taking in due to noise, etc., and is extremely effective for use in noisy engine control systems.

〔Example〕

In FIG. 1, a microcomputer 10 includes a processor CPU, a reception register 12, a reception end detection circuit 14, a clock control circuit 16, and a clock selector 18. Also, 20 is an AD converter, which has selection data for analog input channels a, b, ...
It includes a CD latch circuit 22, a multiplexer 24 for selection, a successive approximation register 26, a digital-to-analog converter 28, a regulator 30 for receiving a power supply voltage Vc.c. and generating a reference voltage V _REF , etc., and a group of comparators 32.

Successive approximation type AD conversion operation is well known, and assuming that the input analog voltage is maximum V volts, the initial
The MSB of SAR is set to 1 and the rest are set to 0. In response, the DAC outputs V/2, and if MPX24 selects input (channel) a, the comparator 3
In 2a, a is compared with V/2, and a>V/2
Then, in SAR, the next bit of MSB is set to 1, and in response to this, DAC28 generates 3V/4, which is compared with a. Each bit of the value is set sequentially starting from the MSB side (although there are various types of operations).

AD conversion operation is instructed by signal line ₁ . That is, as shown in FIG. 2, when ₁ goes to L level, this is a start bit and the AD conversion operation starts. Before this, the data CD specifying the conversion channel has been given from the microcomputer 10 side, so this data is applied to the latch 22 by the start bit.
This causes the multiplexer 24 to select channels a, b, . . . indicated by the data. When the AD conversion operation is eventually completed and all the converted data is accumulated in the SAR 26, its transmission automatically starts. As mentioned above, the level of the signal line ₂ for serial transmission is always at H level, and becomes L level at the start of transmission. This (LSB) is the start bit, and the register data continues thereafter.

A clock CLK for this serial transmission is sent from the microcomputer 10 through a route between a clock selector 18 and a clock control circuit 16. This clock SLK is also input to the reception register 12 to control the acquisition of serial transmission data, and also to the detection circuit 12.
4 is also input to detect the end of reception. That is, this detection circuit 14 is essentially a counter, and when it counts the known number of data bits (8 in this example), it signals the end of reception to the register 12 and processor.
Inform the CPU. For register 12, this is the shift-in stop signal, and also for the processor.
This becomes an interrupt signal for the CPU, and data of the received data 12 is taken in. The start bit on the signal line ₂ is detected by the reception register 12, starts shift-in, and instructs the detection circuit 14 to start counting.

When the signal line ₂ becomes low level due to noise after the serial transmission is completed, the microcomputer side regards this as the start bit of the serial transmission and malfunctions. Therefore, in the present invention, a start bit flag SBF is provided in the processor CPU, and after the serial transmission is completed and the interrupt signal is output, it is set to L level until the next AD conversion (in the above example).
(Until after 3500μS) Keep this at L. processor
In the CPU, an interrupt is received from the reception end detection circuit 14,
When fetching data from the reception register 12, the start bit flag is checked. If it is H, data is fetched, but if it is L, data is not fetched.
In this way, even if the signal line ₂ goes low due to noise, this will not be mistaken as the LSB of serial transmission and the received data will not be taken in.

The start bit flag SBF is set at the timing of AD conversion (every 4 mS in this example), and reset at the data capture interrupt to the processor after serial transmission is completed. FIG. 3 shows the procedure for setting the start bit flag SBF, and FIG. 4 shows the procedure for resetting it. As shown in Figure 3, SBF is set at the start of AD conversion ( ₁ is low), and as shown in Figure 4, SBF is set.
It is reset when AD conversion data is saved to the processor's RAM (random access memory).

AD conversion channel set in FIG. 3 is a step for generating the data CD. There are various types of sensors, and the timing of AD conversion varies, such as those with short cycles and those with long cycles. In this step, it is decided which sensor (channel) will be targeted for AD conversion. The routine of FIG. 4 starts when the interrupt raised by the reception end detection circuit 14 is received.

〔Effect of the invention〕

As explained above, according to the present invention, the processor can capture only AD conversion data and avoid erroneous data capture due to noise, etc., and is extremely effective for use in noisy engine control systems.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart for explaining the operation, FIGS. 3 and 4 are flow charts showing the processing procedure, and FIG.
The figure is a time chart explaining the operation of the conventional device.

Claims (1)

[Claims] 1. Microcomputer 10 and AD converter 20
The microcomputer requests the AD converter to perform AD conversion, and the AD converter serially transmits the AD conversion data after the first L level bit.
A method for transmitting AD-converted data in an engine control system, in which the level is determined to be the start of the serial transmission, the following data is received, and an interrupt generated at the end of reception causes the microcomputer's processor (CPU) to take in the data. A start bit flag (SBF) is provided which is set when the AD conversion request occurs and is reset when data is fetched by the interrupt, and the processor executes the start bit flag (SBF) when the interrupt occurs and the flag is set. A method of transmitting AD conversion data characterized by importing data.