JPH044794B2 - - Google Patents
Info
- Publication number
- JPH044794B2 JPH044794B2 JP31500486A JP31500486A JPH044794B2 JP H044794 B2 JPH044794 B2 JP H044794B2 JP 31500486 A JP31500486 A JP 31500486A JP 31500486 A JP31500486 A JP 31500486A JP H044794 B2 JPH044794 B2 JP H044794B2
- Authority
- JP
- Japan
- Prior art keywords
- vertical deflection
- circuit
- feedback circuit
- zener diode
- smoothing capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000003990 capacitor Substances 0.000 claims description 12
- 238000009499 grossing Methods 0.000 claims description 9
- 230000001360 synchronised effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000002411 adverse Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Landscapes
- Details Of Television Scanning (AREA)
Description
【発明の詳細な説明】
〔概要〕
直流帰還回路を持つ垂直偏向回路において、直
流帰還回路を構成する平滑コンデンサを、容量を
減少することなく短時間に充電できるように構成
することによつて、垂直偏向回路の立上がり時間
を短縮した。[Detailed Description of the Invention] [Summary] In a vertical deflection circuit having a DC feedback circuit, by configuring a smoothing capacitor that constitutes the DC feedback circuit so that it can be charged in a short time without reducing its capacity, The rise time of the vertical deflection circuit has been shortened.
この発明はCRT表示装置に設けられる垂直偏
向回路に関するものである。
The present invention relates to a vertical deflection circuit provided in a CRT display device.
垂直偏向回路は垂直同期信号に同期したのこぎ
り波電圧から垂直偏向電流を生成する装置である
が、特に図形表示装置に用いるものにおいては、
表示図形の歪を減少することが非常に重要視され
ている。 A vertical deflection circuit is a device that generates a vertical deflection current from a sawtooth voltage synchronized with a vertical synchronization signal, but it is especially used in graphic display devices.
Great importance is placed on reducing distortion of displayed graphics.
従来例の構成図を第３図に示す。図において、
１は電圧増幅部１１と電流増幅部１２とからな
る増幅回路、
２は抵抗Ｒ１と同Ｒ２とコンデンサＣ１とから
なる直流帰還回路、
４は垂直偏向コイル（Lv）、また５は交流帰還
回路である。
A configuration diagram of a conventional example is shown in FIG. In the figure, 1 is an amplifier circuit consisting of a voltage amplifying section 11 and a current amplifying section 12, 2 is a DC feedback circuit consisting of resistors R1 and R2, and a capacitor C1, 4 is a vertical deflection coil (Lv), and 5 is an AC This is a feedback circuit.
上記構成の垂直偏向回路では、電源投入の際、
直流帰還回路２に含まれる平滑用コンデンサＣ１
の充電が終わり、この部分の電圧Vfが所定の値
に達するまで、約0.5〜１秒の間は垂直偏向がお
こなわれないという問題点がある。
In the vertical deflection circuit with the above configuration, when the power is turned on,
Smoothing capacitor C1 included in DC feedback circuit 2
There is a problem in that vertical deflection is not performed for about 0.5 to 1 second until the voltage Vf in this part reaches a predetermined value after charging is completed.
なお、この時間を短縮するには抵抗Ｒ１とコン
デンサＣ１とによつて定まる時定数の値を減らす
ことも考えられるが、望ましい帰還信号を得るう
えで好ましくない。 Note that in order to shorten this time, it is possible to reduce the value of the time constant determined by the resistor R1 and the capacitor C1, but this is not preferable in terms of obtaining a desired feedback signal.
すなわち本発明の目的は、直流帰還回路の時定
数を減少することなく、電源投入の際の立上がり
時間を短縮することにある。 That is, an object of the present invention is to shorten the rise time when power is turned on without reducing the time constant of the DC feedback circuit.
本発明による垂直偏向回路は、第１図の原理図
に示すように、
垂直同期信号に同期するのこぎり波を増幅して
垂直偏向コイルに供給する電流を生成する増幅回
路１と、
垂直偏向コイル側から前記のこぎり波の入力側
に直流信号を帰還する直流帰還回路２と、
直流帰還回路２を構成する平滑用コンデンサの
高電位側から正電源Va側に対し順方向に接続さ
れるツエナーダイオード３とによつて構成したも
のである。
As shown in the principle diagram of FIG. 1, the vertical deflection circuit according to the present invention includes an amplifier circuit 1 that amplifies a sawtooth wave synchronized with a vertical synchronization signal and generates a current to be supplied to the vertical deflection coil, and a vertical deflection coil side. A DC feedback circuit 2 that returns a DC signal from the input side of the sawtooth wave to the input side of the sawtooth wave, and a Zener diode 3 that is connected in a forward direction from the high potential side of the smoothing capacitor constituting the DC feedback circuit 2 to the positive power supply Va side. It was constructed by
直流帰還回路２に設けられている平滑用コンデ
ンサの充電を、ツエナーダイオード３を介し、そ
の降伏電圧に達するまで別の電源を利用しておこ
なうものである。
The smoothing capacitor provided in the DC feedback circuit 2 is charged via a Zener diode 3 using another power source until its breakdown voltage is reached.
第２に実施例の構成図を示す。図中の符合は第
１図、第３図によつて説明した通りであるから説
明を省略する。
Second, a configuration diagram of the embodiment is shown. The reference numerals in the drawings are the same as those described in FIGS. 1 and 3, so their explanation will be omitted.
ツエナーダイオード３を介しコンデンサＣ１に
接続する正電源の電圧Vaは、ツエナーダイオー
ド３の降伏電圧をVzとし直流帰還回路２を構成
する平滑用コンデンサの正常動作中の電圧をVf
とするとき、
＋Va＜Vz＋Vf
の関係にある値を用いる。 The voltage Va of the positive power supply connected to the capacitor C1 via the Zener diode 3 is Vz, which is the breakdown voltage of the Zener diode 3, and Vf, which is the voltage during normal operation of the smoothing capacitor that constitutes the DC feedback circuit 2.
When , values in the relationship +Va<Vz+Vf are used.
電源を投入すると同時に、平滑用コンデンサＣ
１には（Va−Vz）の電圧が直接加えられる。 At the same time as the power is turned on, the smoothing capacitor C
1 is directly applied with a voltage of (Va-Vz).
このため、平滑用コンデンサＣ１はツエナーダ
イオードの降伏電圧に達するまで急速に充電さ
れ、ツエナーダイオード３がカツトオフしてから
Vfに達するまでの間のみ帰還信号によつて充電
がおこなわれる。 Therefore, the smoothing capacitor C1 is rapidly charged until it reaches the breakdown voltage of the Zener diode, and after the Zener diode 3 is cut off,
Charging is performed by the feedback signal only until Vf is reached.
その結果、電源を投入してから平滑用コンデン
サの高電位側の電圧が正常な値に達するまでの時
間は0.1〜0.2秒程度に短縮できる。 As a result, the time from when the power is turned on until the voltage on the high potential side of the smoothing capacitor reaches a normal value can be shortened to about 0.1 to 0.2 seconds.
以上説明したように、本発明の垂直偏向回路で
は、単に１個のツエナーダイオードを追加するだ
けで、立上がり時間を大幅に短縮することができ
る。
As explained above, in the vertical deflection circuit of the present invention, the rise time can be significantly shortened simply by adding one Zener diode.
なお、ツエナーダイオードの追加が回路動作そ
の他にあたえる悪影響はない。 Note that the addition of the Zener diode does not have any adverse effects on circuit operation or other aspects.
第１図は本発明の原理図、第２図は実施例の構
成図、第３図は従来例の構成図である。
図中、１は増幅回路、２は直流帰還回路、３は
ツエナーダイオード、４は偏向コイル、５は交流
帰還回路を表す。
FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a configuration diagram of an embodiment, and FIG. 3 is a configuration diagram of a conventional example. In the figure, 1 represents an amplifier circuit, 2 represents a DC feedback circuit, 3 represents a Zener diode, 4 represents a deflection coil, and 5 represents an AC feedback circuit.
Claims (1)
て垂直偏向コイルに供給する電流を生成する増幅
回路１と、 垂直偏向コイル側から前記のこぎり波の入力側
に直流信号を帰還する直流帰還回路２と、 直流帰還回路２を構成する平滑用コンデンサの
高電位側から正電源側に対し順方向に接続される
ツエナーダイオード３とを備えることを特徴とす
る垂直偏向回路。[Claims] 1. An amplifier circuit 1 that amplifies a sawtooth wave synchronized with a vertical synchronization signal to generate a current to be supplied to the vertical deflection coil, and a DC signal is fed back from the vertical deflection coil side to the input side of the sawtooth wave. A vertical deflection circuit comprising: a DC feedback circuit 2; and a Zener diode 3 connected in a forward direction from the high potential side of a smoothing capacitor constituting the DC feedback circuit 2 to the positive power supply side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31500486A JPS63164761A (en) | 1986-12-26 | 1986-12-26 | Vertical deflection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31500486A JPS63164761A (en) | 1986-12-26 | 1986-12-26 | Vertical deflection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63164761A JPS63164761A (en) | 1988-07-08 |
| JPH044794B2 true JPH044794B2 (en) | 1992-01-29 |
Family
ID=18060256
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31500486A Granted JPS63164761A (en) | 1986-12-26 | 1986-12-26 | Vertical deflection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63164761A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1188716A (en) | 1997-09-03 | 1999-03-30 | Hitachi Ltd | Display device |
-
1986
- 1986-12-26 JP JP31500486A patent/JPS63164761A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63164761A (en) | 1988-07-08 |
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