JPH0449193B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a memory device.

Embodiments of the present invention will be described below with reference to the drawings.

[Configuration and operation of dynamic memory system]

The configuration of the dynamic memory system of the present invention will be explained with reference to FIG. First, the block diagram surrounded by dotted lines shows a dynamic memory system, and this system is D-
RAMICARRAY (hereinafter referred to as D-RAM)
It also includes an interface circuit between the computer's central processing unit (hereinafter referred to as CPU, not shown) and D-RAM.

Next, the above dynamic memory system and CPU
The input/output signals between the First, address signals A _p to A _k are signals for selecting an address of the D-RAM. REFGRNT is a refresh instruction signal for refreshing memory information in the D-RAM. is the write enable signal, and D-
These are data read and write command signals in RAM. MS is a memory activation signal that starts the memory operation of the D-RAM. _D1 to _D8 are CPUs
This is input/output data on the data bus connecting the D-RAM and the D-RAM. REFREQ is a refresh request signal for D-RAM memory information.

Next, the dynamic memory system is D-RAM.
and the above-mentioned interface circuit will be explained separately.
First, D-RAM is an nk-bit integrated circuit (hereinafter referred to as nk
It is called. Note that 1k bits indicates 2 ¹⁰ =1024 bits. ) are arranged in m columns and B in rows, and (n
×m) A matrix of words × B bits is constructed.
It consists of an IC array.

Next, the interface circuit will be explained. RAR
is a row address receiver that receives A p to A i of the address signals A ₀ to _{A k} sent from the CPU and converts them into address signals with timing suitable for D-RAM operation, and CAR is a row address receiver that receives the address signals A _p to _{A i} from among the address signals A 0 to A k sent from the CPU, and converts them into address signals with timing suitable for D-RAM operation. A ₀ ~ _{A k}
Of these, ADR is a column address receiver that receives A _{i +1} to A _J and converts it into an address signal at a timing suitable for D-RAM _{operation . +1} ~ Receive _{A k} , D-
This is an address receiver that converts address signals to timing appropriate for RAM operation.

DCR is a chip selection control signal (hereinafter referred to as CS ₁ to SC _o) for selecting a D-RAM chip.
This is a decoder that sends out (m=2 ^KJ ).

RAS-CT is a RAS control circuit that sends out a chip selection signal and a row address capture signal at timings suitable for the operation of the D-RAM.

ADM uses the above address signals A ₀ ~A _i and A _i+1 ~
This is an address multiplexer that multiplexes _AJ in time series and sends it to D-RAM.

RSG is a refresh synchronization generating circuit that determines the timing for refreshing memory information in the D-RAM.

RAC is a refresh address counter that sends out refresh address signals R _p to _{R l} to refresh memory information in the D-RAM.

DBD is a data bus driver in which data input/output between the CPU and D-RAM is switched by signals.

C-CT is the above RAC, ADM, RAS-CT,
This is a control circuit that sends out signals that control the DBD and D-RAM.

Next, the function of address signals within the dynamic memory system will be explained.

Address signals A ₀ -A _k from the CPU have two functions in the dynamic memory system: address signals A ₀ -A _J and address signals A _J+1 -A _k .

That is, address signals A ₀ -A _J are used as address signals for the memory matrix within each chip of the D-RAM. Also, the address signal A _J+1 ~ _{A k}
When viewed from the D-RAM chip, it becomes a chip selection signal indicating whether or not to select the entire chip.

Here, the address signals A _p to A _J are the address signals according to the matrix in the D-RAM IC chip.
A ₀ ~ A _i for IC chip array row selection, A _i+1 ~
Designed to assign A _J to column selection in IC chip arrays.

Next, the circuit operation within the dynamic memory system will be explained.

Introduction signal, ₁ ~ _n signal,
The RAS _a and _b signals are row address strobe signals, and the RAS signal is a column address strobe signal.

First, address signals A _p to _{A i} and A _i+1 to A _J are applied to ADM via RAR and CAR, respectively.

In ADM, when _{the b} signal reaches a certain level, row address signals A _p to _{A i} are sent out, and D-
Applied to the address pins of RAM. At this time,
Column address signals A _i+1 to A _J are not sent out.

Next, when _{the b} signal becomes the opposite level to the above, column address signals A _i+1 to A _J are sent from the ADM.
Applied to the above address terminal. At this time, the row address signals A ₀ to A _i are not sent out from the ADM.

In this way, the above address signals A ₀ to A _i and
A _i+1 to A _J are applied to the address terminals of the D-RAM in time series depending on the level of _{the b} signal.

In addition, the refresh control signal is applied to ADM and RAC.
Since R _CS is not applied, the refresh address signals A ₀ to R _l are not sent out from the ADM.

Also, chip selection signals A _J+1 to A _k mainly select chips in the D-RAM through the DCR. The signals are converted into chip selection control signals CS ₁ to CS _n (m=2 ^KJ ), and further converted to signals ₁ to _n whose timing is controlled by _{the a} signal, which are used as chip selection signals and row address capture signals. be exposed.

Next, the operation of setting addresses within the chip in each column of the D-RAM will be explained.

First, row address signals A _p to _{A i} are applied to the address terminals of all IC chips of the D-RAM.

After that, it is assumed that when _one signal, for example, one signal among the ₁ to _n signals reaches a certain level, the top B ICs are selected. At this time, the row address signals A _p to _{A i} are taken into the row addresses of the memory matrix arrays in the chips (IC, IC ₁₁ , IC ₁₂ , . . . IC _1B ). here,
The reason why the above row address signals A _p to A _i are applied to the above IC before _{the 1} signal is that if the ₁ signal is applied before the above row address signals A _p to _{A i} , the row address signals other than the row address signals This is because there is a possibility that signals may be captured.

Next, column address signals A _i+1 to _{A J} are applied to D−RAM
applied to the address pins of all IC chips.

Thereafter, when the signal delayed from _{the 1} signal reaches a certain level, the column address signals A _i+1 to A _J are taken into the column addresses of the memory matrix array in the top nk, B IC chips. Here, the above column address signals A _i+1 to _{A J} are
The reason why it is applied to the IC before the CAS signal is the same as the reason above.

Also, the function of the signal is the row address signal.
The purpose is to distinguish which of the column address signals A _p to _{A i} or column address signals A _i+1 to A _J are being sent.

By the above operation, the top stage nk of D-RAM, B
In-chip addresses are set.

In addition, the ICs excluding the top stage of D-RAM are ₂ ~
Since the RAS _n signal is at the opposite level to the level of ₁ , it is not selected.

Next, the data write and read operations at the addresses set above will be explained.

Data write and read operations are designed to be determined by the high level or low level of a write enable signal (hereinafter referred to as a signal).

A write operation is written when the signal is at a certain level. The data D _I1 to D _IB from the CPU are applied as B-bit inputs to the above set addresses via the DBD and written.

In the read operation, data D ₀₁ to _{D 0B} are read from the respective addresses for which writing has been completed as B bit outputs when the signal is at the opposite level to the above.

[Function of control signal]

Abbreviations mean the function of the signal, and those with an inverted symbol (bar) above the abbreviation indicate the function of the meaning of the abbreviation when the signal is “0” (Low Level). is executed, and if there is no bar symbol, it means that it will be executed when it is “1” (High Level).

C-CT is a command signal from the CPU, i.e.
Receive REFGRNT signal, signal, MS signal,
CAS signal, _a signal, _b signal, signal,
Send each R _CS signal. The functions of these sent control signals will be explained.

As for the signal, which one of the row address signals A _p to A _i or the column address signals A _i+1 to A _J is D-
This is a signal to determine whether the signal is being sent to each chip in the RAM, and a signal to take in the column address signal of the IC chip.

_{The a} signal is a signal for supplying the CS ₁ to CS _n signals to the IC chip array in the D-RAM in synchronized timing.

The signal is a signal for deciding whether to read data from or write data to a memory cell in the D-RAM IC chip.

R _CS signal is the start of refresh operation and ADM signal.
This is a signal for prohibiting the sending of address signals Ap to A _{i and} A _i+1 to A _J from RAC and switching to refresh address signals R _p to _{R l} from RAC.

_{The b} signal is the row address signal A _p ~ from ADM.
A _i is a switching timing signal for converting column address signals A _i+1 to A _J into time-series multiplexed signals, and when one of the signals , ₁ to _n is selected, the ADM outputs a row address signal.
As shown in the output of A _p -A _i , the switching times of row address signals A _p -A _i and column address signals A _i+1 -A _J are delayed from that of signal _a .

Next, the relationship between the signals and the data bus driver (DBD) will be explained.

The signal sent from C-CT is applied to D-RAM and DBD. For example, when the signal is at a high level, the read mode is entered, and the data in the D-RAM is output and sent to the CPU via the DBD. At this time, the input data is transferred from the DBD to the
-It is controlled not to be imported into RAM. When the signal is at a low level, the write mode is entered, and input data from the CPU is applied to the data input terminal of the D-RAM via the DBD, and data is written to the set address. At this time D-
The data output of RAM is controlled by a signal so that it is not output from DBD.

[Refresh operation]

A D-RAM memory cell circuit retains information by storing charge in a MOS capacitor, and this charge disappears over time due to leakage current. The problem here is information “1”
(High Level) charge disappears and becomes lower than the reference level for distinguishing between information "1" and "0" (Low Level), information "1" will be discriminated as "0" and a malfunction will occur. be. Therefore, in order to continue storing information "1", it is necessary to refresh the charge before it decreases below the reference level. This refresh operation must be performed within the information storage time of the memory cell. Therefore, this refresh mode has priority over read mode and write mode.

Next, the refresh operation will be explained with reference to FIG.

First, the refresh synchronization generation circuit (hereinafter referred to as
It is called RSG. ) sends a refresh request signal (hereinafter referred to as REFREQ) to (information storage time)/
It is sent to the CPU every (number of refresh cycles) synchronization. (Note that the number of refresh cycles is equivalent to the number of word lines connected to the column data line.) Upon receiving the above REFREQ, the CPU sends out a refresh instruction signal (hereinafter referred to as REFGRNT). At this time, a write enable signal (hereinafter referred to as "MS") and a memory start signal (hereinafter referred to as "MS") are not sent from the CPU. the above
REFGRNT is the control circuit (hereinafter referred to as C-CT
It is called. ), its output signal is the refresh control signal (hereinafter referred to as R _CS ).
is an address multiplexer (hereinafter referred to as ADM) and a refresh address counter (hereinafter referred to as ADM).
It is called RAC. ) is applied to Then,
In the ADM, address signals R _p to R ₄ exclusively for refresh are sent to the D-RAM by the R _CS signal instead of address signals A _p to A _J for random access.

Refresh methods for D-RAM can be roughly divided into two. One method is to sequentially refresh each column of the IC chip array (IC ₁₁ , IC ₁₂ . . . , IC _1B is one column). This method has the advantage that the power consumption required for refreshing is small, but has the disadvantage that it takes time for refreshing.

Another method is to refresh the entire D-RAM IC chip array at the same time. Although this method is not shown in FIG. 1, the address signals A _J+1 to A _k from the address receiver are transmitted to the RAS control circuit (hereinafter referred to as RAS-CT) without passing through the decoder (hereinafter referred to as DCR). ), and all output signals of RAS-CT ₁ ~
When RAS _n reaches a certain level, all columns of D-RAM
Refreshing is performed by simultaneously selecting ICs.

The advantage of this is that the time required for refreshing is short, and the disadvantage is that it consumes a lot of power.

Next, the refresh operation in the matrix array in the D-RAM IC will be explained. Refresh address signals R _p to R _l are applied from within the ADM to the address terminals of the D-RAM, and then the signals reach a certain level, and 2 ^l+1 row addresses of the IC matrix array are sequentially selected. At this time,
The CAS signal is at the opposite level to the above. Therefore, refreshing is performed by amplifying the information in the memory cells connected to the selected row address using a sense amplifier (not shown) so as to widen the level difference between "1" and "0". There is.

Note that the signal is D- during the refresh operation.
Since it is not sent to RAM and DBD, DBD
No data is input or output from the .

[Function of RAS system signals and CAS system signals]

RAS system signals (hereinafter referred to as RAS-φ) and
The function of the CAS system signal (hereinafter referred to as CAS-φ) will be explained with reference to FIG.

(1) RAS− _φφAR is an address buffer control signal, which is applied to the address buffer (hereinafter referred to as ADB) and is applied to the row address signals A _p to A _i latched in ADB. Corresponding levels a _p ~ _p ,...
a _i , _i is a row/column decoder (hereinafter referred to as RC-
It is called DCR. ) is a signal that determines whether or not to send it to.

_φX is the word line control signal, which is RC−
DCR is applied to the memory array (hereinafter referred to as M-
It is called ARY. This signal determines whether or not to send the signal selected for selecting the row address of ) to M-ARY.

_φPA is a sense amplifier control signal, which is applied to the sense amplifier and drives the sense amplifier.

(2) CAS−φφ _AC is the address buffer control signal, which is applied to ADB and has a level corresponding to the column address signals A _i+1 to A _J latched to ADB.
This is a signal for determining whether or not to send a i ₊₁ , _i+1 , ... a _j , _j to the RC-DCR.

φ _Y is the column switch control signal, which is
This signal is applied to RC-DCR and selects the column switch connected to the M-ARY column data line by the selected signal.

φ _OP is the data output buffer and output amplifier control signal, which is referred to as the data output buffer (hereinafter referred to as
It is called DOB. ) and an output amplifier (hereinafter referred to as OA), and is a signal that sends read data from the MA-ARY to the output data (Dout) terminal.

φ _RW is a data input buffer control signal, which is a data input buffer (hereinafter referred to as DIB).
This signal is applied to the input data (Din) terminal and causes the write data from the input data (Din) terminal to be sent to the M-ARY.

_RW is a data output buffer control signal, which is applied to DOB and is a signal that prevents read data from being output to the data output (Dout) terminal during a write operation.

[D-RAM configuration and operation]

The configuration of the D-RAM will be explained with reference to FIG.
A block surrounded by a dotted line indicates a D-RAM integrated circuit (hereinafter referred to as IC).

In the above IC, the block surrounded by a dashed line is a timing pulse generation block, and D-
It consists of circuits that generate signals that control the operation of each circuit in the RAM.

Next, the operation of each circuit of the D-RAM will be explained according to the timing diagram of FIG.

When the row address signals A _p -A _i are taken into an address buffer (hereinafter referred to as ADB) and latched, the signals become low level later than the row address signals A _p -A _i . Here, the reason why the signal is delayed from the row address signals A _p -A _i is to ensure that the row address signals A _p -A _i are taken in as a row address in the memory array.

Next, the signal φ _AR delayed from the signal is applied to ADB, and the levels a _p , _p , ... a _i , _i corresponding to the latched row address signal are applied to the row/column decoder (hereinafter referred to as RC-DCR). ). The above levels a _p , _p , ... a _i , in RC-CDR
When a _i is applied, only the selected RC-DCR remains at high level, and the unselected one remains at low level.

Then, when the signal φ _X delayed from φ _AR is applied to RC-DCR, the selected signal is M-ARY
sent to. Here, the reason why _φX is delayed from _φAR is that the RC-DCR is operated after the ADB operation is completed. In this way, the row address in M-ARY is one of the 2 ^{i + 1} output signals of RC-DCR.
Since one line will be at a high level, the corresponding M
-Set by selecting one row address line in ARY.

Next, “1” of the memory cell connected to the selected one row address line in M-ARY
Alternatively, "0" information is amplified by a sense amplifier (hereinafter referred to as SA). This SA operation starts when φ _PA is applied.

After that, the column address signals A _i+1 ~ _{A J} are ADB
Column address signal
The signal becomes low level later than A _i+1 ~ _{A J.} Here, the signal is column address signal A _i+1
The reason for delaying ~A _J is to ensure that the column address signal is taken in as the column address in the memory array.

Next, when the signal φ _AC delayed from the signal is applied to ADB, the levels a _i+1 , _i+1 , . . . a _J , _J corresponding to the column address signal are sent to the RC-DCR. Then, RC-DCR performs the same operation as above. The selected signal is sent to the column switch (hereinafter referred to as C-SW) when the signal φ _Y delayed from φ _AC is applied to RC-DCR.
Thus, the column address in M-ARY is AD
- Since one of the 2 ^Ji output signals of DCR becomes high level, one C-SW is selected, and the column address line, that is, the data line connected to this C-SW is selected. Set by.

In this way, one address within the M-ARY is set.

Next, read and write operations for the addresses set as described above will be explained.

In read mode, the signal is at high level. This signal is designed to go high before going low. This is because when the signal goes to low level, one address of M-ARY is set as a result, so the signal is set to high level before that to prepare for the read operation and shorten the read start time. .

Also, when the CAS system signal φ _OP is applied to the output amplifier, the output amplifier becomes active, the information at the address set above is amplified, and the data is output via the data output buffer (hereinafter referred to as DOB). (Dout) terminal. Reading is performed in this manner, and the read operation is completed when the signal becomes high level.

Next, in the write mode, the signal becomes low level. The signal φ RW created by this low level signal and the low level signal becomes high level and the data input buffer (hereinafter referred to as
It is called DIB. ), DIB becomes active, and write data from the input data (Din) terminal is sent to the address set in the M-ARY, thereby performing a write operation.

At this time, an inverted signal of the above-mentioned φ _RW , that is, a low level signal _RW is applied to DOB to control so that data is not read out during the write operation.

Also, the RAS system signal (RAS-φ) generated from the above timing pulse generation block (TGB)
In addition to the signals mentioned above, the signals ₁₁ , ₁₂ , ₁₃ and _xdp are sequentially delayed.
In addition to the above, the CAS system signal (CAS-φ) includes a signal in which the signals are sequentially delayed.
Includes CAS ₁₁ , ₁₂ and ₁₃ (not shown).

[Overview of configuration and operation of D-RAM transistor circuit]

In the circuit shown in Figures 4A and B, the N-channel
MISFET (Metel Insulator Semiconductor
N-channel IGFET (Insulator-Gate Field Effect Transistor)
Transistor) as an example.

Configuration of memory cell M-CEL A 1-bit M-CEL consists of a capacitor C _S for information storage and a MISFET Q _M for address selection.
Information of "1" and "0" is stored in the form of whether or not there is a charge in the capacitor _CS .

Read signal amount To read information, turn on MISFETQ _M.
This is done by connecting _CS to a common column data line DL and sensing how the potential of the data line DL changes depending on the amount of charge accumulated in _CS . Assuming that the potential previously charged in the stray capacitance C _p of the data line DL is the power supply voltage Vcc, if the information stored in C _S is "1" (potential of V _CC ), at address time data line
The potential of DL (V _DL ) "1" remains the potential of V _CC , and if it is "0" (0V), (V _DL )
“o” becomes {C _p ·V _CC −C _S (V _W −V _th )}/C _p .
However, V _W is the date voltage of MISFETQ _M , and V _th is
This is the threshold voltage of MISFETQ _M. Here, the difference between logic "1" and logic "0", that is, the detected signal amount ΔV _S is ΔV _S = (V _DL ) "1" - (V _DL ) "0" = (V _W - V _th )・C _S /C _p . When V _W =V _CC , the signal amount ΔV _S becomes ΔV _S =(V _CC −V _th )·C _S /C _p .

Since the memory cells are made small and many memory cells are connected to a common data line to form a highly integrated and large capacity memory matrix, V _S ≪ C _p , that is, C _S /C _p becomes a very small value. . Therefore, ΔV _S is a very small signal.

Reference signal for reading A dummy cell D-CEL is used as a reference for detecting such a minute signal. D-
CEL is manufactured under the same manufacturing conditions and design constants as M-CEL, except that the capacitance value of capacitor C _ds is approximately half that of C _S . C _ds is charged to ground potential (the other electrode is fixed at V _CC ) by MISFETQ _D2 prior to addressing. Therefore, the amount of signal change ΔV _R applied to the common column data line DL at the time of addressing is expressed by the following equation similarly to that of the memory cell (ΔV _S ). However, V _DW is
The gate voltage of MISFETQ _D2 , V _th ′ is MISFETQ _D2
is the threshold voltage of

When ΔV _R =(V _DW −V _th ′)·C _ds /C _p V _DW =V _CC , ΔV _R is expressed by the following formula.

ΔV _R =(V _CC −V _th ′)·C _ds /C _pAs mentioned above, C _ds is set to approximately half of C _S , so ΔV _R is approximately equal to half of ΔV _S. Therefore, "1" and "0" information can be determined depending on whether the potential change applied to the data line DL of the memory cell is smaller or larger than that of the dummy cell (ΔV _R ).

Layout of each circuit SA ₁ is a sense amplifier that expands the difference in potential change that occurs during address into the sensing period determined by the timing signal (sense amplifier control signal) φ _PA (the operation will be described later). Its input and output nodes are coupled to complementary data lines DL _1-1 , _1-1 arranged in parallel. Data line DL _1-1 ,
The number of memory cells coupled to DL _1-1 is made equal to increase detection accuracy, and one dummy cell is coupled to each of DL _1-1 and _{DL 1-1} . Each memory cell is also coupled between one word line WL and one of a complementary pair of data lines. Each word line WL
crosses both data line pairs, so even if the noise component generated on the word line WL is transferred to the data line due to capacitive coupling, the noise component appears equally on both data lines, and the differential sense amplifier offset by SA.

A pair of dummy word lines DWL _1-1 , DL 1-1, _1-1 are connected so that when a memory cell coupled to one of the complementary data line pairs DL 1-1, _1-1 is selected, a dummy cell is always coupled to the other data line. One of DWL _1-2 is selected.

Sense Amplifier Operation This sense amplifier SA ₁ has a pair of cross-coupled MISFETs _{Q S8} and Q _S9 , and uses their positive feedback action to differentially amplify minute signals. This positive feedback operation starts at the same time that MISFETQ _S10 starts conducting due to the timing signal (sense amplifier control signal) φ _PA , and based on the potential difference applied during addressing, the higher data line potential (V _H ) is slower. The one with the lower speed (V _L ) descends at a faster speed while the difference between them widens. Thus, V _L is the threshold voltage of the cross-coupled MISFET, V _th
The positive feedback operation ends when V H falls to 0 V, and V _H remains at a potential smaller than V _CC and larger than V _th , and V _L eventually reaches 0 V.

During addressing, the stored information in a memory cell that is once destroyed is recovered (rewritten) by directly receiving the potential of V _H or V _L obtained by this sensing operation.

Compensation for Logic "1" Level However, if V _H falls below V _CC by more than a certain level, a malfunction will occur that will be read as logic "0" after reading and rewriting several times. The active restore circuit AR ₁ was provided to prevent this malfunction, and this AR ₁ has the function of selectively boosting only V _H to the potential of V _CC without having any effect on V _L. There is. The capacitance of C _B11 and C _B12 changes depending on the potential applied to the terminal on the left side of the drawing.
It is an MIS type variable capacitance element, and it should be understood that logically it can act as a capacitor at a voltage higher than the threshold voltage V _th and cannot act as a capacitor at a lower voltage.

When MISFETQ _S4 and Q _S5 are made conductive by the timing signal (active restore control signal) φ _rg , the variable capacitance element C _B belonging to the data line at the potential of V _H is charged, signal) When _φrs becomes high level, MISFETQ _S6 or
The gate potential of Q _S7 becomes sufficiently higher than V _CC and the potential of V _H is restored to V _CC . In this case, in order to reduce the power loss of Q _S6 and Q _S7 , each V _th is designed to be smaller than the MISFET without an asterisk.

[Time-series operation of D-RAM transistor circuit]

Read operation precharge period φ When _PC is high level (higher than V _CC )
MISFETQ _S2 , Q _S3 are conductive and complementary data line pair
The stray capacitance C _p of DL _1-1 and _1-1 is precharged to V _CC . At this time, MISFET Q _S1 is also conductive at the same time, so even if an imbalance occurs in the precharging by Q _S2 and Q _S3 , the complementary data line pair DL _1-1 , _1-1 is short-circuited and set to the same potential condition. MISFETQ _S1 to Q _S3
The V _th of these MISFETs is set lower than that of MISFETs without an asterisk (*) to prevent voltage loss between the source and drain.

At this time, the timing signal (discharge control signal) φ _dc causes MISFET Q _d2 to conduct, and the dummy cell D-CEL is similarly reset to a predetermined state.

Row address period timing signal (address buffer control signal)
The row address signals A _p to A _i supplied from the address buffer ADB at the timing of φ _AR (see Figure 3) are decoded (deciphered) by the row/column decoder RC-DCR and output as the word line control signal _φ Addressing of the memory cell M-CEL and the dummy cell D-CEL is started simultaneously with the rise of the dummy cell D-CEL.

As a result, a voltage difference of approximately ΔV _S /2 is generated between the complementary data line pair DL _1-1 and _{DL 1-1} based on the stored contents of the memory cells, as described above.

Sensing timing signal (sense amplifier control signal) φ _PA
As soon as MISFETQ _S10 starts to conduct, sense amplifier _SA1 starts positive feedback operation and amplifies the detection signal of ΔV _S /2 generated at the time of address. After the amplification operation is almost completed, the above-mentioned active list circuit AR ₁ restores the logic "1" level to V _CC in synchronization with the timing signal (active restore control signal) φ _rs .

Data output operation timing signal (address buffer control signal)
Column address signals A _i+1 to A _j sent from address buffer ADB in synchronization with φ _AC are low.
The information stored in the memory cell M-CEL at the column address selected by the timing signal (column switch control signal) φ _r after being decoded by the column decoder RC-DCR is sent to the column switch C-SW ₁
is transmitted to the common input/output lines CDL ₁ , ₁ via

Next, the main amplifier/data output buffer MA&DOB operates according to the timing signal (data output buffer and main amplifier control signal) φ _OP .
The read memory information is sent to the chip's output terminal Dout. Note that MA&DOB is disabled by a timing signal (data output buffer control signal) φ _RW during writing.

Write Operation Row Addressing Period Precharge, addressing, and sensing operations are exactly the same as the read operation described above. Therefore, irrespective of the logic value of the input write information Din, the storage information of the memory cell to which writing is originally to be performed is read to the complementary data line pair DL _1-1 , _1-1 .
Since this read information is to be ignored in the write operation described later, the operation up to this point can be considered to be essentially row address selection.

Write period Similar to the read operation, the data line pair DL _1-1 , _1-1 located in the selected column is switched via the column switch C-SW ₁ in synchronization with the timing signal (column switching control signal) _φr . Common input/output line
Combined with CDL ₁ , ₁ .

Next _, complementary write input signals dio, _io supplied from the data input buffer DIB in synchronization with the timing signal (data input buffer control signal) _φRW are sent to the memory cell M- through the column switch C- _SW1 .
Written to CEL. At this time, the sense amplifier
Although SA ₁ is also operating, the output impedance of the data input buffer DIB is low, so the information appearing on the column data line pair DL _1-1 , _1-1 is determined by the information on the input Din.

Refresh operation The refresh operation is to temporarily read the information that is being lost stored in the memory cell M-CEL to the column common data line DL, and restore the read information to the restored level by the sense amplifier SA ₁ and the active restore circuit AR ₁ . Then again memory cell M-
This is done by writing to the CEL. Therefore, the refresh operation is similar to the row addressing or sensing period operation described in the read operation. However, in this case, the column switch C- _SW1 is made inactive and refresh is performed simultaneously for all columns and for each row in turn.

[2-mat type 64k-D-RAM circuit configuration] Figure 5A shows memory cells of about 64k bits each having a storage capacity of 128 columns (rows) x 256 columns (columns) = 32768 bits (32k bits). memory cell matrix (memory array M-ARY ₁ , M
_-ARY2 ) is shown. The main blocks in this figure are drawn according to their actual geometrical arrangement.

The row address selection lines (word lines WL) of _each memory array M-ARY ₁ and M-ARY ₂ have 2 ₁₁ ⁼
128 decode output signals are applied from each row decoder (also word driver) R-DCR ₁ and R-DCR ₂ .

The column decoder C-DCR provides 128 decoded output signals based on column address signals _A9 to _A15 . This column selection decode output signal is common to the left and right memory arrays and adjacent upper and lower columns in each memory array, that is, to a total of four columns.

Address signals A ₇ and A ₈ are assigned to select any one of these four columns. For example, A ₇ is assigned to left/right selection, and A ₈ is assigned to top/bottom selection.

The φ _yij signal generating circuit φ _vij -SG decodes four combinations based on the address signals A ₇ and A ₈ , and the column is decoded based on the output signals φ _y00 , φ _y01 , Y _y10 , and φ _y11 . The column switch selectors CSW-S ₁ and CSW-S ₂ are used for switching.

In this way, the decoders for selecting columns of the memory array include the column decoder C-DCR and the column switch selectors CSW-S ₁ . CSW−
It is divided into two stages of S ₂ . The purpose of dividing the decoder into two stages is, first, to prevent unnecessary blank areas from occurring within the IC chip. In other words, the vertical arrangement interval (pitch) of the NOR gates, which have a relatively large area and carry the pair of left and right output signal lines of the column decoder C-DCR, is made to match the column arrangement pitch of the memory cells. That is, by dividing the decoder into two stages, the number of transistors forming the NOR gate can be reduced, and the area occupied by the NOR gate can be reduced.

The second aim of dividing the decoder into two stages is to
By reducing the number of NOR gates connected to one address signal line, the load on one address signal line is reduced and switching speed is improved.

The address buffer ADB receives eight multiplexed external address signals _A0 to _A7 ;
Process _A8 to _A15 into eight types of complementary pair address signals _a0 , ₀ to _a7 , ₇ , _a8 , ₈ to _a15 , _15, respectively,
Timing φ _AR that matches the operation inside the IC chip,
φ Send to the decoder circuit by _AC .

[Two-mat type 64k-D-RAM circuit operation] The circuit operation in the address setting process in the two-mat type 64k-D-RAM will be explained with reference to FIGS. 5A and 5B.

First, by rising the row-related address buffer control signal φ _AR to a high level, seven types of complementary pair row address signals a ₀ , ₀ to a 6 , ₆ corresponding to the row address signals A ₀ to _{A 6 are generated} . However, the address buffer
It is applied from ADB to row decoders R-DCR ₁ and R-DCR ₂ via row address line R-ADL.

Next, the word line _control signal _φ
DCR ₂ becomes active and each memory array M-
One each of the word lines WL of ARY ₁ and M-ARY ₂ is selected and set to high level.

Next, the column system address buffer control signal φ _AC
rises to high level, seven types of complementary pair column address signals _a9 , ₉ to _a15 to ₁₅ corresponding to column address signals _A9 to _A15 are transferred from address buffer ADB to column address line C-. It is applied to the column decoder C-DCR via ADL.

As a result, one pair of the 128 pairs of output signal lines of the column decoder C-DCR becomes high level, and this high level signal is transmitted to the column switch selector CSW-
Applied to S ₁ and CSW−S ₂ .

Next, when the column switch control signal φ _r rises to a high level, the φ _yij signal generating circuit φ _yij -SG becomes operational.

On the other hand, when the address buffer control signal _φAR reaches the high level, the complementary pair signals _a7 , ₇ , which already correspond to the address _signal A7, also change to the address signal _A8 .
Complementary pair signals a ₈ and ₈ corresponding to are respectively applied to the φ _yij signal generation circuit φ _{yij −SG} when the address buffer control signal φ _AC becomes high level. Therefore, when the column switch control signal φ _Y becomes high level, almost at the same time, the φ _yij signal generating circuit φ _yij -SG outputs the column switch selector CSW-S ₁ ,
Sends a signal to CSW-S ₂ .

In this way, the column switches C-SW ₁ , C
One pair out of a total of 512 transistor pairs in -SW ₂ is selected, and a pair of data lines DL in the memory array are connected to the common data line CDL.

[2-mat D-RAMIC layout pattern] A so-called 2-mat D-RAMIC where the memory array is divided into two parts within one IC chip.
The layout pattern will be explained according to FIG.

First, two
The two memory arrays M-ARY ₁ and M-ARY ₂ are arranged spaced apart from each other in the IC chip.

A common column decoder C-DCR is arranged in the center of the IC chip between M-ARY ₁ and M-ARY ₂ .

A dummy array D- consisting of a column switch C-SW ₁ for M-ARY ₁ and a plurality of dummy cells.
ARY ₁ is placed between M-ARY ₁ and C-DCR.

On the other hand, column switch C- for M-ARY ₂
A dummy array D-ARY ₂ consisting of SW ₂ and a plurality of dummy cells is arranged between M-ARY ₂ and C-DCR.

The sense amplifiers SA ₁ and SA ₂ are affected by noise, such as C-
They are placed at the left and right ends of the IC chip to prevent malfunctions caused by signals applied to the DCR and to facilitate wiring layout.

On the upper left side of the IC chip, there is a data input buffer DIB and a read/write signal generation circuit R/W-.
An SG and RAS signal generation circuit _SG1 is arranged. Signal application pads P- and signal application pads P- are located close to these circuits.
WE and a data signal application pad P- _Dio are arranged.

On the other hand, on the upper right side of the IC chip, a data output buffer DOB, a CAS signal generation circuit CAS-SG, and a CAS system signal generation circuit _SG2 are arranged. A V _SS voltage supply pad P-V _SS , a signal application pad P-, a data signal output pad P-D _put , and an address signal A ₆ supply pad DA ₆ are arranged adjacent to these circuits.

A main amplifier MA is arranged between the RAS signal generation circuit SG ₁ and the CAS signal generation circuit SG ₂ .

The V BB generation circuit V _{BB -G} is installed above circuits that occupy a large area such as the RAS signal generation circuit SG ₁ , the CAS signal generation circuit SG ₂ , or the main amplifier MA.
is located. This is because V _BB −G generates minority carriers, and M
There is a risk that the memory cells forming -ARY ₁ and M-ARY ₂ will undergo undesired information inversion. Therefore, to prevent this, the V _BB generation circuit V _BB −G
As mentioned above, is placed as far away from M-ARY ₁ and M-ARY ₂ as possible.

A row decoder R-DCR ₁ for M-ARY ₁ is arranged on the lower left side of the IC chip. and,
Address signal supply pads P-A ₀ , P-A ₁ , P-A ₂ and V _CC voltage supply pad P-V _CC are arranged adjacent to R-DCR ₁ .

On the other hand, a row decoder R-DCR ₂ for M-ARY ₂ is arranged on the lower right side of the IC chip. Address signal application pads P- _{A 3 ,} P-A ₄ ,
P-A ₅ and P-A ₇ are arranged.

An address buffer ADB is arranged between R-DCR ₁ and R-DCR ₂ .

[8-mat type 64k-D-RAM circuit configuration] Figure 7A shows memory cells of approximately 64k bits each having a storage capacity of 128 columns (rows) x 64 rows (columns) = 8192 bits (8k bits). A D-RAM circuit configuration diagram is shown in which the D-RAM circuit is arranged in two memory cell matrices (memory arrays M-ARY 1 to M-ARY ₈ ). The main blocks in this figure are drawn according to their actual geometrical arrangement.

Address signal A ₀ is applied to the row address selection line (word line WL) of each memory array M-ARY _{1 to 8} .
2 ⁷ =128 decoded output signals obtained based on ~A ₆ are applied.

At this time, in order to shorten the wiring length of the word line WL, that is, to reduce the propagation delay time of signal transmission on the word line WL, a total of four row decoders (also word drivers) R-DCR _{1 to 4} are installed. Each memory array is arranged between two memory arrays.

Column decoder C-DCR receives address signal A ₉
Provides 128 decoded output signals based on ~ _A15 . This column selection decode output signal is common to the left and right memory arrays and adjacent upper and lower columns in each memory array, that is, to a total of four columns.

Address signals A ₇ and A ₈ are assigned to select any one of these four columns. For example, A ₇ is assigned to left/right selection, and A ₈ is assigned to upper/lower selection.

The φ _yij signal generation circuit φ _yij −SG decodes into four combinations based on address signals A ₇ and A ₈
The column switch selectors CSW-S ₁ and CSW-S ₂ switch columns based on the output signals φ _y00 , φ _y01 , φ _y10 , and φ _y11 .

In this way, the decoder for selecting a column of the memory array includes the column decoder C-DCR and the column switch selectors CSW-S ₁ and CSW-
It is divided into two stages of S ₂ . The purpose of dividing the decoder into two stages is, first, to prevent unnecessary blank areas from occurring within the IC chip. In other words, the vertical arrangement interval (pitch) of the NOR gates, which have a relatively large area and carry the pair of left and right output signal lines of the column decoder C-DCR, is made to match the column arrangement pitch of the memory cells. That is, by dividing the decoder into two stages, the number of transistors forming the NOR gate can be reduced, and the area occupied by the NOR gate can be reduced.

The second aim of dividing the decoder into two stages is to
By reducing the number of NOR gates connected to one address signal line, the load on one address signal line is reduced and switching speed is improved.

The address buffer ADB receives eight multiplexed external address signals A ₀ to _{A 7} ,
Process _A8 to _A15 into eight types of complementary pair address signals _a0 , ₀ to _a7 , ₇ , _a8 , ₈ , _a15 , _15, respectively,
Timing φ _AR that matches the operation inside the IC chip,
φ Send to the decoder circuit by _AC .

By the way, the complementary pair address signal a ₀ , ₀ ~
_{a7 , a7} and _a8,8 to _a15,15 remain multiplexed _. One of the main reasons is that the address buffer, address signal A ₀
By sharing the address buffers with ~ _A7 and _A8 ~ _A15 , the number of address buffers can be reduced to 8 instead of 16. Another reason will become clear from the following explanation. Dew.

In the center of the figure, eight types of complementary pair address signal lines (column/row address lines CL-ADL run vertically (actually column decoders C-DCR)
(passes approximately through the center of the area). These address signal lines are commonly used for row selection address signals A ₀ to A ₇ and column selection address signals A ₈ to _{A 15} , so the number of wiring lines and the area occupied are reduced compared to when they are independent. has been reduced by half.

The column/row address line CR-ADL connects column/row changeover switches C/R-SW 1 and C/R-SW ₁ and C/ It is branched in both left and right directions via R-SW ₂ , and the row decoder R-
Connected to DCR _1~4 .

The above column/row selector switch C/R-SW ₁ ,
C/R-SW ₂ is a complementary pair of row address signals a ₀ , ₀ ~
It is controlled by a row-related timing signal φ _xy (column/row changeover switch control signal) so that only a ₆ and ₆ are passed. Furthermore, since the operation of the column decoder C-DCR itself is controlled by the column system timing signal φ _df (column decoder control signal),
The multiplexed complementary pair column address signals _a9 , ₉ to _a15 , ₁₅ are complementary pair row address signals
It is divided into a ₀ , ₀ to a ₆ , ₆ .

[8-mat type 64K-D-RAM circuit operation] The circuit operation in the address setting process in the 8-mat type 64K-D-RAM will be explained with reference to FIGS. 7A and 7B.

When the row-related address buffer control signal φ _AR rises to a high level, the address signal A ₀
Eight types _of complementary pair row address signals _a0-0 - _a7-7 corresponding to _{~ A7} are sent from address buffer ADB to column/row address line CR-ADL.

At this time, the column/row selector switch C/R-
Both SW ₁ and C/R-SW ₂ receive the column/row changeover switch control signal φ _xy in a high level state.
Therefore, the complementary pair row address signals a ₀ , ₀ to _{a 6} ,
_a6 is applied to the row decoders R-DCR 1 and R-DCR ₂ via the column/row switching switch C/R-SW ₁ and _the row address line R-ADL ₁ , and
Row decoder R via column/row changeover switch C/R-SW ₂ and row address line R-ADL _2.
-DCR3 and R- _DCR4 .

Next, the word line _control signal _φ
becomes active, and each memory array M-ARY ₁
~ One of each of the _eight word lines WL is selected and set to high level.

Next, the column system address buffer control signal φ _AC
When the address signal rises to high level,
Eight types of complementary pair column address signals _{a8, 8 to a15} , ₁₅ corresponding to _A8 to _A15 are used as address buffer ADB.
is sent to the Kakam row address line CR-ADL.

At this time, the column/row switching line switch C/R-
Since SW ₁ and C/R-SW ₂ are already OFF, complementary pair column address signals a ₉ , ₉ to a ₁₅ , ₁₅
is never applied to the row decoder R-DCR.

Next, when the column switch control signal φ _Y rises to a high level, the φ _yij signal generating circuit φ _yij -SG becomes operational. On the other hand, the complementary pair signals a ₇ and ₇ corresponding to the address signal _A 7 are already activated when the address buffer control signal φ _AR becomes high level, and the complementary pair signals a ₈ and ₈ corresponding to the address signal A ₈ are already activated. When the address buffer control signal φ _AC becomes high level, it is applied to the φ _yij signal generation circuit φ _yij −SG, respectively. Therefore, when the column switch control signal φ _y rises to a high level, the φ _yij signal generating circuit φ _yij -SG switches to the column switch selector almost at the same time.
Sends signals to CSW-S ₁ and CSW-S ₂ .

In this way, the column switches C-SW ₁ , C
One pair out of a total of 512 transistor pairs in -SW ₂ is selected, and a pair of data lines DL in the memory array are connected to the common data line CDL.

[8-mat D-RAMIC layout pattern] The so-called 8-mat D-RAMIC layout pattern has a memory array divided into eight sections in one IC chip.
The RAMIC layout pattern will be explained according to FIG.

As shown in FIG.
8 memory arrays M configured by CEL
-ARY ₁ to M-ARY ₈ are arranged separately from each other in the IC chip.

A column decoder C-DCR _{1, which is a part of C-DCR, is arranged between M-ARY 1} and M-ARY ₂ , and further between M-ARY ₁ and C-ARY ₂ .
A dummy array D-ARY ₁ for M-ARY ₁ and a column switch C-SW ₁₁ which is a part of C-SW ₁ are arranged between the DCR 1 and the column switch C-SW ₁₁ .
On the other hand, there is M-ARY between M-ARY ₂ and C-DCR ₁ .
Dummy array D for ARY ₂ - ARY ₂ and C
-Column switch C which is part of SW _2-
SW ₂₁ is located.

A column decoder C-DCR ₂ , which is a part of C-DCR, is arranged between M-ARY ₃ and M-ARY ₄ , and further between M-ARY ₃ and C-ARY 4.
A dummy array D-ARY _{3 for M-ARY 1 and} a column switch C-SW ₁₂ , which is part of C-SW ₁ , are arranged between DCR ₂ and D-ARY 2. On the other hand, there is an M-ARY between M-ARY ₄ and C-DCR _2.
Dummy array D for ARY ₄ - ARY ₄ and C
-Column switch C which is part of SW _2-
SW ₂₂ is located.

A column decoder C-DCR ₃ , which is a part of C-DCR, is arranged between M-ARY ₅ and M-ARY ₆ , and further between M-ARY ₅ and C-DCR.
D-ARY ₅ for M-ARY ₅ and column switch C-SW ₁₃ , which is part of C-SW ₁ , are arranged between DCR ₃ and D-ARY 5. On the other hand, M-
A dummy array D-ARY ₄ for M-ARY ₆ and a column switch C-SW ₂₃ , which is part of C-SW ₂ , are arranged between ARY ₆ and C-DCR ₃ .

A column decoder C-DCR ₄ , which is a part of C-DCR, is arranged between M-ARY ₇ and M-ARY ₈ , and further between M-ARY ₇ and C-DCR ₄ .
There is a dummy array D- for M-ARY ₇ between
A column switch C-SW ₁₄ , which is part of ARY ₇ and C-SW ₁ , is located. on the other hand,
A dummy array D-ARY ₈ for M-ARY ₈ and a column switch C-SW ₂₄ , which is part of C-SW ₂ , are arranged between M-ARY ₈ and C-DCR ₄ . .

A row decoder R-DCR 1 is provided between M-ARY ₁ and M-ARY ₃ , and a row decoder R-DCR ₁ is provided between M-ARY 1 and M-ARY ₃ .
- ARY ₄ , there is a row decoder R-DCR ₂ for them, and between M-ARY ₅ and M-ARY ₇ there is a row decoder R-DCR ₃ for them. Row decoders R-DCR ₄ for these are arranged between M- _{ARY 6} and M-ARY ₈ , respectively.

C-DCR ₁ , C-DCR ₂ , R-DCR ₁ and R-
A column/row changeover switch C/R-SW ₁ is arranged at a position surrounded by DCR ₂ .

On the other hand, a column/row changeover switch C/R-SW ₂ is arranged at a position surrounded by C-DCR ₃ , C-DCR ₄ , R-DCR ₃ and R-DCR ₄ .

Sense amplifier for M-ARY ₁ to M-ARY ₈
SA ₁ to _{SA 8} are noises, e.g. C-DCR ₁ to C-DCR ₈
To prevent malfunction due to signals applied to the circuit, and to facilitate wiring layout.
They are located at the left and right ends of the IC chip.

On the upper left side of the IC chip, there is a data input buffer DIB and a read/write signal generation circuit R/W-.
SG, RAS signal generation circuit RAS-SG, and RAS system signal generation circuit _SG1 are arranged. Then, a signal application pad P- is placed close to these circuits.
RAS, a signal application pad P-, and a data signal application pad P-Din are arranged.

On the other hand, on the upper right side of the IC chip, there is a data output buffer DOB, a CAS signal generation circuit CAS-
An SG and CAS system signal generation circuit SG ₂ is arranged. A V _SS voltage supply pad P-V _SS and a signal application pad P- are connected adjacent to these circuits.
CAS, a data signal take-out pad P-D _put , and an address signal A ₆ application pad D-A ₆ are arranged.

A main amplifier MA is arranged between the RAS signal generation circuit SG ₁ and the CAS signal generation circuit SG ₂ .

A V _BB generation circuit V _BB -G is placed above a circuit that occupies a large area, such as the RAS signal generation circuit SG ₁ , the CAS signal generation circuit SG ₂ , or the main MA. This is because V _BB -G generates minority carriers, and M-
There is a risk that the memory cells forming ARY ₁ and M-ARY ₂ will undergo undesired information inversion. therefore,
To prevent this, the V _BB generating circuit V _BB -G is placed as far away from M-ARY ₁ and M-ARY ₂ as possible, as described above.

An address buffer ADB is arranged in the lower part of the IC chip adjacent to the C-DCR ₄ . and,
In particular, on the lower left side of the IC chip, there are address signal supply pads P-A ₀ , P-A ₁ , P-A ₂ and
A V _CC voltage supply pad P-V _CC is located.
On the other hand, address signal supply pads P-A ₃ , P-A ₄ , P-A ₅ , P-
A ₇ is located.

[Memory cell element structure]

FIG. 9 is a perspective cross-sectional view showing the element structure of one memory cell M-CEL, in which 1 is a P-type semiconductor substrate;
2 is a relatively thick insulating film (hereinafter referred to as field insulating film), 3 is a relatively thin insulating film (hereinafter referred to as gate insulating film), 4 and 5 are N ⁺ type semiconductor regions, 6 is a first polycrystalline silicon layer, 7 is an N-type surface inversion layer, 8
9 indicates a second polycrystalline silicon layer, 9 indicates a PSG (phosphorus silicate glass) layer, and 10 indicates an aluminum layer.

MISFETQM in one memory cell M-CEL
, whose substrate, source region, drain electrode, gate insulating film and gate electrode are the above-mentioned P type semiconductor substrate 1, N ⁺ type semiconductor region 4, N ⁺ type semiconductor region 5,
Each of them is composed of a gate insulating film 3 and a second polycrystalline silicon layer 8. The second polycrystalline silicon layer 8 is, for example, connected to the word lines WL _{1 to 2} shown in FIG. 4A.
used as. The aluminum layer 10 connected to the N ⁺ type semiconductor region 5 is used, for example, as data lines _DL1-1 shown in FIG. 4A.

On the other hand, in the storage capacitor C _S in the memory cell M-CEL, one electrode, the dielectric layer, and the other electrode are connected to the first polycrystalline silicon layer 7 and the gate insulating film 3.
and an N-type surface inversion layer 7, respectively. That is, since the power supply voltage V _CC is applied to the first polycrystalline silicon layer 6, this power supply voltage
V _CC induces an N-type surface inversion layer 7 on the surface of the P-type semiconductor substrate 1 due to the electric field effect via the gate insulating film 3 .

[Dummy cell element structure]

FIG. 10 is a perspective cross-sectional view showing the element structure of one dummy cell D-CEL. In Figure 10,
In particular, 11 to 14 are N ⁺ type semiconductor regions, 15 is a first polycrystalline silicon layer, 16 is an N type surface inversion layer, 1
7 and 18 are second polycrystalline silicon layers, and 19 is an aluminum layer.

MISFETQ _D1 in one dummy cell D-CEL
is a P-type semiconductor substrate 1 whose substrate, drain region, source region, gate insulating film and gate electrode are
Each of them is composed of an N ⁺ type semiconductor region 11, an N ⁺ type semiconductor region 12, a gate insulating film 3, and a second polycrystalline silicon layer 17. Then, this second polycrystalline silicon layer 17 is applied to the P-type semiconductor substrate 1 as, for example, dummy word lines DW _{1 to 2} shown in FIG. 4A.
extends upward. The aluminum layer 19 connected to the N ⁺ type semiconductor region extends over the P type semiconductor substrate 1 as, for example, dummy data lines _1-1 shown in FIG. 4A.

MISFETQ _D2 in dummy cell D-CEL has its substrate, drain region, source region, gate insulating film, and gate electrode as P-type semiconductor region 1, N ⁺ -type semiconductor region 13, N ⁺ -type semiconductor region 14, gate insulating film 3, and They are each formed by a second polycrystalline silicon layer 18. In this polycrystalline silicon layer 18, for example, a dummy cell D-
The illustrated discharge signal φ _dc is applied within CEL. Connecting the second polycrystalline silicon layer 24 and the N ⁺ type semiconductor region 22 via the aluminum wiring layer requires a contact area between the second polycrystalline silicon layer 24 and its aluminum wiring layer,
Wiring density cannot be improved. Therefore, the above-mentioned connection means are employed to improve wiring density.

The other electrode of the capacitor C _B11 described above is constituted by an inversion layer formed on the surface of the semiconductor substrate 1. This inversion layer is formed by the voltage applied to the second polycrystalline silicon layer 25. And the first
Although not shown in FIG. 1, this inversion layer is connected to an N ⁺ type semiconductor region formed in the semiconductor substrate 1 to which the active restore control signal φ _rs of FIG. 4A is applied.

The second polycrystalline silicon layer 26 is one electrode of the capacitor C _B12 shown in FIG. 4A, and a part of it is shown in FIG. 4A like the capacitor C _B11 .
It is directly connected to the source region of MISFETQ _S5 , and the other part is continuously connected to the gate electrode of MISFETQ _S7 .

[Partial element structure of peripheral circuit (active restore)]

FIG. 11 is a partial perspective cross-sectional view showing the structure of some elements in a peripheral circuit formed around the memory array M-ARY, for example, the active restore AR ₁ shown in FIG. 4A. In Fig. 11, especially 20~
23 is an N ⁺ type semiconductor region, 24 to 27 are second polycrystalline silicon layers, and 28 is an aluminum layer.

In active restore AR ₁ shown in Figure 4A.
MISFETQ _S6 has a substrate, a source region, a drain region, a gate insulating film, and a gate electrode made of P-type semiconductor substrate 1, N ⁺ type semiconductor region 20, N ⁺ type semiconductor region 21, gate insulating film 3, and second polycrystalline silicon. Each layer is composed of layers 24.

MISFETQ _S4 in Active Restore AR ₁ is
The substrate, source region, drain region, gate insulating film and gate electrode are P-type semiconductor substrate 1, N ⁺
type semiconductor region 22, N ⁺ type semiconductor region 23, gate insulating film 3, and second polycrystalline silicon layer 27, respectively. The active restore control signal φ _rg shown in FIG. 4A is applied to the second polycrystalline silicon layer 27.

Capacitor C _B11 in Active Restore AR ₁
In this case, one electrode and the dielectric layer are respectively constituted by the second polycrystalline silicon layer 25 and the gate insulating film 3. This second polycrystalline silicon layer 25
The second one used as the gate electrode of MISFETQ _S6
It is continuously connected to the polycrystalline silicon layer 24. Further, a portion 25a of this second polycrystalline silicon layer 25 is directly connected to the N ⁺ type semiconductor region 22 of MISFETQ _S4 . Because dummy cell D
- The capacitor C _ds in the CEL has one electrode, a dielectric layer, and the other electrode connected to the first polycrystalline silicon layer 15, the gate insulating film 3, and the N-type surface inversion layer 16.
Each is composed of: That is, since the power supply voltage V _CC is applied to the first polycrystalline silicon layer 15 , this power supply voltage V _CC causes an N-type on the surface of the P-type semiconductor substrate 1 due to the electric field effect via the gate insulating film 3 . A surface inversion layer 16 is induced.

Next, FIG. 12 shows a circuit configuration of a specific embodiment of the main part of the RC-DCR shown in FIG. 4A.

The M-ARY and D-ARY word lines are shared through word line selection switches MISFETT ₂₀ to T ₂₉ . These word line selection switches
Between the gates of MISFETT ₂₀ to _T29 and R-DCR, so-called cuts MISFETT ₃₀ to _T39 , each having a power supply voltage V _CC applied to its gate, are provided.

The common word line shared through the MISFETT ₂₀ to _T29 is connected to a pulse generation circuit (hereinafter referred to as _φX -GENE) that supplies _the common word line and the word line control signal φ _X -GENE
A booster circuit (hereinafter referred to as _φ
It is called. ) are combined.

In order to operate the above φ _X −BOOS, the above _φ
- A control signal φ _pad that is substantially phase-shifted with respect to the control signal φ _X output from -GENE is required. Although not particularly limited, the above control signal φ _pad
As shown in the figure, is formed by a delay circuit (hereinafter referred to as _φX -DELAY) which receives the control signal _φX and forms a delayed signal with respect to the control signal φX.

φ _X −BOOS in this example is φ _X −
In order to reduce the load capacity of GENE, the following configuration is adopted. In other words, between the common word line which is the output line of _φX -GENE and the circuit connection point _N1
MISFETT ₅₁ will be provided. A power supply voltage V _CC is applied to the gate of the MISFETT ₅₁ . A Pootstrap capacitor C _B21 made of an MIS capacitor is provided between the circuit connection point _N1 and the circuit connection point _N2 .

Further, a MISFETT ₅₂ is provided between the common word line and the circuit connection point _N3 , and its gate is connected to the circuit connection point _N1 .

Between the above circuit connection point _N3 and circuit connection point _N2 , there is a putotstrap capacitor composed of an MIS capacitor.
C _B22 is provided.

A MISFETT ₅₃ connected in the form of a diode is provided between the circuit connection point T ₃ and the power supply voltage V _CC to precharge the Putstrap capacitance C _B22 . The pulse signal φ _pad formed by φ _x −DELAY as described above is applied to the circuit connection point N ₂ .

The basic operation of this embodiment circuit can be explained as follows.

When _{the word line control signal φ} Charge up to _th . However, V _th is
This is the threshold voltage of MISFET (the same applies below). In addition, at this time, the Pootstrap capacitance C _B21 is
Because it is being discharged through MISFETT ₅₁ ,
MISFETT ₅₂ is turned off. Therefore,
The MISFETT ₅₂ does not act to lower the potential at the circuit connection point _N3 .

Next, for example, the gate of the word line selection switch MISFETT ₂₀ selected by R-DCR is
A word line selection signal will be applied via MISFETT ₃₀ . MISFETT ₂₀ above accordingly
is turned on because a channel region is induced on the surface of the semiconductor substrate under its gate electrode.
At this time, the common word line and the
The word line selected by MISFETT ₂₀ is still at the low level, which is substantially the ground potential of the circuit. The MISFETT ₂₀ has a relatively large gate-channel capacitance because a channel region is induced under the gate electrode as described above. V _CC − to the gate electrode via MISFETT ₃₀
Since a potential of V _th is given, the above MISFETT ₂₀
The gate-channel capacitance of will be charged up to V _CC −V _th .

Next, the word line control signal _φX is raised from the above-mentioned low level to the V _CC level by _φX -GENE. Accordingly, the above word line selection switch
The channel potential of MISFETT ₂₀ is raised. As described above, since the capacitance between the gate and the channel is charged up to V _CC -V _th in advance, the gate potential of the MISFETT ₂₀ is raised to, for example, V _CC +V _th or more.

By increasing the gate potential in this way, MISFETT ₂₀ is fully turned on. Accordingly, despite the presence of a threshold voltage at MISFETT ₂₀ , the potential of word line W ₁ will be raised to a potential approximately equal to the common word line potential V _CC . At this time, MISFETT ₃₀ has its gate electrode connected to the power supply voltage.
Since the electrode _E1 is maintained at approximately V _CC by R-DCR, _the above
When the potential of its electrode E ₂ is increased by increasing the gate potential of MISFETT ₂₀ as described above,
turned off. Therefore, the above MISFETT ₂₀
The gate potential of continues to be maintained at the above-mentioned high voltage. Note that the increase in gate potential as described above causes MISFETT ₂₂ to select dummy word line DW ₁ .
It also occurs in

As mentioned above, when the V _CC level of the word line _control signal _φ
Through this, the bootstrap capacitance CB ₂₁ is charged up. Note that the charge level at this time is V _CC −V _th . Furthermore, at this time
MISFETQ ₅₂ has its gate potential at circuit connection point N ₃
It remains in the OFF state because it is simply brought to almost the same potential as that of .

φ _X - Pulse signal φ _pad for operating BOOS
is due to the operation of φ _X −DELAY as described above,
_The control _{signal φ}

As mentioned above, since the putot strap capacitors CB ₂₁ and CB ₂₂ are charged, the potentials at the circuit connection points N ₁ and N ₃ are increased by raising the signal φ _pad to the V _CC level. I am made to do so. At this time, MISFETT ₅₁ is turned off by the same operation as MISFETT ₃₀ . Therefore, the high potential at the circuit connection point _N1 is maintained as it is.

MISFETT ₅₂ has its gate electrode brought to a high potential by the putotstrap capacitor CB ₂₁ , so that
turned on. At this time, MISFETT ₅₂
The electrode E ₂ coupled to the common word line of is the electrode coupled to its gate electrode and the circuit connection point N ₃
Since E ₁ is brought to a high potential, it will act as a source electrode.

The high voltage at the above circuit connection point N ₆ is
It is supplied to the common word line via MISFETT ₅₂ and further to the word line via the selection switch MISFETT ₂₀ . That is, based on the signal φ _pad , the potentials of the common word line and the selected word line are further increased from the approximately V _CC level determined in advance by φ _X -GENE. .

Note that the gate potential of the selection switch MISFETT ₂₀ is further raised by raising the potential of the common word line from V _CC by the same operation as described above. Therefore, the above selection switch
MISFETT ₂₀ is fully turned on.

In the above boost operation, the charges in the putot strap capacitor CB ₂₂ are distributed to the parasitic capacitances C ₁ to C ₃ existing in the common word line selection word line and the dummy word line.
Therefore, the amount of potential increase on the selected word line is a value determined by the total capacitance consisting of the above-mentioned pulley strap capacitor CB ₂₂ and the parasitic capacitance, and the charge pre-charged in the pulley strap capacitor. Become.

In an IC, the MIS capacitor uses a semiconductor region formed on a semiconductor substrate as one electrode, and a conductor layer formed on this semiconductor region via a relatively thin insulating film as the remaining electrode. The structure is such that In this case, the configuration is such that there is only one electrode. In this case, the semiconductor region as one electrode usually forms a relatively large parasitic capacitance with the semiconductor substrate. Therefore, in order to achieve sufficient push operation, the push strap capacitances CB ₂₁ and CB ₂₂ in FIG.
The electrode formed by the semiconductor region is _φ
Preferably combined with DELAY.

The potential of the data line, which has been set to a high level such as the power supply potential V _CC by the active restore operation etc., is changed to the potential of the word line, which is set to a high level such as the power supply potential V _CC as described above.
By raising the voltage above the threshold voltage of the switch MISFET in the memory cell, the MIS capacitance is supplied without being lowered by the threshold voltage of the switch MISFET in the memory cell.

That is, the MIS capacitor in the memory cell is charged to a voltage approximately equal to the potential V _CC of the data line. In this way, by increasing the data writing level in the memory cell, it is possible to improve the S/N ratio of the D-RAM, and it is also possible to prevent memory malfunctions caused by the well-known alpha rays. can.

Needless to say, when word line boosting is not performed, that is, when the high level of the word line is set to approximately V _CC , even if the high level of the data line is set to V _CC , the MIS capacitance in the memory cell will increase. is the threshold voltage of the switch MISFET, V _th
Therefore, only a voltage of V _cc −V _th can be applied. Correspondingly, high SN in D-RAM
It becomes difficult to obtain a ratio. Also, D-RAM is
Alpha rays can cause malfunctions.

As is clear from the above, in data write operation or data rewrite operation, almost
In order to write the data on the data line set to the high level of V _CC into the memory cell with a sufficient level, the selected word line must be at least
It must be made to exceed V _CC +V _th .

As mentioned above, the amount of increase in word line potential that occurs as a result of the boost operation is reduced by charge dispersion. In order to sufficiently increase the word line potential rise, the putot strap capacitor CB ₂₂ must have a relatively large capacitance, for example, one to two times the capacitance value of the sum of the above parasitic capacitances C ₁ to C ₃ . Must be a value. By the way, 64K bit RAM
In this case, the sum of the above parasitic capacitances C ₁ to C ₃ is
It is about 22PF. Accordingly, the bootstrap capacitance CB ₂₂ is set to, for example, about 30PF.

In addition, in FIG. 12, the putot strap capacitor CB ₂₁ only needs to increase the potential at the circuit connection point N ₁ during boost operation.
Even considering the parasitic capacitance (not shown) between the electrode E ₁ of MISFETT ₅₁ and the semiconductor substrate and the gate capacitance of MISFETT ₅₂ , the capacitance may be relatively small, such as several PF.

In order to increase the potential of the common word line, word line, etc., _φ
Instead of BOOS, common word line and φ _X −DELAY
A circuit can be used in which a Puttstrap capacitance is placed directly between In this case, the putot strap capacitance will be directly precharged by φ _x -DENE, and the potential of the common word line, word line, etc. will be increased by φ _x -DELAY.

However, as mentioned above, since the putotstrap capacitance must be made relatively large, such a putotstrap circuit _has
This will place a very heavy load on GENE. Correspondingly, it becomes difficult to speed up the rise of the control signal _φX , and as a result, it becomes difficult to obtain a D-RAM with a fast access time.

On the other _hand , in _{the φ} , and the charge up has been done in advance by another route (MISFETT ₅₃ ). Therefore,
The load on φ _x -GENE is assumed to be relatively light as determined by the parasitic capacitances C ₁ and C ₂ .

Therefore, the rise speed of the word line control signal _φ
The operating cycle of RAM can be shortened, and its high-speed operation can be realized.

In the embodiment of the present invention, dummy word line selection switches MISFETT ₄₀ and T ₄₁ are provided between the output terminals of R-DCR to MISFETT ₂₈ and T ₂₉ and the reference potential, which are controlled by the pulse signal φ _pad . These MISFETT ₄₀ and T ₄₁ are designed to select dummy word lines by focusing on the fact that there is no need to raise the potential of the word line to which the dummy cell belongs at the operation timing of _φX -BOOS, in other words, at the operation timing of active restore. Provided to turn off switches MISFETT ₂₈ and T ₂₉ . That is, the active restore operation is to raise the data line, which is at the potential of V _H read by SA, to the V _CC level and rewrite the high level into the memory cell. Therefore, writing to the dummy cell as described above has no special significance. Dummy word line selection switch MISFETT ₂₈ , T ₂₉ (one side) as described above
The parasitic capacitance that is dispersed from the putot strap capacitor CB ₂₂ due to the off state of the MISFET (MISFET is turned off by the non-select output signal of R-DCR) is divided into the common data line capacitance C ₁ and the word line parasitic capacitance.
Can only be C ₂ . This allows the capacitance value of the Putstrap capacitor CB ₂₂ to be reduced,
As a result, it is possible to reduce power consumption,
Furthermore, the size of the Putstrap capacitor CB ₂₂ can be reduced.

Note that the configuration in which the dummy word lines are separated as described above can also be adopted in the circuit configuration in which the putot strap capacitance is directly coupled to the common word line as described above. That is, the above
By inserting MISFETT ₄₀ and T ₄₁ , it is possible to reduce the capacitance value of parasitic capacitance coupled to the putostrap capacitance during active restore.
This means that the capacitance value of the Putstrap capacitor can be reduced. Accordingly, the load capacity for _φX -GENE can be reduced, and its rise can be made faster. However, in this example, _φ
It goes without saying that when combined with BOOS, it is even more effective.

In another embodiment of the present invention, a pulse generation circuit (hereinafter referred to as φ _{Y −}
It is called GENE. ) is also provided with a booster circuit (hereinafter referred to as φ _Y -BOOS) similar to the above.

That is, the pair of data lines are connected to the pair of common input/output lines via column selection switches _MISFETQ11 , ₁₁ . Column selection switch above
The gates of _MISFETQ11 , ₁₁ to _Q12 , ₁₂ are connected to the common column line via column address switches _MISFETQ1-1 , _Q1-2 . The gates _of the column address switches MISFETQ _1-1 and Q _1-2 are connected to _the C-
Connected to DCR. The above cut MISFETT ₁₅ ,
Power supply voltage V _CC is applied to the gate of T ₁₆ .

A column switch control signal φ _Y formed by φ _Y −GENE is applied to the common column line.
And this common column line has φ _Y −BOOS
and a delay circuit (hereinafter referred to _as φ _{Y −}
It is called DELAY. ) is provided. This pulse signal φ _nad is used for the putot strap operation of φ _Y -BOOS.

φ _Y -BOOS can be constructed simply by the Puttstrup capacitance. The reason for this is
This is due to the small load capacity of φ _Y -GENE. That is, the load on φ _Y -GENE is only the parasitic capacitance of the common column line and the gate capacitance of the selected column selection switches MISFETQ ₁₁ , ₁₁ , etc., and is smaller than the load on φ _X -GENE. By the way, for 64K bit RAM,
The capacitance value of the above load is about 7 pF.

The operation of this circuit is almost the same as the operation of φ _Y -BOOS. In other words, this circuit sets the gate voltage of column selection switch MISFETQ ₁₁ , ₁₁ to V _CC
Raise it above the level. MISFETQ ₁₁ above,
_Q11 depends on its gate voltage, its source,
The drain-to-drain impedance is sufficiently reduced. Furthermore, the data signal at the V _CC level supplied from the DIP is supplied to the data line without being lowered in level by the threshold voltage V _th of the MISFETQ ₁₁ , ₁₁ . Similarly, the data on the data line is MA without experiencing any level drop.
&DOB will be supplied. As a result, it is possible to improve the transmission speed of data exchange through the column selection switches MISFETQ ₁₁ , ₁₁ .

In another embodiment of the invention, a circuit similar to φ _X -BOOS in FIG. 12 is used as φ _Y -BOOS. In this case, φ _Y −
Since the Pootstrap capacity can be separated from the GENE, the load on the φ _X -GENE can be reduced. Accordingly, it is possible to obtain the effect that the rising speed of φ _Y can be increased. In addition, due to the lightening of the load, φ _Y −
Since the output current capacity of GENE can be reduced, φ _Y
-It is also possible to reduce the chip size of GENE's output MISFET.

φ _Y −BOOS and the φ _X − as described above and above.
In combination with BOOS, it is possible to improve the transmission speed of data exchange as described above, and it is also possible to raise the high level written to the memory cell to the V _CC level as described above. That is, φ _X −BOOS and φ _Y −BOOS
The word line selection level is set to V _CC + by the operation of
V _th or more, the column selection switch
Column selection level of MISFETQ ₁₁ , ₁₁ etc. is V _CC
+V _th or more, and a write high level of V _CC level is transmitted to the data line. Therefore, the S/R during the period from write to read or refresh operation in D-RAM is
This can be effective in improving N and taking measures against alpha rays.

FIG. 13A shows a specific circuit diagram of one embodiment of the improved φ _X -BOOS, and FIG. 13B shows its operating waveform diagram. pulse signal
RAS ₁₁ and ₁₃ are RAS formed by RAS-SG
It is one of the system signals, and is, for example, a delayed signal of ₁ formed by RAS-CT.

In this embodiment, a pulse signal ₁₃ is applied to the gate to bring the precharge level to the push strap capacitor CB ₂₁ to the V _CC level.
Power supply voltage V _CC is applied to the gate of MISFETT ₅₁ via MISFETT ₅₄ . In order to turn off the MISFETT ₅₁ during push trap, a MISFETT ₅₅ to which a pulse signal φ _pad is applied is provided between the gate of the MISFETT ₅₁ and the reference potential point.

As a result, as shown in FIG. _13B , when _the pulse signal ₁₃ is at a high level and the word _{line control} signal _φ High level is applied. This will result in the above MISFETT ₅₁
A channel is induced under the gate electrode. At this time, the word line control signal _φX maintains a low level. Therefore, the capacitance between the gate electrode and the channel is
Precharged to V _CC −V _th .

After that, the pulse signal ₁₃ is set to low level. This turns MISFETT ₅₄ off.
Next, word line control signal _φX rises to the V _CC level. Since this V _CC level is transmitted to the channel of the MISFETT ₅₁ , the gate voltage of the MISFETT ₅₁ rises above V _CC +V _th . By setting its gate voltage to V _CC +V _th , MISFETT ₅₁ becomes
The word _line control signal _φ
The V _CC level can now be transmitted to the Putstrap capacitor CB ₂₁ . Therefore, the putot strap capacitor CB ₂₁ is precharged by the V _CC level of the word line control signal.

Next, the pulse signal φ _pad is raised to the V _CC level. Then MISFETT ₅₅ turns on and
MISFETT ₅₁ is turned off. As a result, the putot strap capacitor CB ₂₁ is not discharged to the common word line through the MISFETT ₅₁ , so that the gate voltage of the MISFETT ₅₂ can be increased to, for example, approximately 2V _CC by the rise of the pulse signal φ _pad .

In addition, in this example, the gate voltage of MISFETT ₅₁ does not need to be raised above V _CC +V _th , and it is turned on by the pulse signal φ _pad .
By making the fall of the gate voltage of MISFETT ₅₁ faster due to MISFETT ₅₅ , the putot strap capacitance CB ₂₁
In order to reduce charge leakage to the common word line, a diode-type MISFETT ₅₆ is provided between the gate of the MISFETT ₅₁ and the power supply voltage terminal V _CC . Due to this operation of MISFETT ₅₆ ,
The putot strap voltage at the gate of MISFETT ₅₁ is clamped to V _CC +V _th .

In addition, as mentioned above, the pulse signal φ _pad
If MISFETT ₅₁ is turned off,
If no discharge path is provided for the gate charge of MISFETT ₅₂ , when the pulse signal φ _pad is returned to low level, the voltage of approximately V _CC will be maintained at the gate of MISFETT ₅₂ . .

If the MISFETT ₅₂ remains on in this way, when the common word line is reset to low level by the pulse signal ₁₁ , that is, the pulse signal ₁₁ is set to high level, and that level turns the MISFETT ₅₀ on. In this case, the common word line is coupled with a putot strap capacitor via MISFETT ₅₂ , which slows down the level fall of the common word line, and also causes precharge to the common word line.
A current is drawn from the supply voltage through the MISFETT ₅₃ , which has the disadvantage of impairing the charging of the Putstrap capacitor and increasing the power consumption of the circuit.

Therefore, in FIG. 13A, in order to discharge the Puttstrap capacitance CB ₂₁ as shown,
A MISFETT ₅₈ controlled by pulse signal ₁₁ is provided as shown. Also, this
Connected in series with MISFETT ₅₈ and supply voltage at gate
MISFETT ₅₉ to which V _CC is applied is provided for high resistance to prevent punch-through from occurring in MISFETT ₅₈ due to the high voltage of approximately 2V _CC at the connection point N ₁ during the above-mentioned pull strap operation. .

By adding such _a circuit, the V _CC level of the _word line control _{signal φ 51}
Since the charge of the putotstrap capacitor _CB21 is less likely to leak to the common word line via the capacitor CB21, the capacitance value of the putotstrap capacitor _CB21 can be reduced. Therefore, the load on _φX GENE can be further reduced.

In other embodiments, the Pootstrap capacity
To increase the precharge level to CB ₂₂ to the V _CC level, the following booster circuit is provided in MISFETT ₅₃ . In other words, there is a diode between the gate of MISFETT ₅₃ and the power supply voltage terminal V _CC .
A putotstrap capacitor CB ₂₃ is provided between MISFETT ₅₇ , the gate of MISFETT ₅₃ , and circuit connection point _N4 . Then, the pulse signal ₁₃ is applied to the circuit connection point _N4 .

In the operation of this circuit, the putotstrap capacitor CB ₂₃ is precharged via the MISFETT ₅₇ while the pulse signal ₁₃ is at a low level.
And, due to this pre-charge operation,
The gate potential of MISFETT ₅₃ becomes V _CC −V _th . For this reason, as explained below, the putotstrap capacity
When the precharging to CB ₂₂ is completed and the potential at the circuit connection point N ₃ is rising to approximately 2V _CC level, MISFETT ₅₃ is off. That is, the precharge to the putotstrap capacitance CB ₂₂ and the previous D- of the putotstrap operation.
During the RAM selection cycle, the putotstrap capacitor CB ₂₃ is precharged. Then, D
- Pulse signal ₁₃ is set to high level when RAM is not selected. As a result, the gate voltage of MISFETT ₅₃ rises above V _CC +V _th , so the putot strap capacitance CB ₂₂ increases through MISFETT _53.
Charged up to V _CC level. after that,
When D-RAM is selected and the pulse signal ₁₃ falls to a low level, MISFETT ₅₃ is turned off, and the power supply voltage V _CC is precharged to the Putstrap capacitor CB ₂₃ via MISFETT ₅₇ for the next operation. Ru. By the above operation, the charge up of the putostrap capacitor CB ₂₂ to the V _CC level is completed, so next the pulse signal φ _pad is
When the voltage rises to the V _CC level, the potential at the circuit connection point N ₃ can be raised to approximately 2V _CC .

Note that MISFETT ₅₂ is on at this time. Therefore, charge is distributed between the common word line and the parasitic capacitances C ₁ to _{C 3} of the word line and the above-mentioned pull-out strap capacitance CB ₂₂ , and the potential of the common word line and the word line is determined by the charge between these capacitances. The voltage increases to a voltage determined by the dispersion.

In this example, the Pootstrap capacity CB ₂₂
It is possible to increase the pre-charge level to.
Therefore, the required voltage to the word line V _CC
The capacitance value of the Pootstrap capacitor BC ₂₂ for obtaining +V _th can be reduced. As a result, the chip size of the Putstrap capacitor CB ₂₂ can be reduced. Furthermore, when this embodiment is combined with the circuit shown in FIG. 12 for isolating the dummy word line during the put-strap operation, there is an effect that the capacitance value of the put-strap capacitor CB ₂₂ can be further reduced.

Further, the booster circuit provided in the MISFETT ₅₁ and the booster circuit provided in the MISFETT ₅₃ each have their own effects. Therefore, only one of them may be provided in the basic circuit shown in FIG.

In the circuit diagram of Figure 13A, MISFETs marked with an asterisk (*) have a lower threshold voltage V _th than MISFETs not marked with an * in order to reduce power loss between their source and drain. is set small. Also, the MIS capacitors marked with * are the MIS capacitors marked with *, in order to ensure that the potential of the gate side electrode rises quickly when a high-level signal is applied to the substrate side electrode. Its threshold voltage is set lower than that of .

The method for manufacturing the MISFETs marked with * will be explained later using FIGS. 19I and 19J and FIGS. 22A and 22B. The MIS capacitors marked with * above can also be manufactured in the same manner as the above MISFET.

FIG. 14A shows a specific circuit diagram of one embodiment of the improved φ _X -BOOS, and FIG. 14B shows its operating waveform diagram. pulse signal
CAS ₁₁ and ₁₃ are one of the CAS signals formed by CAS-SG, and are signals obtained by delaying the signal formed by C-CT.

The circuit configuration of φ _Y -BOOS shown in FIG. 14A is substantially the same as the circuit configuration of φ _X -BOOS shown in FIG. 13A, so a description thereof will be omitted. However, this φ _Y -BOOS is different from the _above - _mentioned φ In other words, the common column line is reset by pulse signals ₁₁ ,
RAS ₁₂ was applied to each gate
MISFETT ₆₀ , T ₆₀ is used to reset the putotstrap capacitor CB ₃₁ using a pulse signal.
RAS ₁₂ , ₁₁ applied to the gate
MISFETT ₆₈ , T ₆₉ .

This is because uncertain data may be erroneously written to the memory cell when there are conditions related to the timing of the signals, and to prevent this, the pulse signal is
The common column lines, etc. are reset using RAS ₁₂ and ₁₁ .

The operation of φ _Y -BOOS is substantially the same as the operation of φ _X -BOOS, so a description thereof will be omitted.
With this example circuit, the Puttstrap capacitance
Capacitance values of CB ₃₁ and CB ₃₂ can be reduced, etc. φ _X −
The same effect as in BOOS can be expected.

FIG. 15 shows a circuit diagram of a decoder for selecting a row (word line) of a memory array, showing another embodiment of the present invention.

In this embodiment, the row decoder is divided into two stages, like the decoder for selecting columns of the memory array described above. That is, R-
By matching the horizontal spacing (pitch) of the NOR gates that make up the DCR to the pitch of the word line arrangement of the memory array, unnecessary blank areas are prevented from occurring within the IC chip.

For this purpose, multiple word lines drawn out from the memory array are selected by word line selection switches.
Rather than being all commonly coupled to one common word line via MISFETT ₂₀ to T ₂₇ , respectively, they are divided into four word lines.
That is, the common word lines are sequentially shared by four divided common word lines. The gates of the word line selection switches MISFETT ₂₀ to T ₂₃ and T ₂₄ to T ₂₇ connected to different common word lines are connected to the cut MISFETT ₃₀ to T ₃₃ and T ₃₄ , respectively.
It is commonly connected to the outputs of row decoder circuits R-DCR1 and R-DCR2, which are composed of NOR gates, through _T37 . Therefore, for example, when a row selection signal is formed at the output of R-DCR1, MISFETT ₂₀ to _T23 are turned on and four word lines are selected. Since only one word line control signal (for example, φ _x00 ) is selected from the common word lines, only one word line is selected for the memory array.

The row switch selector (hereinafter referred to as RSW-) forms such word line control signals _φX00 to _φX11 .
(referred to as S).

Therefore, for example, the row address signal _a
a Of _X6 and _X0 ~ _X6 , row address signal a _X0 ~
a _X1 is input to RSW-S, row address signal
_aX2 to _X6 are input to R-DCR, and word line selection as described above is performed.

In other words _, RSW- _{S is an operation of transmitting the word line control signal φ X formed} by _φ This is what we do.

In this case, if _the word line control signal _φ
The high level of V _CC +V _th cannot be transmitted to the selected common word line and word line.

Therefore, when φ _X −BOOS is provided, the first
The circuit shown in the embodiment of FIG. 6 is used.

This embodiment circuit is a circuit for selecting one common word line, and four sets of similar circuits (different only in row address signals) are provided to form an RSW-S.

The configuration of this example circuit can be explained as follows. Pulse signal _Xdp was applied to the gate
The drain of MISFETT ₇₄ is connected to the power supply voltage terminal V _CC . MISFETT ₇₀ and T ₇₁ are provided in parallel between the source and the reference potential terminal.
Row address signals a _X0 and a _X1 are applied to the gates of MISFETT ₇₀ and T ₇₁ , respectively. Also,
MISFETT ₇₆ is provided between the gate of MISFETT ₇₇ and the power supply voltage terminal V _CC . The pulse signal _Xdp is applied to the gate of MISFETT ₇₆ .
A word line control signal _φX is applied to the input side source or drain of the MISFETT ₇₇ . and,
A parallel connection is made between the source or drain, which is the output side of MISFETT ₇₇ , and the reference potential terminal.
MISFETT ₇₂ and T ₇₃ are provided. MISFETT ₇₂ ,
Each row address signal is connected to the gate of _T73 .
a _X1 and a _X0 are applied.

Further, a MISFET ₇₈ is provided between the source or drain on the output side of the MISFETT ₇₇ and a reference potential terminal, and the pulse signal ₁₂ is applied to the gate. Additionally, the source of MISFETT ₇₄ and
MISFETT ₇₅ is provided between the gates of MISFETT ₇₇ . The gate of MISFETT ₇₅ has a supply voltage
V _CC is applied. In this example circuit, the MISFETs marked with * are set to low threshold voltages as described above.

The operation of this circuit will be explained next with reference to the operational waveform diagram in FIG.

The above pulse signals _Xdp and ₁₂ are respectively
This is one of the RAS signals formed by RAS-SG, and is a delayed signal of the signal formed by RAS-CT.

When RSW-S is not selected, the pulse signal _Xdp is set to high level. Therefore, node T ₅ becomes V _CC −
Precharged to V _th .

Thereafter, when the potential of at least one of the row address signals _aX0 and _aX1 becomes, for example, a high level, the node _T5 is discharged and the potential of the word line control signal _φX00 becomes the ground potential of the circuit. That is, the word line control signal φ ₀₀
becomes unselected.

On the other hand, if the potentials of the row address signals a _X0 and a _X1 are at low level,
Thereafter, the level of the control signal _φX becomes equal to or higher than V _CC +V _th , so that the level of the word line control signal φ _X00 becomes equal to or higher than V _CC +V _th . That is, the above-mentioned _φX00 is in the selected state. At this time, the gate voltage _of MISFETT ₇₈ is charged up to V _CC -V _th between the gate and the substrate when the level _{of φ} ), so
V _CC +2V _th or more. As a result, as described above, the level of word line control signal _φX can be transmitted almost unchanged to word line control signal _φX00 .

In addition to the D-RAM described above, the Pooster circuit according to the present invention can reduce the load on the pulse generation circuit in which the Pooster circuit is provided.
It is widely available for general use.

[Memory array and dummy array layout pattern]

Memory array M-ARY and dummy array D
-The layout pattern of ARY will be explained according to FIG. 18A.

The memory array M-ARY shown in FIG. 18A has a plurality of memory cells M-CEL shown in FIG. 9 arranged on the semiconductor substrate 1. On the other hand, the first
The dummy array D-ARY shown in FIG. 8A has a plurality of dummy cells D-CEL shown in FIG. 10 arranged on the semiconductor substrate 1.

First, the memory array M- shown in FIG. 19A
ARY is structured as follows.

On the surface of the semiconductor substrate 1, a plurality of memory cells M- each composed of a MISFET Q _M and a storage capacitor C _S are formed.
In order to isolate the CELs from each other, a field insulating film 2 is formed based on the pattern shown in FIG. 18Aa.

Unlike this basic pattern rule, a field insulating film 2a is exceptionally arranged below the contact hole _CH0 for applying the power supply voltage _VCC to the first polycrystalline silicon layer 6. Therefore,
The aluminum-silicon alloy formed due to the interaction between the aluminum layer and the polycrystalline silicon layer near this contact hole CH ₀ penetrates the insulating film directly under the contact hole CH ₀ and undesirably forms on the surface of the semiconductor substrate 1. Accidents such as reaching the target can be prevented.

This field insulating film 2 and gate insulating film 3
A first polycrystalline silicon layer 6 used as one electrode of the storage capacitor C _S in the memory cell M-CEL is formed thereon based on the pattern shown in FIG. 18Ab.

Further, on the first polycrystalline silicon layer 6, an 18th
A word line formed by the second polycrystalline silicon layer 8 in FIG. 9 along the vertical direction in FIG.
WL _1-1 to WL _1-6 extend.

Further, a power supply line V _CC -L for supplying the power supply voltage V _CC to the polycrystalline silicon layer 6 as one electrode of the storage capacitor C ₈ through the contact hole CH ₀ is provided as shown in FIG. 11A. It extends in the horizontal direction.

On the other hand, the data lines DL _1-1 , _1-1 formed by the aluminum layer 10 in FIG.
As shown in FIG. 18A, the power supply line V _CC -L
extends almost parallel to the The data line DL _1-1 is connected to the drain region of the MISFET Q _M in the memory cell M-CEL through the contact hole CH ₁ , and the data line DL _1-1 is connected to the drain region of the MISFETQ M in the memory cell M-CEL through the contact hole CH ₂ . Connected to the drain region of MISFETQ _M inside. In addition, data lines DL _1-2 ,
DL _1-2 is the 18th line like data lines DL _1-1 and _1-1 .
Extending in the horizontal direction of Figure A, the contact hole in the memory cell M-CEL is inserted through a contact hole at a predetermined portion.
Connected to the drain region of MISFETQ _M.

Next, as shown in FIG. 18A, the dummy cell D-CEL
is structured as follows.

A field insulating film 2 is formed on a part of the surface of the semiconductor substrate 1, and a gate insulating film 3 is formed on the other part of the surface of the semiconductor substrate 1.

On the field insulating film 2 and gate insulating film 3, first polycrystalline silicon layers 15a and 15b extend apart from each other along the vertical direction shown in FIG. 19A. This first polycrystalline silicon layer 15a, 15
The width of b is the capacitor d in dummy cell D-CEL.
This is extremely important in determining the capacitance value. An N ⁺ -type semiconductor region 14 shown in FIG. 11 is located between the first polycrystalline silicon layer 15a and the first polycrystalline silicon layer 15b. This N ⁺ type semiconductor region 14 is used as a common ground line for a plurality of dummy cells D-CEL.

Furthermore, a dummy word line DWL _1-1 formed by the second polycrystalline silicon layer 17 in FIG. 10 extends over the first polycrystalline silicon layer 15a. This dummy word line DWL _1-1 constitutes the gate electrode of MISFETQ _D1 in the dummy cell D-CEL. On the other hand, the control signal line φ _dc -L1 formed by the second polycrystalline silicon layer 18 in FIG. 10 to apply the discharge control signal φ _dc shown in FIG. 4A is a dummy word line.
It is separated from and parallel to DWL _1-1 . This control signal line φ _dc −L ₂ is the dummy cell D
-Constitutes the gate electrode of MISFETQ _D2 in CEL.

Similarly, dummy word line DWL _1-2 and control signal line φ _de -L ₂ extend in parallel with dummy word line DWL _1-1 and control signal φ _de -L ₁ .

Then, further data lines DL _1-1 , _1-1 ,
DL _1-2 , _1-2 extend from memory array M-ARY as shown in FIG. _1-1 is connected to the dummy cell D-CEL through the contact hole CH ₃ .
Connected to the drain region of MISFETQ _D1 , _1-2
Similarly, other _D-
Connected to the drain region of MISFETQ _D1 in CEL.

[Peripheral circuit layout pattern]

FIG. 18B shows a layout pattern of a part of the peripheral circuit, for example, the sense amplifier _SA1 shown in FIG. 4A.

In FIG. 18B, AR is an active restore section, and PC is a data line precharge circuit section.

Two active restore units AR ₁ shown in FIG. 4A are arranged in the active restore unit AR. That is, one active restore is configured on the arrow A side shown in FIG. 18B, and another active restore is configured on the arrow B side. In this acti-restore unit AR, acti-restore control signal lines φ _rg -L, φ _rs -L and power supply voltage line V _{CC -L} , which are common to each acti-restore, are shown in FIG. 18B. It is arranged like this.

On the other hand, two data line precharge circuits corresponding to the two active restores described above are arranged in the precharge circuit section PC. and,
There is a potential line in this pre-charge circuit PC.
V _DP-L , the precharge control signal line φ _PC-L , and the data lines DL _1-1 , _1-1 , DL _1-2 , _1-2 extending to the memory array MA-ARY in FIG. 18A are the 18th
They are arranged as shown in Figure B.

MISFETs Q _S1 to _{Q S7} and capacitors C _B11 and C _B12 in FIG. 4A are arranged as shown in FIG. 18B.

[N-channel dynamic RAM manufacturing process]

The manufacturing process of the N-channel type dynamic RAM will be explained with reference to FIGS. 19A to 19T. In each figure, X ₁ is a _process sectional view _{of the} X _{1 -} Process sectional view of the cutting part, and
X ₃ is ActiRestore AR shown in Figure 18B.
It is a process cross-sectional view of the X ₃ - _{X 3} cut portion of .

(Oxide film and oxidation-resistant film forming step) As shown in FIG. 19A, an oxide film 102 and an oxygen-blocking insulating film, that is, an oxidation-resistant film 103, are formed on the surface of a semiconductor substrate 101.

Preferred specific materials for the semiconductor substrate 101, the oxide film 102, and the oxidation-resistant film 103 include a P-type single crystal silicon (Si) substrate having 100 crystals, a silicon dioxide (SiO ₂ ) film, and a silicon nitride (Si _{3 )} film.
N ₄ ) membranes are used respectively.

The SiO ₂ film 102 is formed to a thickness of about 500 Å by surface oxidation of the Si substrate 101 for the following reason. That is, when the Si ₃ N ₄ film 103 is directly formed on the surface of the Si substrate 101, the Si substrate 101 and
Due to the difference in thermal expansion coefficient from the Si ₃ N ₄ film 103, Si
Heat is applied to the surface of the substrate 101. Therefore, crystal defects occur on the surface of the Si substrate 101. To prevent this, the SiO ₂ film 10 is formed before forming the Si ₃ N ₄ film 103.
2 is formed on the surface of the Si substrate 101.

On the other hand, as will be described in detail later, the Si ₃ N ₄ film 103 is used as a mask for selective oxidation of the Si substrate 101 by, for example, chemical vapor deposition (CVD).
The film is formed to a thickness of approximately 1400 Å using the Deposition method.

(Selective removal of oxidation-resistant film and ion implantation process) Si ₃ N ₄ film 10 on the surface of the Si substrate 101 on which a relatively thick oxide film, that is, a field insulating film is to be formed.
In order to selectively remove the Si ₃ N ₄ film 1, the photoresist film 104 is first used as an etching mask.
selectively formed on the surface of 03. In this state,
For example, the exposed portion of the Si ₃ N ₄ film 103 is removed by plasma etching, which allows for highly accurate etching.
remove.

Next, in order to prevent a layer of the opposite conductivity type from that of the substrate, so-called inversion layer, from being formed on the surface of the Si substrate 101 where the field insulating film is formed.
As shown in FIG. 19B, impurities of the same conductivity type as the substrate, that is, P-type impurities, are introduced into the Si substrate 101 through the exposed SiO ₂ film 102 with the photoresist film 104 remaining. Ion implantation is preferred as a method for introducing this P-type impurity. For example, boron ion implantation energy, which is a P-type impurity,
It is implanted into the Si substrate 101 at 75keV. The ion dose at this time was 3×10 ¹² atoms/cm ³ .

(Field insulating film forming process) A field insulating film 105 is formed on the surface of the Si substrate 101.
selectively formed. That is, as shown in FIG. 19C, after removing the photoresist film 104,
Using the Si ₃ N ₄ film 103 as a mask, the surface of the Si substrate 101 is selectively oxidized by thermal oxidation to a thickness of approximately 9500 mm.
A SiO ₂ film 105 (hereinafter referred to as field SiO ₂ film) is formed. This field/SiO ₂ film 1
During the formation of 05, the ion-implanted boron is Si
A P-type anti-inversion layer (not shown) which is stretched and diffused in the substrate 101 and has a predetermined depth is formed directly under the field SiO ₂ film 105 .

(Oxidation-resistant film and oxide film removal process) In order to expose the surface of the Si substrate 101 where the field SiO ₂ film 105 is not formed,
The Si ₃ N ₄ film 103 is removed using, for example, hot phosphoric acid (H ₃ PO ₄ ) solution. Subsequently, the SiO ₂ film 102 is removed using, for example, a fusic acid (HF) solution, and the 19th D
As shown in the figure, the surface of the Si substrate 101 is selectively exposed.

A plan view of the memory array and dummy array with the Si ₃ N ₄ film 103 and SiO ₂ film 102 removed is shown in FIG. 20A, and a plan view of the peripheral circuit section is shown in FIG. 20B. That is, the cross _- sectional view when the substrate is cut along line X _1D in FIG. 20A is shown in the X ₁ section in FIG. A diagram is shown in the section X ₂ of FIG. 19D, and a cross-sectional view of the substrate taken along the line X _3D in FIG. 20B is shown in the section X ₃ of FIG. 19D.

(First gate insulating film forming step) Memory cell M-CEL and dummy cell D-
In order to obtain dielectric layers for capacitors C _{S and} C _ds in the CEL, a first gate insulating film 106 is formed on the exposed surface of the Si substrate 101 as shown in FIG. 19E.
That is, by thermally oxidizing the exposed surface of the Si substrate 101, a first gate insulating film 106 having a thickness of about 430 Å is formed on the surface. Therefore, the first gate insulating film 106 is made of SiO ₂ .

(First conductor layer deposition process) The first conductor layer 10 is used as one electrode of a capacitor in a memory cell and a dummy cell.
7 is formed on the entire surface of the Si substrate 101 as shown in FIG. 19F. That is, for example, a polycrystalline silicon layer 107 is formed as the first conductor layer 107 by the CVD method.
It is formed on the upper surface of the Si substrate 101. The thickness of this polycrystalline silicon layer 107 is about 4000 Å. Next, in order to reduce the resistance value of the polycrystalline silicon layer 107, an N-type impurity such as phosphorus is introduced into the polycrystalline silicon layer 107 by a diffusion method. As a result, the resistance value of the polycrystalline silicon layer 107 is approximately 16Ω/□.

(Selective removal step of first conductor layer) First conductor layer, that is, first polycrystalline silicon layer 10
In order to form electrode 7 into a predetermined shape, first polycrystalline silicon layer 107 is selectively removed by photoetching to form electrode 108, as shown in FIG. 19G. Plasma etching is suitable as a method for selectively removing the first polycrystalline silicon layer 107, as it allows for highly accurate etching. Subsequently, the exposed first gate SiO ₂ film 106 is also etched to partially expose the surface of the Si substrate 101.

First polycrystalline silicon layer 107 and first gate
FIG. 21A shows a plan view of the memory array and dummy array with the SiO ₂ film 106 selectively removed.
A plan view of the peripheral circuit section is shown in FIG. 21B. That is, a cross-sectional view when the substrate is cut along line X _1G in FIG. 21A is shown in the section X ₁ in FIG. 19G,
A cross-sectional view of the substrate taken along the line X _2G in FIG. 21B is shown in the X ₂ section of FIG.
A cross-sectional view of the substrate taken along line X _3G in FIG. 21B is shown in the section X ₃ in FIG. 19G.

(Second gate insulating film forming step) Memory array M-ARY, dummy array D-
A second gate insulating film 109 is formed on the exposed surface of the Si substrate 101 as shown in FIG. 19H to obtain a gate insulating film for the MISFET in the ARY and peripheral circuit section. That is, the exposed Si substrate 101
A second gate insulating film 109 having a thickness of about 530 Å is formed on the surface by thermally oxidizing the surface.
Therefore, the second gate insulating film 109 is made of SiO ₂ . Simultaneously with the formation of the second gate insulating film, that is, the second gate SiO ₂ film 109, the surface of the first polycrystalline silicon electrode 108 is also oxidized, and an SiO ₂ film 110 with a thickness of about 2200 Å is formed on the surface. This SiO ₂ film 110 serves as an interlayer insulating film between the electrode 108 and an electrode made of a second polycrystalline silicon layer, which will be described later.

(Low threshold voltage control ion implantation process) Has the low threshold voltage shown in Figure 4A.
In order to define the threshold voltages of MISFETQ _S1 to Q _S3 , Q _S6 and Q _S7 , P-type impurities are implanted into the substrate surface through the second gate SiO ₂ film 109 by ion implantation, as shown in FIG. 19I. Introduce. For example, boron is used as the P-type impurity. The implantation energy was 75keV and the ion dose was 2.4×10 ¹¹
Atom/cm ² is preferred.

Since no selection mask is used for ion implantation at this time, other MISFETs such as Q _M , Q _D1 ,
Boron is also introduced into the substrate surface area where Q _D2 , Q _S4 , and Q _S5 are to be formed.

(High threshold voltage control ion implantation process) Has a higher threshold voltage than MISFETQ _S1 to Q _S3 , Q _S6 and Q _S7 shown in Figure 4A.
MISFET, e.g. MISFETQ _M in memory cells,
In order to define the threshold voltage of MISFETQ _D1 , Q _D2 in the dummy cell or MISFETQ _S4 , Q _S5 during active restore, see Figure 19J and 2.
As shown in Figure 2B, the ion implantation mask, that is, the photoresist film 111, is applied to MISFETQ _S1 to Q _S3 ,
The second gate SiO ₂ in the channel region of Q _S6 and Q _S7
A photoresist film 111 is formed on the film 109 as shown in FIGS. 22A and 22B.
Boron ions are implanted in this state without being formed on the channel regions of MISFETQ _M , Q _D1 , Q _D2 , Q _S4 , and Q _S5 . The implantation energy is preferably 75 keV, and the ion dose is preferably 1.0×10 ¹¹ atoms/cm ² .

As a result, MISFETQ _M , Q _D1 , Q _D2 , Q _S4 and
Since the impurity concentration of the substrate surface where Q _S5 is to be formed is further increased, the threshold values of these MISFETs will have a high value.

FIG. 22A is a plan view of the memory array and dummy array in an ion-implanted state, and FIG. 22B is a plan view of the peripheral circuit section.

(Direct contact hole forming process) As explained using FIG.
The contact hole so-called direct contact CH ₁₀₀ for directly connecting one electrode 25 of C _B11 to the N ⁺ type semiconductor region 22 of MISFETQ _S4 is connected to the 19th
As shown in Figure K, the second gate SiO ₂ film is formed by selective etching using the photoresist film 112 as a mask.

The plan view of the memory array and dummy array at this time is shown in Figure 23A, and the plan view of the peripheral circuit section is shown in Figure 23A.
Shown in Figure 3B. In particular, as shown in Figure 23B, this direct contact hole CH ₁₀₀
It is installed between the part that should become MISFETQ ₄ and the part that should become capacitor C _B11 .

(Second conductor layer deposition step) A second conductor layer 113 is formed over the entire surface of the Si substrate 101 to be used as the gate electrode and wiring layer of all MISFETs. That is, the 19th L
As shown in the figure, a polycrystalline silicon layer, for example, is formed as the second conductor layer 113 over the entire surface of the Si substrate 101 by CVD. The thickness of this polycrystalline silicon layer 113 is approximately 3500 Å. Next, in order to reduce the resistance value, an N-type impurity, for example, phosphorus, is introduced into this polycrystalline silicon layer 113 by a diffusion method. As a result, the resistance value of the polycrystalline silicon layer 113 becomes approximately 10Ω/□. During such phosphorus treatment,
Phosphorus impurity is directly contact hole CH ₁₀₀
It is introduced into the Si substrate 101 through.

(Selective removal process of second conductor layer) Second conductor layer, that is, second polycrystalline silicon layer 11
3 is selectively removed into a predetermined electrode or wiring shape by photoetching. In other words, the 19th
As shown in FIG _{.
18th B _ _ _ _ _}
Active restore control signal line φ _rg − shown in the figure
L, electrode 114 of capacitor C _B11 , C _B12 or
Form the gate electrodes of MISFETQ _S1 to Q _S3 .

As shown in FIG. 18M, the exposed second gate SiO ₂ film 109 is further removed, and the Si substrate 1
FIG. 18A is a plan view of the memory array and dummy array in this state, and FIG. 24B is a plan view of the peripheral circuit section. That is, the second
A cross-sectional view obtained by cutting the substrate along line X ₁ in FIG. 4A is shown in the X ₁ section of FIG.
A cross _{- sectional} view when the board is cut along _line is shown in the section X ₃ of FIG. 19M.

(Surface oxidation process) In order to prevent the surface on which the source and drain regions of MISFET are to be formed from being contaminated, the exposed Si substrate 10 is
1 to a thickness of 100 Å by thermal oxidation of the surface.
A SiO ₂ film 115 is formed. At the same time as the SiO ₂ film 115 is formed, word lines WL _1-1 to _{WL 1-6} made of the second polycrystalline silicon layer, dummy word lines DWL _1-1 ,
DWL _1-2 , control signal lines φ _dc −L ₁ , φ _dc −L ₂ , electrodes 114 of capacitors C _B11 and C _B12 or
The surfaces of the gate electrodes of MISFETQ _S1 to Q _S3 are also oxidized, resulting in approximately 300 Å thick SiO ₂ on their surfaces.
A membrane 116 is formed as shown in FIG. 20N.

(Source/drain region formation process) Source/drain regions of MISFET are formed on Si substrate 1.
190, an N-type impurity, such as arsenic, is introduced into the Si substrate 101 through the SiO ₂ film 115 to selectively form the impurities in the Si substrate 101. Ion implantation is preferred as a method for introducing this N-type impurity. For example, arsenic ions are implanted with energy
It is implanted into the Si substrate 101 at 80 keV. The ion dose at this time was 1×10 ¹⁶ atoms/cm ² .

(Contact hole formation step (1)) First conductor layer, that is, first polycrystalline silicon layer 10
A contact hole for connecting 8 and a third conductor layer to be described later is formed in the SiO ₂ film 116. That is,
Contact hole CH ₁₀₁ as shown in Figure 19P
is selectively formed in the SiO ₂ film 110 using the photoresist film 117 as a mask.

Note that this contact hole CH ₁₀₁ is the 18th A
It corresponds to contact hole CH ₀ shown in the figure.

The reason why only the contact hole CH ₁₀₁ for connecting the first polycrystalline silicon layer 108 and the third conductor layer is formed is as follows.

That is, as described above, the thickness of the SiO ₂ film 110 formed on the surface of the first polycrystalline silicon layer 108 is 300 Å. On the other hand, the thickness of the SiO ₂ film 115 formed on the surface of the Si substrate 101 is 100 Å. Therefore, if these SiO ₂ films 115 and 110 are etched at the same time, the first polycrystalline silicon layer 1
There is a risk that the SiO ₂ film 115 will be over-etched before 08 is completely exposed. To prevent this, contact holes should be made as described above.
CH ₁₀₁ is formed independently.

25A is a plan view of the memory array and dummy array with contact hole CH ₁₀₁ formed.
FIG. 25B shows a plan view of the peripheral circuit section. That is, the cross-sectional view when the board is cut along the line _X1P in FIG. 25A is shown in the _X1 part of FIG. 19P, and the cross-sectional view when the board is cut along the line _X2P in FIG. 25B. is shown in the X ₂ part of Figure 19P,
A cross-sectional view of the substrate taken along the line X _3P in FIG. 25B is shown in the section X ₃ in FIG. 19P.

(Contact hole forming step (2)) Contact holes for connecting the source/drain regions and the third conductor layer are formed in the SiO ₂ film 115.
That is, by selectively etching SiO ₂ 115 using a predetermined mask, contact holes CH ₁₀₂ to _{CH 104} are formed as shown in FIG. 19Q. The above mask also has an opening in the part corresponding to contact hole CH ₁₀₁ , but the contact hole
Overetching of the SiO ₂ film 110 in CH ₁₀₁ does not pose a practical problem. In addition, the contact hole
CH ₁₀₂ corresponds to contact hole CH ₁ in FIG. 18A.

A plan view of the memory array and dummy array in this state is shown in FIG. 26A, and a plan view of the peripheral circuit section is shown in FIG. 26B. In other words, the cross-sectional view when the board is cut along line X _1Q in Figure 26A is Figure 19Q.
The cross-sectional view when the board is cut along the guide X _2Q in FIG. _26B is the X ₂ section in FIG. 19Q.
A cross-sectional view of the substrate taken along line X _3Q in FIG. 26B is shown in section X ₃ of FIG. 19Q.

(Interlayer insulating film forming step) An interlayer insulating film is formed on the entire surface of the Si substrate 101.
That is, as shown in FIG. 19R, the interlayer insulating film 11
8. For example, a phosphorus silicate glass (PSG) film with a thickness of about 8000 Å is formed on the entire surface of the Si substrate 101. This PSG layer 118 also serves as a getter for sodium ions that affect the characteristics of the MISFET.

(Contact hole formation step (3)) Contact holes are formed in the PSG film 118 to connect between the second polycrystalline silicon layer and the third conductor layer and between the source/drain region and the third conductor layer. . That is, as shown in Figure 19S,
The PSG film 118 is selectively etched to form contact holes CH ₁₀₁ to CH ₁₀₄ . The mask used to form the contact holes CH ₁₀₁ to _{CH 104} is the same as the mask used to form the contact holes CH ₁₀₁ to _{CH 104} in the contact hole forming step (2).

Subsequently, the PSG film 118 is heat-treated at a temperature of about 1000° C. in order to planarize the PSG film 118.
FIG. 27A shows a plan view of the memory array and dummy array with these contact holes CH ₁₀₁ to _{CH 104} formed by this heat treatment, and FIG. 27B shows a plan view of the peripheral circuit section.

By the way, the arsenic impurity ion-implanted as described in the above contact hole forming step (2) is stretched and diffused to form N ⁺ -type semiconductor regions 119 to 126 having a predetermined depth. These N ⁺ type semiconductor regions 119 to 126 become source/drain regions. The formation of contact holes for the SiO ₂ film 115 can also be accomplished simultaneously with the formation of contact holes for the PSG film 118. However, while the contact hole for the SiO ₂ film 115 is being completed, the PSG film 118 is also etched. That is, overetching of the PSG film 118 occurs. Therefore, in order to prevent this overetching, it is preferable to form the contact holes for the PSG film 118 and the contact holes for the SiO ₂ film 115 separately, as described above.

(Third conductor layer forming step) In order to form the power supply section V _CC -L and data lines DL _1-1 , _1-1 , DL _1-2 , _1-2 shown in FIG. 18A, first, a Si substrate is formed. A third conductor layer on the entire surface of 101,
For example, an aluminum layer with a thickness of 12000 Å is formed.
Next, this aluminum layer is selectively etched to form a power supply line V _CC - as shown in FIG. 19T.
A data line DL _1-1 and a wiring layer 127 are formed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a dynamic memory system configuration according to the present invention, FIG. 2 is a block diagram of a D-RAM according to the present invention, and FIG. 3 is a block diagram showing the operation of the D-RAM described above. A waveform diagram, FIG. 4A is a circuit showing an embodiment of the above D-RAM, FIG. 4B is a waveform diagram for explaining the outline of its operation, and FIG. 5A is an embodiment of the above D-RAM. FIG. 5B is a waveform diagram for explaining the outline of its operation, FIG. 6 is an IC layout pattern diagram of the D-RAM shown in FIG. 5A,
FIG. 7A is a circuit configuration diagram showing another embodiment of the above D-RAM, FIG. 7B is a waveform diagram for explaining the outline of its operation, and FIG. 8 is a diagram showing the D-RAM shown in FIG. 7A. -RAM IC layout pattern diagram; FIG. 9 is a perspective sectional view showing the element structure of one memory cell according to the present invention; FIG. 10 is a perspective sectional view showing the element structure of a dummy cell according to the present invention; FIG. 11 is a partial oblique sectional view showing some structural elements during active restore according to the present invention, and FIG. 12 is a circuit diagram showing a specific embodiment of the main part of the RC-DCR according to the present invention. Figure 13A shows the improved _φ
A circuit diagram showing one embodiment of BOOS, FIG. 13B, is
FIG. 14A is a circuit diagram showing one embodiment of the improved φ _Y -BOOS, FIG. 14B is a waveform diagram for explaining its operation, and FIG. 15 is a waveform diagram for explaining its operation. , FIG. 16 is a circuit diagram of a word line selection circuit showing an embodiment of the present invention, FIG. 16 is a circuit diagram showing a specific embodiment thereof, FIG. 17 is a waveform diagram for explaining its operation, and FIG. Fig. 18
Figures Aa and 18Ab are memory and dummy array layout pattern diagrams, Figure 18B is a peripheral circuit layout pattern diagram, Figures 19A to 19T are dynamic RAM manufacturing process diagrams, and Figures 20A to 27B are FIG. 2 is a plan view of a memory, a dummy array, and a peripheral circuit according to the manufacturing process.

Claims (1)

[Claims] 1. A sense amplifier connected to a pair of data lines and differentially amplifying the potential between the data lines, a row address decoder circuit, and a pulse generation circuit forming a word line control signal. A switching device that is provided between a signal line to which output pulses of the circuit are supplied, a word line, and the above signal line, and receives an output signal from the row address decoder circuit at its gate.
In a memory device including a MISFET and a dummy cell on each data line, receiving an output pulse signal from the pulse generation circuit,
a delay circuit that forms a timing signal with a delayed rise time relative to the output pulse signal; a cell boost circuit that receives the timing signal and boosts the signal line; and a cell boost circuit that receives the timing signal and connects the dummy cell. A memory circuit comprising control means for disconnecting a dummy word line and the signal line, the dummy word line being unselected when boosting the boost circuit. 2. The boost circuit includes a first bootstrap capacitor having one terminal receiving the timing signal, and a first switching means provided between the other terminal of the first bootstrap capacitor and the signal line. , and precharging means for the other terminal of the first bootstrap capacitor, and boosting the voltage of the signal line via the first switching means when receiving the timing signal. The memory device according to scope 1. 3 The above switching means is the first MISFET.
a second bootstrap capacitor that applies a bootstrap voltage to the gate electrode as the control electrode of the first MISFET; and the pulse provided between the signal line and the second bootstrap capacitor. 3. The memory device according to claim 2, further comprising a second MISFET that applies precharge to the second bootstrap capacitor in response to the output pulse signal of the generating circuit. 4. The memory device according to claim 3, wherein the second MISFET has a gate electrode maintained at a predetermined potential.