JPH0449306B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] Regarding a maintenance scanning circuit in a time-sharing switch equipped with a maintenance scanning circuit that transmits a plurality of fault information to a processing device, maintenance that does not impair economic efficiency even when the number of fault detection points increases. In a time-sharing switch equipped with a maintenance scanning circuit that holds multiple pieces of fault information until it is read by a processing device and transmits it to the processing device, the purpose is to realize a scanning circuit. a multiplexing means for time-division multiplexing information at a predetermined cycle; and a multiplexing means for sequentially accumulating the time-division multiplexed fault information output from the multiplexing means, and reading it after one cycle and inputting it from the multiplexing means. a storage means for repeatedly accumulating failure information by calculating a logical sum with failure information and re-inputting the logical sum;
A fault display means for displaying that the above fault information has been detected, and the processing device that scans the fault display means at a predetermined maintenance scanning cycle to detect a fault display are stored in the storage means. comprising a fault information output means for holding the read fault information while the processing device reads the fault information and outputting it to the processing device when the fault information is read;
Each time the processing device reads out the fault information from the storage means, it inputs an erase signal to the storage means to erase the fault information that has been read out and reset the display on the fault display means. .

[Industrial application field]

The present invention relates to a maintenance scanning circuit, and more particularly to a maintenance scanning circuit in a time-sharing switch having a maintenance scanning circuit for communicating a plurality of fault information to a processing device.

In a time-division switch, the processing unit monitors fault occurrence indications at multiple fault detection points at regular intervals, but scanning all fault detection points each time is a heavy burden on the processing unit, so it is difficult to detect fault occurrence. A method is often used in which the presence or absence of a fault is scanned at a fixed cycle (usually referred to as a maintenance scan cycle), and when the occurrence of a fault is indicated, the fault detection point is identified.

In the above method, a flip-flop is provided for each fault detection point to hold fault information, and the outputs of each flip-flop are aggregated by an OR circuit to display the presence or absence of a fault.

However, the scale of these flip-flops and OR circuits increases as the number of fault detection points increases.
This has the problem of impairing economic efficiency.

Therefore, there is a need for a maintenance scanning circuit that does not impair economic efficiency even when the number of failure detection points increases.

[Conventional technology]

FIG. 1 is a diagram showing an example of the configuration of a conventional maintenance scanning circuit.

In FIG. 1, fault information a detected at a plurality of fault detection points 1 is accumulated and held in a flip-flop 2 provided corresponding to each fault detection point 1, and then transmitted to a selection circuit 3 and an OR circuit 4. be done.
The OR circuit 4 creates common information ac constituted by the OR of the transmitted failure information a, and transmits it to the gate 5.

On the other hand, a processing device (not shown) sends out a common information reading signal b to the signal line 7 at a predetermined maintenance scanning period to make the gate 5 conductive, and checks whether the common information ac is output to the signal line 6 or not. monitor. If the common information ac is detected, a failure information read signal c is sent to the signal line 10 to make the gate 8 conductive, and a selection signal d is sent to the selection circuit 3 via the signal line 11. Identify the flip-flop 2 that holds the fault information a. Thereby, the fault detection point 1 that is generating the fault information a can be identified.

As is clear from the above explanation, in the conventional maintenance scanning circuit, the flip-flop 2 corresponds to each fault detection point 1, and the OR circuit 4 creates the common information ac from the fault information a transmitted from each flip-flop 2. It is necessary to provide Since these elements increase in proportion to the number of fault detection points 1,
This results in a loss of economic efficiency of the maintenance scanning circuit.

[Problem to be solved by the invention]

In conventional maintenance scanning circuits, as the number of fault detection points increases, the number of flip-flops provided for each fault detection point and OR circuits for creating common information increases, resulting in an increase in scale and a loss of economic efficiency. are doing.

An object of the present invention is to realize a maintenance scanning circuit that does not impair economic efficiency even when the number of failure detection points increases.

[Means to solve the problem]

The above purpose is to process fault information inputted from a plurality of fault detection points at a predetermined period in a time-sharing switch equipped with a maintenance scanning circuit that holds a plurality of pieces of fault information until it is read by a processing device and transmits it to the processing device. a multiplexing means for time-division multiplexing the fault information output by the multiplexing means, and the fault information and logic read out after one cycle and output from the multiplexing means after sequentially accumulating the time-division multiplexed fault information output from the multiplexing means; a storage means for repeatedly accumulating fault information by calculating a sum and re-inputting the fault information; and at least one fault information is detected when the fault information stored in the storage means is read at the predetermined period. a failure display means for displaying that the failure has occurred, and the processing device that scans the failure display means at a predetermined maintenance scanning cycle to detect a failure display, reads out the failure information stored in the storage means. a fault information output means for holding the read fault information while the processing device reads the fault information and outputting it to the processing device, and each time the processing device reads the fault information from the storage means; This is achieved by inputting an erasing signal to the storage means to erase the fault information that has been read out, and to reset the display of the fault display means.

[Effect]

In a maintenance scanning circuit equipped with the above means,
Fault information input from a plurality of fault detection points is time-division multiplexed by a multiplexing means, stored in a storage means, read out after one cycle, and logically summed with the fault information input from the multiplexing means. Since the fault information is inputted again after the fault has occurred, it is stored and held without using a flip-flop. Further, the accumulated and held information is read out at a predetermined cycle, and when at least one fault information is detected, the existence of a fault is displayed on the fault display means, and the fault display means is read at a predetermined maintenance scanning cycle. The presence of a fault is determined by the scanning processor.

When the processing device that has confirmed the existence of a fault sequentially reads out the fault information accumulated and held in the storage means, the read fault information is held in the fault information output means while the processing device reads it, and the fault information is stored in the fault information output means and output to the processing device. is transmitted to. Further, each time the processing device reads fault information from the storage means, it inputs an erase signal to the storage means to erase the fault information that has been read out, and at the same time resets the display on the fault display means.

As described above, the plural pieces of fault information are held until the processing device reads them and are transmitted to the processing device, and are erased when the processing device finishes reading them, so the conditions necessary for the maintenance scanning circuit are satisfied.

However, in the maintenance scanning circuit described above, there is no need to provide a flip-flop for each fault detection point as described above, and there is no need to aggregate the outputs of the flip-flops by an OR circuit to indicate the presence of a fault. Therefore, even if the number of fault detection points increases, the scale of the maintenance scanning circuit will not increase significantly, and economic efficiency will not be impaired.

〔Example〕

FIG. 2 is a diagram showing the configuration of a maintenance scanning circuit according to an embodiment of the present invention, and FIG. 3 is a time chart showing an example of the operation process in FIG. 2.

The same reference numerals indicate the same objects throughout the figures. Incidentally, .about.21 in FIG. 2 indicates that a time chart is shown at the same numbered location in FIG. 3.

An embodiment of the present invention will be described below with reference to FIGS. 2 and 3.

First, the operation until the failure information is stored in the storage unit will be explained in the first half of the time chart 1 in FIGS. 2 and 3, in part a. In FIG. 2, each fault detection point 1 is a multiplex circuit (MPX) 12, 13
The time domain TS is scanned one by one at a predetermined period T by
Input information (fault information a) from each fault detection point 1 is multiplexed. In Figure 3, the predetermined period T is 125 μs,
An example is shown in which 32 pieces of fault information are multiplexed in 32 time domains TS ₀ to TS ₃₁ within a period T.

As shown in FIG. 3, each time domain TS is divided into three time domains TR, TW, and TP, and TP is further divided into TP-R and TP-W. The fault information storage memory (MEM) 16 of the storage section stores this TR,
Reading and writing are performed in synchronization with TW, and within the time domain TP, reading is performed with TP-R and writing is performed with TP-W.

The read and write addresses in each time domain TR and TW are one for each time domain TS.
It is supplied via a selection circuit (SEL) 18 from a counting circuit (CNT) 17 (see FIG. 3, description of FIG. 3 will be omitted hereafter) which is stepped and reset at the period T. In addition, in the time domain TR and TW, the selection circuit 18 supplies the output from the counting circuit 17 as an address to the fault information storage memory 16, and in the time domain TP-P and TP-W, it detects a fault from a processing device (not shown). Switching is performed to supply the information read/erase address e to the failure information storage memory 16 (see).

A selection circuit (SEL) 15 is also provided in the circuit that inputs write information to the fault information storage memory 16, and in the time domain TP-P and TP-W, the input from the OR circuit 14 is stored as fault information. In the time domain TP-P and TP-W, switching is performed so that the erasure signal f from the processing device is inputted to the memory 16 (see).

The fault information a multiplexed in the multiplexing circuits 12 and 13 is input to the OR circuit 14 (reference),
When the selection circuit 15 is switched to the OR circuit 14 side, the fault information is input to the fault information storage memory 16. For example, failure information a _0-1 (a _0-1 is in the time domain TS ₀ The first fault information of multiplexed fault information a (same for other fault information) is applied to the write enable signal h (reference) sent from the processing device in the time domain TW. Therefore, it is written to address "0" of the fault information storage memory 16 (see). Thereafter, sequential writing is performed by incrementing the address output from the counting circuit 17, and the failure information a is stored in successive addresses.

Next, using part b in the second half of the time chart of FIG. The reading operation of the common information ac will be explained.

For example, the fault information a _0-1 stored in the fault information storage memory ₁₆ at a in FIG. (reference). The read fault information _a0-1 is set in the flip-flop 23 by a clock output from a timing circuit (not shown) and output from the Q terminal (see , ). This output is ORed with the newly input fault information _a0-2 in the OR circuit 14 and re-inputted to the fault information storage memory 16, and is sent out from the processing device in the time domain TW. It is stored again at the same address "0" by the signal h (see ,,,). This re-accumulation will be repeated thereafter, so for example in the time domain
If there is any fault information indicating the occurrence of a fault among the fault information a _0-1 , a _0-2 ... multiplexed at TS ₀ , this fault information will be deleted from the input from fault detection point 1 after that. Even if the fault information is stored, it is stored and held in the fault information storage memory 16.

On the other hand, the failure information a _0-1 read out after one cycle and output from the Q terminal of the flip-flop 23 is input to the S terminal of the flip-flop 19. Since the flip-flop 19 is a set-reset type flip-flop, once it is set, the R
It continues to be held until a reset signal is input to the terminal. Therefore, during the period T, the flip-flop 23
If there is "1" indicating the occurrence of a fault in even one of the fault information _a0 to _a31 sent from the flip-flop 19, the flip-flop 19 continues to output fault information from the Q terminal (see). This output indicates that a failure exists in at least one of the 32 pieces of failure information _a0 to _a31 , and is hereinafter referred to as common information ac.

The processing device detects the presence or absence of fault information at a plurality of fault detection points 1 by monitoring common information ac set in the flip-flop 19.
This monitoring is performed by transmitting the common information reading signal b at a fixed period (hereinafter referred to as a maintenance scanning period), for example, at a 30 ms period, to make the gate 5 of the fault display part conductive, and to output the common information from the Q terminal of the flip-flop 19. This is done by reading ac. While the common information read signal b is being sent from the gate 5, the common information ac is sent to the processing device (,
reference).

Next, the failure information reading operation will be explained using FIG. 3 and FIG. The processing device (not shown) that reads the common information ac knows that fault information indicating the occurrence of a fault has been input from any of the 32 fault detection points 1, so it reads the common information based on the maintenance scanning cycle.
Interrupts ac monitoring and starts reading failure information. This reading process is a process of reading all the fault information stored and held in the fault information storage memory 16, and is performed by sequentially specifying the addresses to be read using the fault information read/erase address e.
Note that since this processing is normally performed through the intervention of software, the signal transmission from the processing device is performed asynchronously with the predetermined cycle T.

The processing device first reads the first address of the area where the fault information is stored as the fault information read address,
For example, a failure information read/erase address e with "0" specified is sent (reference). This fault information read/erase address e is input to the fault information storage memory 16 when the selection circuit 18 is switched, so that the fault information stored at address "0" of the fault information storage memory 16 is stored in the time domain TP. -R is read out (referenced) and inputted to the D terminal of the flip-flop 21 of the fault information output section.

On the other hand, after sending out the failure information read/erase address e, the processing device sends out a clock g in synchronization with the time domain TP-R, but since this clock g is input to the CK terminal of the flip-flop 21, the
The fault information input to the terminal is set in the flip-flop 21 and output from the Q terminal (see , ).

After sending out the clock g, the processing device sends out the fault information read signal c and makes the gate 8 conductive, so that the output of the flip-flop 21, that is, the fault information a at address "0" is sent to the processing device. (see ). This allows the processing device to confirm whether or not the fault information a is being sent to the fault detection point 1 corresponding to address "0". Next, the processing device sends out the fault information read/erase address e specifying the address "1", reads the fault information a stored and held at the address "1" of the fault information storage memory 16, and in the same manner, the fault information at the address is detected. Read information a.

In the above, for example, after the fault information a of address "0" is set in the flip-flop 21 in the time domain TP-R, the processing device
Sends write enable signal h in synchronization with TP-W (
reference). In the time domain TP-W, the selection circuit 15
is switched to the processing device side (reference), so the erasure signal f sent from the processing device side is written into the fault information storage memory 16. Since this erasure signal f is a "0" signal that is constantly output, "0" is input to the fault information storage memory 16 each time the selection circuit 15 is switched (see , ).
However, since the write enable signal h is not normally sent out, this erase signal f is not written into the fault information storage memory 16. When the failure information reading process is started, the write enable signal h is sent as described above, so that the erase signal f of "0" is written to the same address as the address read immediately before (see , ). That is, the read fault information a is erased immediately after reading is finished.

The processing unit also operates in the same time domain TP-W as above.
A reset signal k is sent out in synchronization with the flip-flop 19, and this reset signal k is input to the R (reset) terminal of the flip-flop 19 and resets the flip-flop 19 which has been in the set state.
That is, the flip-flop 19 is reset each time the fault information of one address is read.
Therefore, if the cause of the failure has disappeared after all failure information has been read, the flip-flop will remain reset, but if the cause of the failure remains or a new failure occurs, the failure information will be read again. The data is stored in the storage section, and the flip-flop 19 is set in the same manner as described above. The common information set in the flip-flop 19 at this time is confirmed by the processing device when the processing device that has finished reading the fault information resumes reading the common information in the maintenance scanning period.

On the other hand, the flip-flop 21 remains set with the failure information of address "0", for example, and is not reset (see).
However, since the set information is never read after being read once by the failure information reading signal c, no problem occurs. When the processing device that has finished reading the fault information at address "0" reads address "1", the fault information stored at address "1" is output, but only at this time does the flip-flop 21 Fault information for a new address "1" is set to overwrite the fault information for address "0".

As is clear from the above description, according to the embodiment of the present invention shown in FIG.
Since all of the fault information a that occurs in the fault information is stored and held in the fault information storage memory 16, the flip-flop 2 that holds the fault information a for each fault detection point 1 provided in FIG. 1 becomes unnecessary. In addition, common information ac indicating whether at least one failure information a is held is also stored on the flip-flop 19.
Therefore, unlike the OR circuit 4 provided in FIG. 1, there is no need for a circuit element whose input terminals increase in proportion to the number of fault detection points 1.

Due to recent advances in semiconductor technology, the size and cost of the fault information storage memory 16 will not increase sharply even when the number of fault detection points 1 increases.
Therefore, compared to the flip-flop 2 and the OR circuit 4 shown in FIG. 1, the device can be made much smaller and more economical.

Although the embodiment of the present invention has been described above with reference to FIGS. 2 and 3, FIG. 2 and FIG. Needless to say, it is not limited to. For example, the value of the multiplexing cycle T (125 μs), the number of failure detection points 1 and time-division multiplexed failure information (32), the value of the address of the failure information storage memory 16 (“0 to 32”), etc. Of course, it is not limited to the numerical values given above. Further, the configuration of the maintenance scanning circuit can be varied in various ways depending on the scale of the time division switch and the circuit elements used, but the effects of the present invention will not be changed by this. Furthermore, it is clear that the effects of the present invention do not change even if the potentials of the various signals in FIG. 3 are reversed depending on the circuit elements used.

〔Effect of the invention〕

As described above, according to the present invention, when the number of fault detection points increases in a time division switch equipped with a maintenance scanning circuit that holds a plurality of pieces of fault information until it is read by a processing device and transmits it to the processing device, It also becomes possible to realize a maintenance scanning circuit that is small and economical.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the configuration of a conventional maintenance scanning circuit, FIG. 2 is a diagram showing the configuration of a maintenance scanning circuit according to an embodiment of the present invention, and FIG. 3 is an example of the operation process of FIG. 2. This is a time chart showing. In the figure, 1 is the fault detection point, 2, 19, 21, 23
are flip-flops, 3, 15, 18 are selection circuits, 4, 14 are OR (logical sum) circuits, 5, 8 are gates, 6, 7, 9, 10, 11, 20, 22, 2
4, 25, 26 are signal lines, 12, 13 are multiplexing circuits, 16 is a fault information storage memory, 17 is a counting circuit, a is fault information, b is a common information read signal, c is a fault information read signal, d is a fault information read signal Selection signal, e is failure information read/erase address, f is erase signal, g is clock, h is write enable signal, k is reset signal, TS,
TR, TW, TP (TP-R, TP-W) are time domain,
shows.

Claims (1)

[Scope of Claims] 1. In a time-sharing switch equipped with a maintenance scanning circuit that holds a plurality of pieces of fault information until it is read by a processing device and transmits it to the processing device, fault information input from a plurality of fault detection points is predetermined. multiplexing means for time-division multiplexing at a cycle; and after sequentially accumulating the time-division multiplexed fault information output from the multiplexing means, the fault information is read out after one cycle and inputted from the multiplexing means. an accumulation means for repeatedly accumulating fault information by logically ORing the result and re-inputting the fault information; and at least one fault information when the fault information stored in the storage means is read at the predetermined period a fault display means for displaying that a fault has been detected; and the processing device that scans the fault display means at a predetermined maintenance scanning cycle to detect the display of a fault, and the processing device detects the fault display stored in the storage means. and a fault information output means for holding the read fault information while the processing device reads it and outputting it to the processing device when reading the fault information, and the processing device receives the fault information from the storage means. A maintenance scanning circuit characterized in that each time it is read, an erase signal is input to the storage means to erase the fault information that has been read out and to reset the display of the fault display means.