JPH0450624B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] This is a multi-access control method in which when the same device is simultaneously accessed from multiple directors, the access is allowed and processed normally unless the access is to the same cylinder; In the case of access, the director with slower access will wait, and after the director with faster access finishes processing, the slower director continues processing using predetermined information, thereby reducing the processing capacity of the inter-system shared device. Significant improvements are possible.

[Industrial Application Field] The present invention relates to a multi-access control method that makes it possible to significantly improve the processing capacity of devices shared between systems.

As the usage of information processing systems has become more sophisticated and complex, many systems have been constructed in which multiple devices are shared and accessed by multiple host systems.

Improving the efficiency of access and processing capacity of such inter-system shared devices will be necessary in order to make the use of information processing systems more general in the future.

[Problems to be solved by conventional technology and invention]

FIG. 6 is a diagram for explaining the conventional example, FIG. 7 is a diagram for explaining access truth values in the conventional example, and FIG. 8 is a diagram for explaining the operation of the conventional example.

In Fig. 6, A is a system configuration block diagram, and B is a path selection array 5 (hereinafter referred to as PSA5).
The formats within are shown below.

FIG. 6A shows a host system 1a, which has a plurality of paths a to e (connection paths) and issues various commands to devices connected to the lower level, and transfers data in response to the various commands. 1b, and a director (hereinafter referred to as DIR) 2 that recognizes various commands from the higher-level systems 1a and 1b and instructs devices connected to lower levels to execute them.
a, 2b, and adapters (hereinafter referred to as ADP) 3a, 3b that select specific devices 4l to 4h and control execution processing based on execution instructions from DIRs 2a, 2b.
and has multiple cylinders for recording data,
The devices 4l to 4n that execute specific execution processes under the control of the ADPs 3a and 3b have a predetermined format for exclusive control information, etc. when the ADP 3a and ADP 3b respectively access the same devices 4l to 4n at the same time. It consists of PSA5 which is stored in

Furthermore, as shown in FIG. 6B, the PSA format is an available (hereinafter referred to as AVL) information area that resets bits other than the own porter a to p when the predetermined device 4(i) is in use or reserved. , Regarding boats a to p whose AVL information is off,
When the start I/O command is received, it responds with device busy and then sets the bits of the ports a to p of the device 4i, which is an outstanding device end that needs to respond with the device end, and sets the bits of the ports a to p. When the AVL information is turned on, the Outstanding Device End (hereinafter referred to as ODE
When the specified device 4i is powered on and enters the ready state, the package change interrupt information of all ports a to p is set, and the logical product with the AVL information indicates that the specified device 4i is ready for use. Regarding the patch change interrupt (hereinafter referred to as PCH) information area and PSA5, which is a file shared between systems,
When using from the corresponding port a to p, other ports a to p
It consists of a reserved (hereinafter referred to as RSV) information area for prohibited use.

Note that each of the above information areas corresponds to one port a to p.
Bits are assigned one by one, and the initial value of AVL information is "FFFF", and the initial values of ODE information, PCH information, and RSV information are "OOOO". Also, an AVL information area that defines multiple ports as one group,
"Port" used in the explanation of the RSV information area is replaced with "group".

For example, if DIR2a receives a start I/O command from host system 1a via port b,
As shown in Figure 8(l), the AVL information of each port a to p is set to "l", and the port b
AVL information other than this is reset to "O". Next, when the start I/O command processing is completed via port b, the AVL information of all ports a to p is
is set to l″.

Next, issue a start I/O command via port b.
When the DIR 2a receives a start I/O command and is executing the process, for example, when the DIR 2b receives a start I/O command via port i, it responds that the device is busy to the host system 1b. At this time, port i of the ODE information area is set to "l", and port i of the AVL information area is reset to "o".

The start I/O command processing via port b is completed, and port i in the AVL information area is set to "1", and the device end is responded via port i. At this time, port i of the ODE information area is reset to "o". This situation is shown in FIG. 8-2.

Next, when performing device reservation via port b, port b in the AVL information area and RSV information area is set to "l" as shown in Figure 8, and device release is performed via port b. and
All ports a to p of the AVL information area are set to “l”, and port b of the RSV information area is set to “O”.
will be reset to

FIG. 7 illustrates the various access conflict states described above as access truth values, and this is
This access truth value is based on the assumption that the device 4l is being accessed through the device 4l. In addition, the white "○" mark in the figure indicates that access is possible, the black "○" mark indicates DIR2a, 2b busy, the "x" mark indicates device busy, and the "-" mark indicates a combination that does not exist. show.

For example, when a start I/O command is received through path e, access to devices 4l to 4n is possible when nothing is being done to device 4l, and access to cylinder m is possible when cylinder n of device 4l is being processed. access is not possible and device busy is responded.

Further, a device busy response is sent in all cases when a plurality of ports are in a reserved state without being defined as one group, in a reserved state with a group definition, and when cylinder n is being processed in a reserved state.

As described above, even when accessing the same device 4i in different cylinders, access is conventionally impossible, which is one of the major factors that reduce processing efficiency.

[Means for solving problems]

FIG. 1 shows a block diagram illustrating the principle of the present invention.

The block diagram in Figure 1 is the DIR explained in Figure 6A.
2a, 2b, ADP3a, 3b, and device 4
i and PSA5, and the format of PSA5 is that among the information areas explained in Figure 6B, the AVL information area has multiple DIR2a,
When trying to access the same device 4i and the same cylinder via 2b, DIR2 was accessed slowly
Set the predetermined information of the corresponding ports a to p of a and 2b in the currently accessed DIR2a and 2b side, and store the cylinder ODE information area for waiting and the cylinder address currently being accessed for each DIR2a and 2b. A cylinder address information area has been added to form the format.

[Effect]

When accessing different cylinders on the same device at the same time, the cylinder address information inside the PSA is compared, and if the set values are different, access is enabled using mismatch information. When accessing the same device and the same cylinder at the same time,
In addition to setting the cylinder ODE information of the DIR that is being accessed, it also sets the cylinder ODE information of the DIR that is being accessed, and
DIR waiting at DIR and accessing it
After the processing is completed, the set cylinder ODE information is notified to the waiting DIR, and access to this DIR is immediately continued, thereby enabling more efficient system processing.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 1 to 5.

FIG. 2 is a diagram explaining an embodiment of the PSA of the present invention,
FIG. 3 is a diagram for explaining access truth values in the embodiment of the present invention, and FIGS. 4 and 5 are diagrams for explaining the operation of the embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

As explained in FIG. 6, in order to perform exclusive control between DIR2a and DIR2b, a memory called PSA5 is prepared, and the upper system 1a, 1b is connected to this memory.
It stores an interface exclusive control table between DIR2a and DIR2b.

The initial value for each DIR2a and 2b of the cylinder (hereinafter referred to as CYL) ODE information area shown in Figure 2 is "OOOO", and the CYL address (hereinafter referred to as ADR
That of the information area (referred to as "FFFF") is "FFFF".

For example, when cylinder n is accessed via port b, the CYLADR information of DIR2a is “FFFF”
It is set to "n" from then on, and reset to "FFFF" when the access via port b is completed.
Also, when cylinder m is accessed via port i while cylinder n is being accessed via port b,
Set value “n” of CYLADR information area of DIR2a
and the cent value “m” in the CYLADR information area of DIR2b
are compared within PSA5.

At this time, if a mismatch in cylinder addresses is confirmed, access to cylinder m via port i is permitted, and at the end of access to cylinder m via port i and cylinder n via port b, the respective CYLADR information is is reset to “FFFF”. This situation is illustrated in FIGS. 1 and 2.

Next, if you try to access cylinder m via port i while cylinder m is being accessed via port b, the CYL ADR information of DIR2a at that time is “m”, and this set value and DIR2b
The updated value of CYL ADR information is compared to confirm address matching.

As a result, only port i of the CYL ODE information of DIR2a is set to "1", and accesses from DIR2b are waited for inside DIR2b.

Next, when the access via port b is completed, the CYL ADR information of DIR2a is reset to “FFFF”, and DIR2a checks this and sets DIR2a to indicate that cylinder m has been accessed via port i.
Notify DIR2b from a.

As a result, DIR2b becomes the CYL ODE of DIR2a.
At the same time as resetting the information port i to “O”,
Set the CYL ADR information of DIR2b to "m" and continue accessing cylinder m via port i.

FIG. 3 shows the availability of the above-mentioned access state as an access truth value, which is the access truth value when the device 4l is accessed through path a, as in the case of FIG. 7.

For example, if cylinder m of the device 4l is accessed through path e while cylinder n of device 4l is being processed through path a, the access becomes possible.

On the other hand, when the cylinder n of the device 4l is accessed through the path e, a wait occurs inside the DIR 2b (triangular black mark), and processing continues after the processing of the DIR 2a is completed.

Although this embodiment describes a multi-access control method between cylinders, it goes without saying that the multi-access control method between tracks or sectors can be similarly controlled instead of cylinders.

〔Effect of the invention〕

According to the present invention as described above, there is an effect that more efficient system processing can be performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the principle of the present invention.
FIG. 2 is a diagram explaining an embodiment of the PSA of the present invention,
FIG. 3 is a diagram for explaining the access truth value in the embodiment of the present invention, FIGS. 4 and 5 are diagrams for explaining the operation of the embodiment of the present invention, and FIG. 6 is a diagram for explaining the conventional example. FIG. 7 is a diagram explaining the access truth value in the conventional example, FIG. 8 is a diagram explaining the operation of the conventional example,
are shown respectively. In the figure, 1a and 1b are upper systems, 2
a, 2b are DIR, 3a, 3b are ADP, 4l~n
indicates the device, and 5 indicates the PSA.

Claims (1)

[Claims] 1. A device comprising: a path selection array 5 that stores exclusive control information that controls whether simultaneous access to the same device 4i from a plurality of directors 2a, 2b is possible; and a plurality of cylinders that store user data. 4i, adapters 3a and 3b that control access and data transfer to the device 4i, and a plurality of ports a to p, and the adapter recognizes commands from a host device corresponding to each port a to p. In a subsystem consisting of directors 2a and 2b that instruct 3a and 3b to access the device 4i, when a conflict for accessing the same cylinder occurs between different directors 2a and 2b, the director 2
A cylinder device end information area for waiting inside the directors 2a and 2b, and a cylinder address information area for storing the cylinder address currently being accessed for each director 2a and 2b are provided in the format of the path selection array 5, When an attempt is made to access the same device 4i and the same cylinder via the ports a to p based on instructions from multiple directors 2a and 2b, the cylinder device end information of the ports a to p of the slower director 2a and 2b is transferred to the faster director. 2a, 2b, and when the processing of the earlier directors 2a, 2b is completed, the existence of the cylinder device end information is notified to the slower directors 2a, 2b, and as a result, the slower directors 2a, 2b start processing. A multi-access control method characterized by continuing.