JPH0450790B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reference signal generation circuit used in a television camera having a solid-state image sensor and an imaging device using the circuit.

[Prior art]

The reference signal generation integrated circuit (IC) used in television cameras with solid-state image sensors generates pulses (clamp pulses, synchronization pulses, blanking pulses, etc.) used in signal processing from the reference frequency from a reference oscillator, and solid-state It has the function of generating drive pulses (vertical transfer pulses, horizontal transfer pulses) and sample hold pulses for the image sensor.

On the other hand, in a television camera using a solid-state image sensor, it is possible to discharge the charge on the pixel once during the vertical accumulation period, thereby making the actual accumulation time shorter than one vertical period.

For example, in a solid-state image sensor called a frame transfer type, the charge in the light receiving part that performs photoelectric conversion and charge accumulation is forcibly removed by vertical transfer once in the middle of the vertical period, and then the charge is removed for the remaining period of the vertical period. For example, Japanese Patent Application No. 55-61098 proposes a driving method in which the storage time is set as a substantial storage time.

According to the above method, for example, in an NTSC TV camera, the accumulation time is usually 1/60 seconds, but this can be changed to 1/120 seconds, 1/500 seconds, etc., which allows for a large amount of light. There is no need to make a small aperture during incidence. Therefore, a blurring effect can be obtained.
Further, effects such as preventing blurring of images of objects moving at high speed are produced.

[Problem that the invention seeks to solve]

However, when performing the above-mentioned operation, the actual accumulation time is shortened, especially when the charge accumulated up to the middle of the vertical period is eliminated inside the image sensor instead of being taken out as a signal as described above. In this case, the amount of charge to be removed becomes extremely large. For example, if the effective accumulation time t ₁ is 1/500 seconds, the ratio of the accumulation time t ₂ of the charge to be removed and t ₁ is t ₂ /t ₁ = (1/60−1/500)/1/ 500≒7.3 This is about 7.3 times, and if the charge accumulated at t ₁ is at the standard level, at t ₂ it will be at the standard level.
7.3 times more charge is accumulated. When such a large amount of charge is accumulated, it is extremely difficult to eliminate it all within the image sensor so that it does not affect the substantial accumulation time. In particular, the amount of charge generated in so-called highlight areas on the screen is extremely large, and when vertical transfer is performed to discharge charge in the middle of the vertical period, a large amount of charge remains and is output to the screen. There will be a negative impact on.

Also, when using a conventional reference signal generation IC,
In order to perform such operations, many external circuits, such as logic circuits or microcomputers, are required.

The first invention of the present application aims to eliminate the drawbacks of the above-mentioned conventional example, and at the same time, to propose an imaging device in which no adverse effect appears on the screen even if the actual storage time is set short.

[Effect]

In the first invention of the present application, image charges are accumulated in the light receiving section by the imaging means, but by once discarding these charges midway through, the charges accumulated thereafter become the substantial image charges. Further, the control means makes the accumulation state of the light receiving section different between the charge accumulation period to be eliminated and the actual accumulation period, and intermittently erases unnecessary charges during the charge accumulation period to be eliminated, and erases unnecessary charges during the actual accumulation period. continuously dissipates unnecessary charges.

This makes it possible to effectively erase unnecessary charges during the charge accumulation period to be eliminated and during the actual accumulation period.

[Means for solving problems]

In the imaging device of the first invention of the present application, an imaging means;
The charge accumulated in the light receiving section of the imaging means is once removed, and the charge is substantially accumulated in the subsequent period, and
It has a control means for switching and controlling the accumulation state and erasing state of the light receiving section in the accumulation period of the charge to be removed and the actual accumulation period.

〔Example〕

The present invention will be explained in detail below using the drawings. FIG. 1 shows a block diagram of an imaging device using the reference signal generating IC of the present invention.

Reference numeral 1 denotes a solid-state imaging device as an imaging means, which is a frame transfer type CCD (charge coupled device) consisting of a light receiving section 1a and a storage section 1b. 10
1 is a reference oscillator such as a crystal oscillator, 102 is a reference signal generation IC as a control means of the present invention, 103
is a vertical drive circuit that generates a transfer pulse φI for the light receiving section 1a, a driving pulse φS for the storage section 1b, an anti-blooming (AB) gate driving pulse φAB for preventing blooming in the light receiving section 1a, etc. from the signal from 102. do. Reference numeral 104 denotes a horizontal drive circuit, which generates a horizontal register drive pulse φSH, a reset gate drive pulse φR, etc. for the solid-state image sensing device 1 from a reference signal generation IC, 102. Reference numeral 105 denotes a sample and hold circuit that samples and holds the output of the solid-state image sensor 1 and makes it continuous.

106 is a signal processing circuit that performs color separation, processing, and processing on the output of the sample hold circuit 105;
Performs encoding etc. to generate a standard television signal,
Output to output terminal 107. Reference numeral 108 denotes an accumulation time changeover switch for switching the operation mode of the solid-state image sensor 1, that is, setting the actual accumulation time of the solid-state image sensor 1 to be one vertical period or shorter than one vertical period.

FIG. 2 shows the output of the vertical drive circuit 103 in a normal mode in which the substantial storage time of the solid-state image sensor 1 is one vertical period. VBLK indicates a vertical blanking interval at a high level.

φI generates vertical transfer pulses at the IH and IL levels for the number of vertical pixels once during the vertical retrace interval, and is at the intermediate level IM during the other periods. During the vertical retrace period, φS is generated as vertical transfer pulses of the SH and SL levels, the same number as the number of pulses of φI, in synchronization with the vertical transfer pulse of φI, and transfers the signal of the light receiving section 1a to the storage section 1b. One pulse is generated in each horizontal blanking interval except for the vertical blanking interval.

φAB is set to intermediate level ABM when the vertical transfer pulses of φI and φS are generated in order to increase the transfer efficiency when transferring the signal from the light receiving section 1a to the storage section 1b, and otherwise the ABH and ABL levels are unnecessary only in the horizontal retrace section. Generates a charge erase pulse.

This will be explained in detail.

As is well known, the light receiving section 1a has a two-dimensional array of imaging cells along a predetermined number of rows, and the storage section 1b has an equal number of storage cells along the same rows and columns. The horizontal register section 1c has a two-dimensional array, and the horizontal register section 1c has at least the storage section 1b.
It has a one-dimensional array of charge transfer cells along the rows, the same number as the number of memory cells in the CCD, and the entire CCD is shielded from light except for a predetermined area of the light receiving section 1a.

When such a frame transfer type CCD 1 is driven at the television cycle, charges generated and accumulated in the light receiving section 1a are vertically transferred from the light receiving section 1a to the storage section 1b during the vertical blanking period of the television.
Further, the charges stored in the storage section 1b are step-transferred to the horizontal register section 1c one line at a time during the horizontal blanking period.

Further, the charges in the horizontal register section 1c are horizontally transferred to the output amplifier section within the period of one horizontal line.

A single-phase drive anti-blooming gate type CCD will be described below.

FIG. 3 is a diagram showing the configuration of main electrodes near the boundary between the light receiving section 1a and the storage section 1b.

10CS is the channel stop that separates horizontal pixels, φ′I is the drive electrode of the light receiving section, φ′ABG is the anti-blooming gate electrode, φ′S is the storage section drive electrode,
CB is the drive barrier area, CW is the drive well area,
VB is a virtual barrier area, and VW is a virtual well area.

FIG. 4 is a cross-sectional view taken along line A-A' in FIG.
A virtual phase potential is formed in VB and VW by implanting P ions, and furthermore, from the viewpoint of electrons, CB>CW,
N ions are implanted to form a potential distribution of VB>VW. X indicates the transfer direction of this CCD. FIG. 5 is a potential distribution diagram of this CCD, in which VB and VW are fixed to virtual phases, and the potentials of the CB, CW, and ABG sections change as shown in FIG. 5 depending on the driving voltage.

When φI is the intermediate value IM, the potentials of CW and VW are almost the same as shown in Figure 8.
Charge is accumulated in both CW and VW. Furthermore, the charges accumulated in CW and VW during transfer are automatically added pair by pair, and by shifting the added charges for each field, the position of the center of gravity of sensitivity is shifted, thereby performing an interlacing operation.

During vertical transfer, φABG is fixed at a predetermined intermediate potential ABM between the virtual potentials of regions VB and VW so as not to disturb vertical transfer, and at the same time, continuous pulses of about 500 KHz to 2 MHz are applied during other periods.
Unnecessary charges above a predetermined level are removed by charge recombination.

A method for removing unnecessary charges by charge recombination is disclosed in Tokuhan Sho.
58-75838, etc., by driving φABG, a part of the accumulated charge is pushed up to the potential of the recombination center, and by recombining with holes, unnecessary charges are periodically removed. It is something.

FIG. 6 shows the drive voltage waveform in a so-called mode (short time mode) in which vertical charge transfer is performed during the storage to reduce the actual storage time.

φI generates a vertical transfer pulse once for the number of vertical pixels just before the vertical retrace period, transfers the charge on the pixels of the light receiving section 1a to the storage section 1b and eliminates it, and then after the end of the vertical retrace period Vertical transfer pulses for sending the signal of the light receiving section 1a to the storage section 1b again are generated for the number of vertical pixels to shorten the actual storage time.
Further, during the accumulation of the charge to be removed, φI is not set to an intermediate level, but is set to the level indicated by IL in order to reduce the amount of excess charge accumulated in the pixel as described later.

To explain this, FIG. 8a shows the potential distribution of the light receiving section when φI is at the IM level, and FIG. 8b shows the potential distribution when φI is at the IL level. In the same figure a, electricity Q ₁ accumulated in CW and VW after excess charge is removed.
The sum of the charges Q ₂ accumulated in is the maximum charge amount, but in the figure b, only Q ₃ is accumulated after the excess charges are removed. Therefore, the amount of charge to be removed later is reduced, so that overflow of charges that occurs during vertical transfer can be reduced.

When the vertical transfer pulse of φI is generated, φS generates the same number of pulses that are synchronized with the vertical transfer pulse, and 1 pulse is generated outside the vertical retrace interval where no vertical transfer pulse occurs.
Generates one pulse during the horizontal blanking interval. φAB generates continuous pulses during the substantial storage period, becomes intermediate level ABM during vertical transfer, and otherwise generates a plurality of pulses only during the horizontal retrace interval. This makes it possible to effectively prevent blooming even if strong light is incident when the actual storage time is shortened.
Further, while reading out the charges accumulated during the substantial accumulation time, noise accompanying erasing of the unnecessary charges is not mixed.

FIG. 4 shows control signals from the reference signal generation IC for generating the drive pulses shown in FIGS. 2 and 3. FIG.

VT is a vertical transfer trigger signal, and a rising edge of the signal starts vertical transfer. In the normal mode, a pulse is generated once during the vertical retrace interval, and in the short time mode, a pulse is generated once before and after the vertical retrace interval.

SMS is an accumulation mode switching signal for the light receiving section, and at H level, φI becomes intermediate level IM except during vertical transfer, and L
It becomes low level IL except during vertical transfer.
In the normal mode, it is always at the H level, in the short time mode, it is at the L level while accumulating charges to be removed, and at the H level while accumulating charges to be substantially read out. ABS
is an anti-blooming switching signal, and at H level, φAC occurs continuously, and at L level, φAB occurs only in the horizontal flyback section. However, during vertical transfer, it becomes intermediate level ABM. In the normal mode, it is L level; in the short time mode, it is L level while accumulating the charge to be discarded; it becomes H level while accumulating the charge to be substantially read out.

FIG. 9 is a diagram showing an embodiment of the reference signal generating IC of the present invention. 200 is a reference oscillation circuit, 201 is an H counter that counts horizontal (H) timing, 2
02 is an H decoder that generates the necessary horizontal timing from the output of the H counter, 203 is a V counter that counts vertical (V) timing, and 204 is 2
a V decoder as a control signal forming unit that generates the necessary vertical timing from the output of the 03V counter;
205 is a gate circuit that synthesizes necessary pulses from H timing and V timing, 206 is a horizontal transfer pulse generator, and the horizontal drive circuit generates φSH, φR.
Generates SH, R and sample and hold pulses to create

A vertical transfer pulse generator 207 generates a vertical transfer pulse using VT and outputs I and S for producing φI and φS in the vertical drive circuit. 20
8 is an AB pulse generating section which generates continuous or discontinuous AB signals by ABS.

209, 210, 214 are AND gates, 21
1,213 is a NOT gate, and 212 is an OR gate. 218 is a mode switching input terminal, 219 is a mode switching input terminal, and 219 is a mode switching input terminal.
SMS output terminal, 220 is ABS input terminal, 221
222 is a vertical transfer trigger VTIN input terminal, and a short time mode vertical transfer trigger signal VT2 output terminal. Further, 215 is a NOT gate, 216 is an OR gate, and 217 is a NOT gate, which are external gates. VT1 is a normal mode vertical transfer trigger signal.

AND when switch 108 is in normal mode 'H'
209, VT1 is connected to VT through OR212, and at 207, a normal mode vertical transfer pulse is generated. Also, 219 becomes 'L', SMS remains 'H', and ABS remains 'L'.
As described above, the entire device operates in the normal mode.

When the switch 108 is in the short time mode 'L', VT2 and VT are connected through the terminal 222 → terminal 221 → AND 210 → OR 212, and the vertical transfer pulse generator 207 generates a vertical transfer pulse in the short time mode. Also, connect terminal 2 through AND214.
19 is output, and through NOT215
SMS OR and NOT, ABS through terminal 220
is input. As a result of the above, the entire device operates in the short time mode. In this embodiment, both the ABS and AMS control signals are commonly generated from one output of the V decoder 204, so the number of control lines is reduced.
Another feature is that the number of pins can be reduced when connecting this line outside the IC with pins.

In addition, in order to perform vertical transfer at other timings of VT2, switch 108 is set to 'L' and terminal 22 is set to 'L'.
If a desired timing signal is input to VTIN 221 without connecting VTIN 222, vertical transfer can be performed at any timing. This embodiment also has a feature in this respect.

In the above embodiments, a single-phase drive type frame transfer type CCD having an excess charge discharge structure by recombination has been described, but the present invention can also be applied to other types when the potential distribution changes depending on the driving conditions. It can be implemented.

Furthermore, in this embodiment, anti-blooming gate electrodes are provided in the virtual regions VB and VW by charge recombination, so during the period _T1 , the potential levels seen from the electrons in the drive regions CB and CW are set to VB and VW. However, when the anti-blooming gate electrode ABG is provided on the drive region side, the potential level seen from electrons in the drive regions CB and CW regions is lowered with respect to VB and VW.

As described above, according to this embodiment, a reference signal generation IC capable of switching between the normal mode and the short time mode can be easily constructed with a small number of external circuits.

〔Effect of the invention〕

As explained above, according to the first invention of the present application, a good image can be obtained even when the storage time of the solid-state image sensor is made shorter than the vertical period.

In addition, blooming can be effectively prevented without significantly increasing power consumption. Furthermore, the blooming prevention effect is high both during the actual accumulation and during the accumulation of removed charges.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an imaging device using the reference signal generating IC of the present invention, FIG. 2 is an operation timing diagram in normal mode, FIG. 3 is a diagram showing an example of the main electrode configuration of the configuration shown in FIG. 4, and FIG. The figure is a schematic cross-sectional diagram of the configuration shown in Figure 2, Figure 5 is a potential state diagram in the configuration shown in Figure 4, Figure 6 is an operation timing diagram of short-second mode, and Figure 7 is a timing diagram of control signals when switching modes. , FIGS. 8a and 8b are diagrams showing potential distribution examples when φI is at the IM level and the IL level, respectively, and FIG. 9 is a diagram showing an embodiment of the reference signal generating IC of the present invention. 1... Solid-state image sensor, 102... Reference signal generation IC.

Claims (1)

[Claims] 1: first and second regions that convert incident light into charges; a charge transfer electrode provided in the first region; a recombination electrode provided in a second region to recombine the charges with the charges; controlling the transfer electrode and supplying an intermittent drive signal to the recombination electrode during that period, and controlling the charge transfer electrode so as to read out and eliminate the charge in the second region in a subsequent second period; , in a subsequent third period, controlling the charge transfer electrode to accumulate charge in the first and second regions, respectively, and continuously supplying a drive signal to the recombination electrode during that period; an imaging device comprising: control means for controlling the transfer electrode to add and read out charges in the first and second regions during a period of , and outputting the readout signal from the imaging element as a video signal; .