JPH0451086B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a switch capacitor arithmetic circuit, and more particularly to a switch capacitor amplification circuit that obtains a desired amplification degree by combining the capacitance ratio of the switch capacitor circuit and the switching frequency. Regarding circuits.

[Background of the invention]

Recently, there has been a movement to realize an amplifier circuit using an IC, which consists of the resistors R _a and R _f and the operational amplifier OP shown in Fig. 1, but the circuit using such resistors is When integrating circuits, it is difficult to create highly accurate resistors within the IC.

On the other hand, according to the switch capacitor circuit method, which has been researched and developed in recent years and which equivalently realizes resistance using a switch and a capacitor, when integrating a circuit, the capacitor has a smaller chip size than the resistor. Since the capacitance value can be determined based on the area, the value can be created accurately. Therefore, it is an effective method for creating a circuit with good characteristics in terms of accuracy, temperature characteristics, etc.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a switched capacitor amplifier circuit which is suitable for IC implementation and which obtains an arbitrary amplification degree by controlling the clock frequency.

[Summary of the invention]

The present invention is characterized in that, in a switched capacitor type arithmetic circuit composed of an operational amplifier, a switch, and a capacitor, an arbitrary amplification degree is determined by the capacitance ratio of the switched capacitor circuit and the switching frequency. The main points are: (1) The switched capacitor circuit connected to the input side of the operational amplifier is switched faster than the switched capacitor circuit connected to the feedback side.

(2) Furthermore, one switched capacitor circuit on the input side is connected in parallel to switch this circuit even faster.

(3) The same circuit as in (2) above is further connected in parallel to
(2) This circuit is switched by an inverted clock.

In this way, for each switching, the values determined by the ratio to the feedback capacity are added one after another to obtain the desired degree of amplification.

[Embodiments of the invention]

FIG. 2 shows an embodiment of the switched capacitor operational amplifier of the present invention. In the figure, _S1 to _S10 are analog switches, _C1A , _C1B , _C2A , _C2B , and _C3 are capacitors, OP is an operational amplifier, V _I is an input voltage, and V _O is an output voltage. However, the symbol φ attached to S ₁ to S ₁₀
and or and means that the switches are driven by signals having mutually inverted phases.

Figure 3 shows each switch S ₁ to S ₁₀ in Figure 2.
An example of mode switching timing control pulses φ, , applied to When _the timing _control pulses φ, . In Fig. 3e, T ₁ and T ₃ are the times when the control pulse φ is at the “1” level, T ₂ and T ₄ are the times when the control pulse φ is at the “1” level, and T ₁ ′ and T ₃ ′ are the times when the control pulse φ is at the “1” level. T ₂ ' and T ₄ ' indicate the time when the control pulse is at the "1" level, respectively.

FIG. 4a shows a circuit state diagram of FIG. 2 at times T ₁ and T ₃ of FIG. 3. That is, at times T ₁ and T ₃ , φ becomes "1" and φ becomes "0", so that the analog switches S ₂ , S ₃ , S ₆ ,
S ₇ , S ₉ are turned on and analog switches S ₁ , S ₄ , S ₅ ,
Since S ₈ and S ₁₀ remain OFF, the circuit of Fig. 2 connects capacitors C _1A and C _2A as shown in Fig. 4 a.
is connected to the OP amplifier.

FIG. 4b shows the circuit state diagram of FIG. 2 at times T ₂ and T ₄ of FIG. 3. In other words, the switch
S ₂ , S ₃ , S ₆ , S ₇ , S ₁₀ are turned ON, and switches S ₁ , S ₄ ,
Since S ₅ , S ₈ , and S ₉ remain OFF, a capacitor C ₃ is newly connected to the circuit shown in FIG. 4A between the input terminal and one input terminal of the OP amplifier.

FIG. 4c shows a circuit state diagram of FIG. 2 at times T ₁ ' and T ₃ ' of FIG. 3. In other words, the switch
S ₁ , S ₄ , S ₅ , S ₈ , S ₉ are turned ON, and switches S ₂ , S ₃ ,
Since S ₆ , S ₇ , and S ₁₀ remain OFF, the circuit in Figure 2 is connected to the capacitor C _1B as shown in Figure 4 c.
and _2B are connected to the OP amplifier.

FIG. 4d shows a circuit state diagram of FIG. 2 at times T ₂ ' and T ₄ ' of FIG. 3. In other words, the switch
S ₁ , S ₄ , S ₅ , S ₈ , S ₁₀ are turned ON, and switches S ₂ , S ₃ ,
Since S ₆ , S ₇ and S ₉ remain OFF, a capacitor C ₃ is newly connected between the input terminal and one input terminal of the OP amplifier in the circuit shown in FIG. 4c.

Further, the circuit shown in FIG. 2 returns to the circuit state at time _T1 after time _T4 '. That is, the states shown in FIGS. 4a to 4d are repeatedly executed.

From the above operation, while the clock φ shown in Fig. 3 is "1", that is, while the capacitors C _1A and C _2A are connected to the OP amplifier in the circuit of Fig. 2, the output voltage is the capacitor C ₃ However, the number of times it is connected between the input terminal and one input terminal of the OP amp is pumped up by the relative ratio of C ₃ and C _2A . Furthermore, while the clock shown in Fig. 3 is "1", that is, in the circuit of Fig. 2, capacitors C _1B and C _2B are OP.
While connected to the amplifier, the output voltage pumps up by the relative ratio of C ₃ and C _2B the number of times capacitor C ₃ is connected between the input terminal and one input terminal of the op amp. Also, clock φ is “1”
When φ changes from “0” to “1”, capacitors C _1A and C _2A discharge, and when φ changes from “0” to “1” and from “1” to “0”. Then, by discharging capacitors _1B and _C2B , the pump-up is reset and each starts from 0.

The following formula shows the general formula for the output voltage pumped up n times while the clock φ is "1".

V _OA (n)={C _1A /C _2A +nC ₃ /C _2A }V _I ...(1) Furthermore, the general formula for the output voltage pumped up n times while the clock is "1" is shown.

V _O ′ _A (n) = {C _1B /C _2B +nC ₃ /C _2B }V _I ...(2) From equations (1) and (2) above, control the relative ratio of each capacitor value and the number of pump-ups. By doing so,
It can be seen that an output voltage of arbitrary magnitude can be obtained. Therefore, it is easy to see that by controlling the number of times the pump is pumped up, an amplifier circuit whose gain can be controlled can be obtained.

In this embodiment shown in the circuit of FIG. 2, the number of times of pumping up is two when φ and is "1", so the output voltage is calculated as follows from equations (1) and (2). is expressed in

V _OA (2)={C _1A /C _2A +2C ₃ /C _2A }V _I ...(3) V _O ′ _A (2)={C _1B /C _2B +2C ₃ /C _2B }V _I ...( 4) Furthermore, if the capacitors C _1A , C _1B , C _2A , C _2B and the pump-up capacitor C ₃ all have the same value, the output voltage is expressed by the following equation.

V _OA (2)=3·V _I ……(5) V _O ′ _A (2)=3·V _I ……(6) Also, this value is the final value of the pumped-up output voltage.

Figure 5 shows that in the circuit shown in Figure 2, when the number of pumps is 2, the input is a sine wave.
V _I =sinω The output voltage V _O at time t is shown in relation to the control clock.

In other words, at time T ₁ , the circuit in Figure 2 becomes Figure 4a, with no pump up and gains of C _1A and C _2A .
It is determined by the ratio of , and an output voltage with a gain of 1 is obtained.
Next, at time T ₂ , the state becomes Fig. 4 b, and the capacitor
It is pumped up by C ₃ and an output voltage with a gain of 2 is obtained. Next, at time T ₃ , it becomes Figure 4 a,
An output voltage with a gain of 2 can be obtained without pumping up. Next, at time T ₄ , it becomes Figure 4 b,
It is pumped up by capacitor C ₃ and an output voltage with a gain of 3 is obtained. Below, all capacitor values are the same and the relative ratio is 1, so do the same thing,
An output voltage with a gain of ₁ is obtained at time T1', a gain of 2 is obtained by pumping up at time _T2 ', a gain of 2 is obtained at time _T3 ', and a gain of 3 is obtained at time _T4 '.

In addition, the equivalent resistances of the analog switches S ₉ and S ₁₀ and the capacitor C ₃ which are part a of the circuit shown in Fig. 2 are shown in Fig. 6 a, b,
The configuration of c can also be constructed in the same way.

FIG. 7 shows an analog switch S ₁₁ , which is added to the circuit (dotted line) in FIG.
In this circuit, S ₁₂ and capacitor C ₄ are added, and while S 12 is “1”, capacitor C ₄ is connected between the input terminal and one input terminal of the OP amplifier. That is, it is connected alternately with capacitor _C3 . Furthermore, an analog switch _S12 for sample-and-hold and a capacitor _C3 are added, making it a switch capacitor operational amplifier circuit that can extract any output voltage.

FIG. 8 shows an example of a control clock for operating the circuit of FIG. 7. Further, in FIG. 8, a clock φ _S for sampling and holding the output is added to the control clock shown in FIG. 3.

FIG. 9 shows a circuit state diagram of the circuit of FIG. 7 using the control clock of FIG. 8. Further, FIG. 9 shows the clocks T ₁ , T ₃ , T 1 ', T ₁ ', whose clocks shown in FIG.
At time T ₃ ', capacitor C ₃ is connected between the input terminal and one input terminal of the OP amplifier, and the clock becomes "1".
By connecting capacitor C ₄ between the input terminal and one input terminal of the OP amplifier at times T ₂ , T ₄ to T ₆ , T ₂ ′, T ₄ ′ to _{T 6} ′, the capacitor is always
Indicates that C ₃ or C ₄ is connected.

Further, the circuit shown in FIG. 7 returns to the circuit state at time _T1 after time _T6 '. That is, from Figure 9 a to Figure 9
Repeat the state shown in Figure f.

From the above operation, as shown in Fig. 8, while the clock φ is "1", that is, in the circuit of Fig. 7, capacitors C _1A and C _2A , which are a to c in Fig. 9, are connected to the OP amplifier. The output voltage between the capacitor
For the number of times C ₃ is connected between the input and the op amp,
Pump up by the relative ratio of C ₃ and C _2A . Furthermore, the number of times capacitor _C4 is connected between the input and the op amp is pumped up by the relative ratio of _C4 and _C2A . Also, the output voltage is between d and f in Figure 9 when the clock is "1" as shown in Figure 8, that is, when capacitors C _1B and C _2B are connected to the OP amplifier in the circuit in Figure 7. is the same as when the clock φ is “1”, the capacitors C ₃ and C ₄
is connected between the input and the op amp, C ₃
and pump up by the relative ratio of C ₄ and C _2B . Therefore, in the circuit of Fig. 7, the circuit of Fig. 2 pumps up at all times due to the alternately connected capacitors _C3 and _C4 , whereas the circuit of Fig. 2 does not pump up at all times, resulting in a higher output voltage. can get.

In the following equation, in the circuit shown in Figure 7, the clock φ is "1".
The general formula for the output voltage pumped up n times during this period is shown below.

V _OB (n) = {C _1A /C _2A +nC ₃ /C _2A +nC ₄ /C _2A }V _I …(
7) Furthermore, the general formula for the output voltage that is pumped up n times while the clock is "1" is shown.

V _O ′ _B (n) = {C _1B /C _2B +nC ₃ /C _2B +nC ₄ /C _2B }V _I
...(8) From equations (7) and (8) above, by controlling the relative ratio of each capacitor value and the number of pump-ups,
Output voltage of arbitrary magnitude can be obtained. Furthermore, any gain in the pump-up process can be extracted from the sample-and-hold circuit at the subsequent stage.

In this embodiment, shown in the circuit of FIG. 7, C ₃ and C ₄
Since the number of pump up operations is 2,
The output voltage is expressed as follows.

V _OB (2)={C _1A /C _2A +2C ₃ /C _2A +2C ₄ /C _2A }V _I …(9) V _O ′ _B (2)={C _1B /C _2B +2C ₃ /C _2B +2C ₄ /C _2B }V _I …(1
0) Also, if each capacitor has the same value, the output voltage is expressed by the following formula.

V _OB (2)=5·V _I ……(11) V _O ′ _B (2)=5·V _I ……(12) Also, this value is the final value of the pumped-up output voltage.

FIG. 10 shows the output voltage when the input is a sine wave in the circuit shown in FIG. 7 in relation to each time T ₁ to T ₆ . That is, at time _T1 , the circuit in Figure 7 becomes a in Figure 9, pumping up from _C3 ,
An output voltage of 2 is obtained whose gain is the sum of the ratio of C _1A and C _2A and also the ratio of C ₃ and C _2A . Next, at time T ₂ , it becomes Figure 9 b, pumping up from C ₄ ,
The output voltage is further increased by the ratio of C ₄ and C _2A , resulting in an output voltage with a gain of 3. Then at time T ₃ ,
As shown in FIG. 9a, the output voltage is further pumped up by _C3 , and an output voltage with a gain of 4 is obtained. Next, at time _T4 , the output voltage is further pumped up by _C4 , and an output voltage with a gain of 5 is obtained.

Below, the output voltage from time T ₁ ′ to time T ₆ ′ is
Assuming all capacitor values are the same, the relative ratio is 1
Therefore, it is exactly the same as time T ₁ to time _{T 6} .

That is, an output voltage with a gain of 2 at time T ₁ ', a gain of 3 at time T ₂ ', a gain of 4 at time T ₃ ', and a gain of 5 at time T ₄ ' is obtained.

Here, if we sample and hold at times T ₄ and T ₄ ', the output voltage will be as shown in Figure 11a.
An output voltage waveform with a gain of 5 can be extracted, and it can also be made continuous. Furthermore, T ₁ and
By sampling and holding at time T ₁ ', an output voltage waveform with a gain of 2 can be extracted as shown in FIG. 11b.

FIG. 12 shows analog switches S _s1 to S _so in the output stage of the switched capacitor operational amplifier shown in FIGS. 2 and 7 that can arbitrarily vary the amplification degree.
This shows a circuit configuration in which a sample-and-hold circuit including a pair of capacitors C _s1 to _{C so} are connected in parallel.

With this configuration, a desired output voltage can be extracted at any time from the pumped-up output voltage using the clocks φ _s1 to _{φ so} , and multiple output voltages can be obtained with one switched capacitor operational amplifier.

In the switch capacitor operational amplifier described above, the value of each capacitor can be set freely, and furthermore,
By freely setting the clock that operates the switch that connects each capacitor to the OP amplifier, the output voltage can be pumped up with high resolution, making it possible to obtain a highly accurate amplifier.

〔Effect of the invention〕

According to the present invention: 1. Since the amplification degree setting can be determined by the capacitor ratio and the number of times charge is accumulated, an arbitrary gain can be obtained by varying the clock frequency for moving the charge.

2. Even if the capacitor ratio is small, a large amplification degree can be obtained depending on the clock frequency.

3. Furthermore, with regard to semiconductor integration, the chip area can be reduced, which is effective for high integration, miniaturization, and cost reduction.

Furthermore, since the relative ratio of the capacitors can be brought close to 1, a circuit with less influence on parasitic capacitance can be realized.

With these effects, a switched capacitor operational amplifier whose amplification degree can be easily varied can be obtained, which has great practical merits.

[Brief explanation of the drawing]

Fig. 1 shows a known amplifier, Fig. 2 shows the overall circuit configuration of the amplifier of the present invention, Fig. 3 shows an example of analog switch control timing pulses of the amplifier of the invention, and Fig. 4 shows various control timings of the amplifier of the invention. Mode state diagram, Figure 5 is an example of the output voltage when the input voltage is a sine wave, Figure 6 is a modification of the configuration of the analog switch of the amplifier of the present invention, and Figure 7 is the overall circuit of the modification of the amplifier of the present invention. Configuration, FIG. 8 shows an example of analog switch control timing pulses in a modification of the present invention, FIG. 9 is a diagram of various mode states depending on control timing in a modification of the present invention, and FIG. 10 shows an example of input voltage in a modification of the present invention. An example of the output voltage when the input voltage is a sine wave. Figure 11 is a sample-and-hold waveform example of the output voltage when the input voltage is a sine wave. Figure 12 is a circuit in which multiple sample-and-hold circuits are connected in parallel to the circuit of the present invention. This is a configuration example. OP... operational amplifier, S... analog switch,
C...Capacitor, V _I ...Input voltage, _Vp ...Output voltage, φ,,,...Analog switch drive signal.

Claims (1)

[Claims] 1. A series circuit consisting of a first and second switch that opens and closes in reverse linkage with each other, and a switch capacitor circuit consisting of a capacitor connected in parallel to the first switch are connected to the input circuit and feedback circuit of the operational amplifier, respectively. Two sets of switch capacitor circuits are provided in parallel, and the first switch of one of the two sets of switch capacitor circuits and the second switch of the other of the input circuit and the feedback circuit are opened and closed in conjunction with each other. A switch capacitor operational amplifier characterized in that a third switch capacitor circuit is added and the opening/closing cycle of the switch is set to 1/n (where n is an integer) of the opening/closing cycle of the other switch capacitor circuits.