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JPH0451985B2 - - Google Patents
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JPH0451985B2 - - Google Patents

Info

Publication number
JPH0451985B2
JPH0451985B2 JP58103024A JP10302483A JPH0451985B2 JP H0451985 B2 JPH0451985 B2 JP H0451985B2 JP 58103024 A JP58103024 A JP 58103024A JP 10302483 A JP10302483 A JP 10302483A JP H0451985 B2 JPH0451985 B2 JP H0451985B2
Authority
JP
Japan
Prior art keywords
gaas
film
insulating
insulating film
ultra
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58103024A
Other languages
Japanese (ja)
Other versions
JPS59227164A (en
Inventor
Hideki Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP58103024A priority Critical patent/JPS59227164A/en
Publication of JPS59227164A publication Critical patent/JPS59227164A/en
Publication of JPH0451985B2 publication Critical patent/JPH0451985B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]

Landscapes

  • Junction Field-Effect Transistors (AREA)

Description

【発明の詳細な説明】 (技術分野) 本発明は、GaAs絶縁ゲート型電界効果トラン
ジスタに関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a GaAs insulated gate field effect transistor.

(従来技術とその問題点) GaAsはSiに比べて電子移動度が数倍大きいた
め高速動作素子用の材料として期待されてきた。
ところが、Siでは熱酸化膜SiO2とSiとの界面が良
好であり、容器にMOSFETが実現できるが、
GaAsではどのような絶縁膜形成法を用いても界
面準位密度が高く、良好なMIS構造は得られてい
ない。このためGaAsの電界効果トランジスタと
してはGaAsと金属とのシヨツトキ障壁を利用し
たシヨツトキゲート型電界効果トランジスタ(以
下MESFETと略す)が用いられてきた。ところ
がGaAs MESFETではゲート電極に+0.8V以上
の正電圧を印加できないことから、エンハンスメ
ント型MESFETを用いたGaAsIC(DCFL)では
論理振巾を大きくとれないという問題点があつ
た。またシヨツトキゲートは熱や電気的シヨツク
に弱く破損しやすいことも問題であつた。
(Prior art and its problems) GaAs has electron mobility several times higher than that of Si, so it has been expected to be a material for high-speed operating devices.
However, with Si, the interface between the thermal oxide film SiO 2 and Si is good, and a MOSFET can be realized in the container.
GaAs has a high interface state density no matter what insulating film formation method is used, and a good MIS structure cannot be obtained. For this reason, as a GaAs field effect transistor, a shot gate field effect transistor (hereinafter abbreviated as MESFET), which utilizes a shot barrier between GaAs and a metal, has been used. However, with GaAs MESFETs, it is not possible to apply a positive voltage of +0.8V or more to the gate electrode, so GaAs ICs (DCFLs) using enhancement-type MESFETs have had the problem of not being able to achieve a large logic amplitude. Another problem was that the shot gate was susceptible to heat and electrical shock and was easily damaged.

ところが、GaAs絶縁ゲート電界効果トランジ
スタ(以下GaAs MISFETと略す)は、Siの
MOSFETに比べて動作速度が速く、またGaAs
のシヨツトキゲート電界効果トランジスタ
(MESFET)に比べてゲートに正電圧を加えるこ
とができるため、集積回路を形成したときの論理
振巾を大きくとれるという点、現在FET,ICが
用いられているあらゆる分野に用いることがで
き、その産業上の利用分野は極めて大きく、特に
高速処理が必要な分野、例えば計算機のCPV、
メモリ、画像処理等で利用が期待できるという点
から、GaAs MISFETの開発が強く要求されて
来ている。
However, GaAs insulated gate field effect transistors (hereinafter abbreviated as GaAs MISFETs) are
It has faster operating speed than MOSFET, and GaAs
Compared to short-gate field effect transistors (MESFETs), it is possible to apply a positive voltage to the gate, so the logic width when forming an integrated circuit can be increased, making it suitable for all fields where FETs and ICs are currently used. The field of industrial application is extremely wide, especially in fields that require high-speed processing, such as computer CPV,
There is a strong demand for the development of GaAs MISFETs as they are expected to be used in memory, image processing, etc.

GaAs MISFETの製造において、従来の方法
では、GaAs表面に絶縁膜を形成すると、絶縁膜
の種類によらず、Gaの空孔が生じ、界面準位密
度が大きくなるため、良好な界面が得られなかつ
た。
In the production of GaAs MISFETs, with conventional methods, when an insulating film is formed on the GaAs surface, Ga vacancies are generated and the interface state density increases, regardless of the type of insulating film, making it difficult to obtain a good interface. Nakatsuta.

(発明の構成) 本発明は、これらの問題点を解決するためにな
されたものであり、GaAsのMISFETの製造方法
を与えるものである。
(Structure of the Invention) The present invention has been made to solve these problems, and provides a method for manufacturing a GaAs MISFET.

以下本発明を説明する。 The present invention will be explained below.

このGaAs表面Gaの絶縁側への拡散を抑制する
ために発明者等は、SiO2のアルコール溶液にGa
をあらかじめ含ませ熱処理するとこにより、良好
な界面を得ている。また発明者等は、GaAs表面
の真空蒸着Alをちようど界面まで陽極酸化する
方法によつても良好な界面を得ている。しかし本
発明は、これらの絶縁膜形成法をさらに改善した
ものであり、超高真空中でGaAsの成長に引き続
き多量のGaを含んだAl膜を形成する方法を用い
るものである。
In order to suppress this diffusion of Ga on the GaAs surface to the insulating side, the inventors added Ga to an alcohol solution of SiO 2 .
A good interface was obtained by pre-impregnating and heat-treating. The inventors also obtained a good interface by anodizing the vacuum-deposited Al on the GaAs surface right up to the interface. However, the present invention further improves these insulating film forming methods, and uses a method of forming an Al film containing a large amount of Ga following the growth of GaAs in an ultra-high vacuum.

以下本発明の製造方法を図面に基づいて説明す
る。
The manufacturing method of the present invention will be explained below based on the drawings.

先ず第1図aに示すように半絶縁性GaAs基板
1上にSIドープn型GaAs層2を分子線エピタキ
シヤル法で1000Å成長させ、基板温度を低下させ
たのち、引き続き超高真空中でGaとAlの分子線
によりGaとAlとの固溶合金膜3を500Å成長させ
る。固溶合金中のGaのモル%は20〜80%である。
First, as shown in Figure 1a, an SI-doped n-type GaAs layer 2 of 1000 Å is grown on a semi-insulating GaAs substrate 1 by molecular beam epitaxial method, and after lowering the substrate temperature, GaAs layer 2 is grown in an ultra-high vacuum. A solid solution alloy film 3 of Ga and Al is grown to a thickness of 500 Å using molecular beams of Ga and Al. The mole percent of Ga in the solid solution alloy is 20-80%.

AlとGaとの固溶合金では、29℃以上では相分
離が起こつてしまうため基板を充分冷やしてから
Ga−Al膜を成長させている。
In solid solution alloys of Al and Ga, phase separation occurs at temperatures above 29°C, so cool the substrate sufficiently.
Ga-Al film is grown.

次に固溶合金膜3を酸素プラズマ中でちようど
固溶合金膜3がすべて絶縁膜4になるまで酸化す
る(第1図b)。
Next, the solid solution alloy film 3 is immediately oxidized in oxygen plasma until all the solid solution alloy film 3 becomes an insulating film 4 (FIG. 1b).

次に第1図cに示すように2領域の絶縁膜4を
除去する。
Next, as shown in FIG. 1c, two regions of the insulating film 4 are removed.

この後この領域にAuGeNiによる電極パターン
を形成し、450℃3分間熱処理してオーミツク電
極5,6とする(第1図d)。
Thereafter, an electrode pattern of AuGeNi is formed in this region and heat treated at 450° C. for 3 minutes to form ohmic electrodes 5 and 6 (FIG. 1d).

次に第1図eに示すようにオーミツク電極5,
6間の絶縁膜3上にAlのゲート電極7を形成す
る。
Next, as shown in FIG. 1e, the ohmic electrode 5,
A gate electrode 7 of Al is formed on the insulating film 3 between the gate electrodes 6 and 6.

Ga−Al膜を絶縁化する方法は、実施例で述べ
た酸素プラズマ中での陽極酸化法に限らず、たと
えば電解質溶液中での陽極酸化法でも良い。これ
らの方法でのGa−Al膜の酸化の終了の検知は、
陽極電圧一時間曲線の傾きの変化または干渉色の
出現によつて容易に検知できる。
The method for insulating the Ga-Al film is not limited to the anodic oxidation method in oxygen plasma described in the embodiment, but may also be an anodic oxidation method in an electrolyte solution, for example. Detection of completion of oxidation of Ga-Al film using these methods is as follows:
It can be easily detected by a change in the slope of the anode voltage one hour curve or by the appearance of interference colors.

(発明の効果) 本発明においては、下記の優れた効果がある。(Effect of the invention) The present invention has the following excellent effects.

GaAs層をいつたん大気中にさらすとGaAs
表面にGaAsのnative oxide膜ができてしま
い、良好な界面が得られないが、本発明では、
超高真空中でGaで含んだAl膜を成長させてい
るため上記問題はない。
When a GaAs layer is exposed to the atmosphere, GaAs
A GaAs native oxide film is formed on the surface, making it impossible to obtain a good interface, but in the present invention,
The above problem does not exist because the Al film containing Ga is grown in an ultra-high vacuum.

このGa−Al膜は、Gaを多量に含んでいるこ
とにより、酸化中あるいはその後の熱処理中に
Gaが絶縁膜中に拡散するのが抑えられる。
This Ga-Al film contains a large amount of Ga, so it can be used during oxidation or subsequent heat treatment.
Diffusion of Ga into the insulating film is suppressed.

このGa−Al膜はAlを含んでいることによ
り、電気提供率が高く耐薬品性も良い安定な酸
化膜を得る。
Since this Ga-Al film contains Al, a stable oxide film with a high electricity supply rate and good chemical resistance is obtained.

このGa−Al膜はAlを含んでいることによ
り、超高真空中であるにもかかわらず、GaAs
表面にごくわずか存在する酸素を吸収してい
る。
This Ga-Al film contains Al, so even though it is in an ultra-high vacuum, GaAs
It absorbs the very small amount of oxygen present on its surface.

(産業上の利用可能性) 上記実施例ではn型、GaAs層2を動作層とし
て用いており、ゲート電極に印加する電圧により
ゲート電極直下の空乏層の厚さを変え、動作層2
を流れる電流を変調する型のFETであるが、
FET構造はこの実施例に限るものではない。例
えばp-型層を動作層として用いた反転型の
MISFETにも本発明による絶縁膜形成法は適用
することができる。
(Industrial Applicability) In the above embodiment, the n-type GaAs layer 2 is used as the active layer, and the thickness of the depletion layer directly under the gate electrode is changed by the voltage applied to the gate electrode.
It is a type of FET that modulates the current flowing through the
The FET structure is not limited to this embodiment. For example, an inverted type using a p -type layer as the active layer
The insulating film forming method according to the present invention can also be applied to MISFET.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図a,b,c,d及びeは本発明による一
実施例の説明のための図であり、製造プロセスの
各段階での素子の断面構造を示すためのものであ
る。 1は半絶縁性GaAs基板、2はn型GaAs層、
3はGa−Al固溶合金膜、4はGa−Alの酸化膜、
5,6はオーミツク電極(AuGeNi)、7はゲー
ト電極(Al)である。
FIGS. 1A, 1B, 1C, 1D, and 1E are diagrams for explaining one embodiment of the present invention, and are for showing the cross-sectional structure of the device at each stage of the manufacturing process. 1 is a semi-insulating GaAs substrate, 2 is an n-type GaAs layer,
3 is a Ga-Al solid solution alloy film, 4 is a Ga-Al oxide film,
5 and 6 are ohmic electrodes (AuGeNi), and 7 is a gate electrode (Al).

Claims (1)

【特許請求の範囲】[Claims] 1 半絶縁性GaAs基板上に超高真空中で、
GaAs層を成長させる工程と、該GaAs層上にひ
き続き超高真空中でGaを多量に含んだAl膜を成
長させる工程と、該Al膜を絶縁化する工程と、
2領域の該絶縁膜を除去する工程と、該2領域に
オーミツク電極を形成する工程と、該2オーミツ
ク電極間の前記絶縁膜上にゲート電極を形成する
工程を含むGaAs絶縁ゲート型電界効果トランジ
スタの製造方法。
1 In an ultra-high vacuum on a semi-insulating GaAs substrate,
a step of growing a GaAs layer; a step of subsequently growing an Al film containing a large amount of Ga on the GaAs layer in an ultra-high vacuum; and a step of insulating the Al film;
A GaAs insulated gate field effect transistor comprising the steps of removing the insulating film in two regions, forming an ohmic electrode in the two regions, and forming a gate electrode on the insulating film between the two ohmic electrodes. manufacturing method.
JP58103024A 1983-06-08 1983-06-08 Method for manufacturing GaAs insulated gate field effect transistor Granted JPS59227164A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58103024A JPS59227164A (en) 1983-06-08 1983-06-08 Method for manufacturing GaAs insulated gate field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58103024A JPS59227164A (en) 1983-06-08 1983-06-08 Method for manufacturing GaAs insulated gate field effect transistor

Publications (2)

Publication Number Publication Date
JPS59227164A JPS59227164A (en) 1984-12-20
JPH0451985B2 true JPH0451985B2 (en) 1992-08-20

Family

ID=14343072

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58103024A Granted JPS59227164A (en) 1983-06-08 1983-06-08 Method for manufacturing GaAs insulated gate field effect transistor

Country Status (1)

Country Link
JP (1) JPS59227164A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6231170A (en) * 1985-08-02 1987-02-10 Agency Of Ind Science & Technol Structure of compound semiconductor device

Also Published As

Publication number Publication date
JPS59227164A (en) 1984-12-20

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