JPH0452473B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data display device used in an information processing system.

[Conventional technology]

When displaying text on a Kirakuta display such as a CRT display device, there are two types of display: horizontal writing and vertical writing.
There is a street. Normally, when a document is created using a world processor or the like, it is displayed in horizontal writing mode, but there are times when it is necessary to display the document in vertical writing mode or convert it to horizontal writing mode. In the case of vertical writing display, the display data stored in the screen buffer in a form corresponding to the screen may be displayed as is. but,
When converting from horizontal to vertical display, generally
On a CRT, as shown in Figure 1a, the number of horizontal characters is greater than the number of vertical characters, so the display must be converted to vertical writing, resulting in the lower text protruding from the screen, as shown in Figure 1b. It is necessary to scroll up to see the text that is protruding from the top of the screen, or scroll down to see the text that is protruding from the top of the screen. Alternatively, it is necessary to display a text in one column over two columns as shown in FIG. 1c.

[Problem to be solved by the invention]

However, when viewing the screen by scrolling, there was a problem in that the sentences were cut off in the middle, making it impossible to view the entire text at once. In addition, in the case of repeat display, the load on the software increases and one line of text is displayed in two lines, resulting in a different image from what should be created. Moreover, since the conversion was done using software, there was a problem that the display speed was slow.

An object of the present invention is to enable data displayed horizontally to be displayed in an easy-to-read manner even when vertically displayed.

[Means to solve the problem] The means of the present invention are as follows.

A screen buffer for storing display data for at least one screen; a specification means for specifying either horizontal writing display or vertical writing display; and when horizontal writing display is specified, the data is stored in the screen buffer. a first display control means that sequentially reads the display data stored in the display screen according to matrix specifications and controls the display output on the display screen; and when vertical writing display is specified, the display data stored in the screen buffer is A second display control means is provided which sequentially reads out the data by inverting the matrix designation, compresses the data in the vertical direction, and controls the display output on the display screen.

[Effect]

The operation of the means of the invention is as follows.

When the horizontal writing display is specified by the specifying means, the first display control means operates, and the display data for one screen stored in the screen buffer is sequentially read out according to the matrix specification and is displayed as it is on the display screen. Is displayed. At this time, when the vertical writing display is specified, the second display control means operates, and the row and column specifications of the display data stored in the screen buffer are inverted and sequentially read out, and this data is displayed on the display screen. It is displayed compressed vertically at the top.

Therefore, when switching one screen worth of data displayed on the display screen in horizontal writing display to vertical writing display, it is possible to optimize the data display on the display screen, and the display can be easily viewed in the vertical direction.

When displaying text on a character display such as a CRT display device, there are two types of display: horizontal writing display and vertical writing display. Normally, when a document is created using a world processor or the like, it is displayed in horizontal writing mode, but there are times when it is necessary to display the document in vertical writing mode, or to convert the horizontal writing mode into vertical writing mode. In the case of vertical writing display, the display data stored in the screen buffer in a form corresponding to the screen may be displayed as is. However, when converting a horizontal writing display to a vertical writing display, generally on a CRT, the number of horizontal characters is greater than the number of vertical characters as shown in Figure 1a, so if you convert to a horizontal writing display, the number of characters from the bottom of the screen as shown in Figure 1b is The text sticks out. It is necessary to scroll up to see the text that protrudes from the top of the screen, or to scroll down to see the text that protrudes from the top of the screen. Alternatively, it is necessary to display a text in one column over two columns as shown in FIG. 1c. However, when viewing the screen by scrolling, there was a problem in that the sentences were cut off in the middle, making it impossible to view the entire text at once. In addition, in the case of repeated display, the load on the software increases and one line of text is displayed in two lines, resulting in a different image from the text to be created. Moreover, since the conversion was done using software, there was a problem that the display speed was slow.

The present invention was made in view of the above-mentioned drawbacks.In the case of horizontal writing display, non-interlace is used for display, and in the case of horizontal writing display, interlace is used to display the vertical width of the screen in non-interlace. The purpose is to provide a character display display method that can compress the text to half the time and display the entire text at once even in vertical writing.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram for explaining non-interlace and interlace. FIG. 2a shows a non-interlaced character display, and FIG. 2b shows an interlaced character display.

In other words, in non-interlaced display, one screen is created by scanning the bright spot from the upper left to the lower right once, but in interlaced display, the rising edge of the vertical synchronization signal is shifted by 1/2 for each frame. This method creates one screen by scanning the screen twice, which apparently doubles the number of rasters and halves the screen vertically.
Compress to 2. The solid lines in FIG. 2b are the first scanning lines, and the broken lines are the second scanning lines. In this way, the displayed characters in FIG. 2b are halved in the vertical direction compared to the displayed characters in FIG. 2a.

Next, the configuration of the embodiment will be explained. In FIG. 3, 1 is a screen buffer in which display data for two screens is stored. A CPU (not shown) selects channel 1 of multiplexers 2a and 2b and channel 1 of multiplexer 2c, specifies the address of screen buffer 1, and writes display data. Screen buffer 1
When display data is read from the multiplexers 2a, 2b, and 2c, channel 0 is selected. 3 is a character generator which converts the display data of the screen buffer 1 into character pattern data and sends out the character pattern data specified by the address. Reference numeral 4 denotes a shift register for parallel/serial conversion, which converts the parallel data sent from the character generator 3 into serial data, shifts it, and outputs it. The output signal becomes a video signal. Reference numeral 5 denotes an oscillation circuit which sends its pulses to the dot counter 6 and also to the parallel/serial conversion shift register 4 as shift pulses. When the dot counter 6 counts and reaches a constant value, a pulse is output to a 1/2H counter 7 that counts 1/2 horizontal period and a column up/down counter 8. 9 is an H counter that counts columns. As shown in FIG. 4, when the 1/2H counter 7 counts 2, the H counter 9 counts 1 and outputs a horizontal synchronizing signal. Reference numeral 10 denotes an R counter for counting rasters, which specifies the address of the character generator 3 and outputs a pulse to the row counter 11 when a constant value is reached.

Horizontal/vertical is a signal for commanding horizontal writing display and vertical writing display, SW is a switch for selectively switching between the two screens, 12a and 12b are AND circuits, 13 is an OR circuit, and I is an inverter circuit. AND circuit 1
2a inputs the most significant bit of the row counter 11 and horizontal/vertical signals via the inverter circuit I. The AND circuit 12b receives the switch SW state and horizontal/vertical signals as inputs. The OR circuit 13 inputs the outputs of the AND circuits 12a and 12b.
Additionally, the output of the OR circuit is added to the address bus of the row counter 11 as the most significant bit, and the bus line
Channel 1 of multiplexer 14a as LB
and is added to channel 0 of multiplexer 14b. The count value of the column up/down counter 8 is added to channel 0 of the multiplexer 14a and channel 1 of the multiplexer 14b, and when the horizontal/vertical signal status is 1, channel 1 is set, and when the status is 0, channel 0 is added. is selected and its output is supplied to channel 0 of the multiplexers 2a and 2b. On the other hand, when the 1/2H counter 7 counts up to a certain value, the pulse is sent to the vertical brisset counter 15.
Output to. In addition, a vertical brisset counter 15
The vertical set parameter is sent from the CPU, and when non-interlaced, the number of rasters x 2 =
N is set, but in the case of interlace, the number of rasters×2+1=N+1 is set. The pulses input to the vertical preset counter 15 are counted, and when the vertical set parameter from the CPU is reached, a vertical synchronization signal is output. As shown in FIG. 4, during non-interlacing, when the output of the 1/2H counter 7 reaches the vertical set parameter (N) from the CPU, the vertical preset counter 15 outputs a vertical synchronizing signal. This will make it non-interlaced and display it. Also, when interlaced, 1/
When the output of the 2H counter 7 reaches the vertical set parameter (N+1) from the CPU, the vertical preset counter 15 outputs a vertical synchronizing signal. in the end,
Interlace display is performed in a manner that shifts by the output of the 1/2H counter 7.

Next, the operation of the above embodiment will be explained.
When the CPU writes to screen buffer 1,
Specify the address via channel 1 of multiplexers 2a, 2b and 2c, and
Write display data via c. Next, the operation of reading display data from the screen buffer 1 will be explained. The oscillation circuit 5 is oscillating and sending its output to the dot counter 6.
When the dot counter 6 reaches a certain value, the column up/down counter 8 and the column counter 7
Outputs pulses to Next, since horizontal writing display and vertical writing display have different operations, they will be considered separately. First, in the horizontal writing display mode, the vertical set parameter (N) is set in the vertical preset counter 15, and the horizontal/vertical status becomes "1". The column up counter 8 then functions as an up counter. The 1/2H counter 7 similarly counts up, and when it reaches a certain value, sends a pulse to the vertical preset counter 15. This pulse is counted by the vertical preset counter 15, and when the count value reaches the vertical set parameter (N), the vertical preset counter 15 outputs a vertical synchronizing signal. On the other hand, the H counter 9 generates a horizontal synchronizing signal and sends its output to the R counter 10. Further, the output of the R counter 10 is sent to the row counter 11. The row counter 11 and column up/down counter 8 are sent to multiplexers 2a, 2b via channel 1 of multiplexers 14a, 14b for horizontal display. Since channel 0 is selected, these multiplexers 2a and 2b designate the address and column address of the first row of the screen buffer.
That is, in the case of horizontal writing display, the column up/down counter 8 reads the column address of the screen buffer 1,
A line counter 11 specifies a line address of the screen buffer 1. The display data at the designated address is sent to the character generator 3 via channel 0 of the multiplexer 2c and converted into character pattern data. Then, the data is addressed by the count value of the R counter 10 and sent to the parallel/serial conversion shift register 4, and is shifted as serial data using the dot pulse from the oscillation circuit 5 as a shift clock and output as a video signal. Become. At this time, when the switch SW is turned on, the output of the AND circuit 12b is "0" because the horizontal/vertical status is "1". Therefore, the output of the OR circuit 13 becomes "0", that is, the most significant bit of the bus line LB becomes "0", and the first screen of the two screens of the screen buffer 1 is accessed. Conversely, if the switch is turned OFF, the most significant bit of the bus line LB becomes "1", so the second
The line counter 11 accesses the screen. In other words, you can change the screen using the switch SW.

Next, in the case of vertical display mode, the vertical preset counter 15 is set to the vertical set parameter (N+
1) is set, and the horizontal/vertical status becomes "0". The column up counter then works as a down counter. 1/2H counter 7,
The H counter 9 and the R counter 10 operate in the same manner as in the horizontal writing display mode. The vertical preset counter 15 counts in the same way as in the horizontal writing mode, and when this count value reaches the vertical set parameter (N+1) from the CPU, the vertical preset counter 1
5 outputs a vertical synchronization signal. On the other hand, column up/
The down count value of the down counter 8 and the count value of the row counter 11 are the row address and column address of the screen buffer 1 through channel 0 of the multiplexers 14a and 14b, respectively, since the horizontal/vertical status is "0". Specified. That is, the column down count value specifies the row address, and the row counter value specifies the column address. For example, an address is specified for the screen buffer 1 corresponding to FIG. 1a in the form of vertical writing as shown in FIG. The addressed display data becomes a video signal through a character generator 3 and a shift register 4 for parallel/serial conversion, similar to the horizontal display. At this time, since the horizontal/vertical status is "0", the gate of the AND circuit 12a is open, and the most significant bit of the row counter 11 is enabled.
Therefore, the most significant bit of the row counter 11 is coupled to the most significant bit of the bus line LB.
can access all column addresses of screen buffer 1.

In this way, if you specify the row address of screen buffer 1 corresponding to the horizontal writing display screen with the column down count value and the column address with the row count value, the entire horizontal writing display screen will be displayed vertically using compressed interlace display. Moreover, two horizontal writing screens can be displayed on one vertical writing screen. Furthermore, in the case of horizontal writing display, if there is display data for two screens in the screen buffer, one screen's worth of display data can be selected by a switch.

It goes without saying that the present invention can also be implemented in devices other than CRT devices, such as plasma display devices and liquid crystal display devices.

〔Effect of the invention〕

According to the present invention, it is possible to optimize the data display on the display screen when switching one screen worth of data displayed on the display screen in horizontal display to vertical display, and it is possible to display data that is easy to see in the vertical direction. .

[Brief explanation of drawings]

Figure 1a shows a horizontal writing display, Figures 1b and c show a conventional example of a vertical writing display, Figure 2a shows a non-interlaced display, and Figure 2b shows an interlaced display. 3 is a circuit configuration diagram of an embodiment of the present invention, FIG. 4 is a time chart diagram for explaining the operation of an embodiment of the present invention, and FIG. 5 is an embodiment of the present invention. FIG. 7 is a diagram illustrating vertical writing display according to an example. 1...Screen buffer, 2a, 2b, 2c
...Multiplexer, 3...Character generator, 4...Shift register for parallel/serial conversion, 5...Oscillation circuit, 6...Dot counter, 7...1/2H counter, 8...Column up. Down counter, 9...H counter, 10...R counter, 11...line counter, 12a, 12b...
...AND circuit, 13...OR circuit, 14a, 14
b...Multiplexer, 15...Vertical preset counter, SW...Switch, I...Inverter circuit.

Claims (1)

[Scope of Claims] 1. A screen buffer for storing display data, a specifying means for specifying either horizontal writing display or vertical writing display, and when horizontal writing display is specified, the screen buffer is a first display control means that sequentially reads out stored display data according to row and column specifications and controls the display output on the display screen; A data display device comprising: second display control means for sequentially reading out display data with the row and column designation reversed, compressing it vertically onto the display screen, and controlling the display output.