JPH0452552B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a frequency detection circuit, and is particularly applicable to a digital recording/reproducing system to detect information recorded using a predetermined modulation method in which maximum and minimum inversion periods are determined. The present invention relates to a frequency detection circuit that detects the maximum or minimum inversion period when demodulating a signal.

[Technical background of the invention]

The so-called PCM method (Pulse Cord Modulation) converts signals that are inherently analog information, such as acoustic signals (audio signals), into digital signals.
In recent years, the use of systems has been gaining momentum due to its advantages such as improved quality of recording and reproduction signals. Applicable
When recording an audio signal according to the PCM method, an analog signal is sampled, quantized, and encoded, and finally a digital signal having two levels is stored on an information recording medium such as an optical disk (DAD: Digital Audie Disk). (named). At this time, the signal is subjected to error correction processing and then modulated, and the modulation method is, for example,
EFM (Eight to Fourteen Modulation), 3PM
(3Poaition Modulation) etc. are applied, and the maximum and minimum inversion periods are determined.

A conventional frequency detection circuit basically includes an edge detection circuit, a counter, a comparator, and a register (for example, a register for storing the maximum inversion period), and the pulse edge of the reproduced input signal is detected by the edge detection circuit. Detected and fed to the counter. A counter counts detected pulse edge intervals of the input signal based on the demodulated clock signal. The count value of the counter is supplied to a comparator where it is compared with the register value from the maximum inversion period (Tmax) storage register. In the comparison process in the comparator,
If the counter value of the counter is larger than the register value of the Tmax register, the counter value of the counter is loaded into the Tmax register as a new register value. Through such operations, the maximum inversion cycle value (Tmax) for a predetermined period can be stored in the register.

[Problems with background technology]

According to the conventional frequency detection circuit configured as described above, in order to improve the detection resolution when detecting the maximum or minimum inversion period, it was necessary to set the frequency of the demodulated clock signal high. For example, in order to double the detection resolution, a demodulated clock signal with twice the clock frequency must be supplied to the counter. Therefore, the counter in this case must have a margin sufficient to operate in synchronization with the high frequency clock signal. However, improving the clock margin of the counter is not desirable because it complicates the configuration of the counter and increases manufacturing costs. That is, conventionally,
If the counter does not have the required clock margin, there is a problem in that it cannot be expected to improve the detection resolution. Further, it has not been possible to perform any effective processing not only for improving the detection resolution but also for reducing the clock margin of the counter in frequency detection circuits having the same resolution.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and its purpose is to reduce the clock margin of the counter required in accordance with the detection resolution, and thereby to easily improve the detection resolution. To provide the circuit.

[Summary of the invention]

The frequency detection circuit of the present invention includes a count section that counts pulse edge intervals of a digital input signal having an inversion period limit value uniquely set according to a predetermined modulation method based on a clock signal having a predetermined frequency; a register section that stores
It includes a comparator section that compares the outputs from the counter section and the register section with each other. A plurality of the counter sections are provided and connected in parallel to each other. The outputs from each counter section are added together and supplied to a comparator section, and in this case, a signal having a frequency equal to or divided from the frequency of the clock signal is supplied to each of the plurality of counter sections as a clock signal. . This makes it possible to achieve the above-mentioned purpose.

[Embodiments of the invention]

First, an overview of an optical (CD type) digital audio disk (DAD) playback device to which an embodiment of the present invention is applied will be explained.

As shown in FIG. 1, an information recording medium, for example, an optical disk 54, is mounted on a turntable 52 that is rotationally driven by a disk motor 50.
is reproduced by the optical pickup 56. In this case, the optical pickup 56 irradiates the signal recording surface of the optical disk 54 with the light emitted from the semiconductor laser 56a via the beam splitter 56b and the objective lens 56c, and applies a predetermined modulation method such as EFM to the optical disk 54. The reflected light from the pits (irregularities with different reflectances) corresponding to the digital (PCM) data of the information signal (audio signal) recorded in the form of both modulation and interleaving is transmitted to the objective lens 56c and the beam splitter 56.
It leads to a four-part photodetector 56d via b. The four-division photodetector 56d is configured to be able to output the four reproduction signals photoelectrically converted to the outside.
It is linearly driven in the radial direction of 4.

The four reproduced signals from the four-division photodetector 56d are supplied to the matrix circuit 60 and subjected to a predetermined matrix calculation process, thereby producing a focus error signal F, a tracking error signal E, and a high frequency signal RF. separated into

The focus error signal F is sent to the focus servo system of the optical pickup 56 along with the focus search signal from the focus search circuit 62.
Used to drive FS. Further, the tracking error signal E is transmitted to a system controller 64 which will be described later.
The optical pickup 56's tracking servo system TS
and linear tracking control of the pick-up feed motor 58.

The high frequency signal R is supplied to the reproduction signal processing system 66 as a main reproduction signal component. The reproduced signal processing system 66 first guides the reproduced signal to a waveform shaping circuit 70 controlled by a slice level (eye pattern) detector 68 to separate unnecessary analog components and necessary data components. only
The signal is supplied to a PLL type synchronous clock regeneration circuit 72 and an edge detector 74a of a signal processing system 74.

In this situation, the synchronous clock regeneration circuit 72
The synchronization clock from the synchronous signal is guided to the synchronization signal separation clock generation circuit 74b in the signal processing system 74 for data use, and is used to generate a synchronization signal separation clock signal.

On the other hand, the reproduced signal that has passed through the edge detector 74a is supplied to a synchronization signal detector 74c, where the synchronization signal is separated by the synchronization signal separation clock signal and EFM demodulated by a modulation circuit 74d. In addition, the synchronization signal is transmitted to the synchronization signal protection circuit 74.
e, protected to prevent malfunction,
It is led to the input data processing timing signal generation circuit 74f together with the synchronization signal separation clock signal.

Further, the demodulated signal is supplied to an input/output control circuit 76a of another signal processing system 76, which will be described later, via a data bus input/output control circuit 74g, and the control signal and display signal components, which are subcodes, are , control display processing circuit 74h
and is supplied to the subcode processing circuit 74i. The subcode data subjected to necessary error detection and correction by the subcode processing circuit 74i is transmitted to the system controller 64 via the system controller interface circuit 74g.

The system controller 64 includes a microprocessor interface circuit, a driver integrated circuit, etc., and a control switch 78.
A command signal from the DAD playback device is used to control the DAD playback device to a desired state and to display the above-mentioned subcode (for example, index information of the playback song, etc.) on the display 80.

The timing signal from the input data processing timing signal generation circuit 74f is provided for controlling the data bus input/output control circuit 74g via the data selection circuit 74j. At the same time, the timing signal is transmitted via the frequency detector 74k, the phase detector 74l, and the PWM modulator 74m to automatic frequency control (AFC) and automatic phase control for driving the disc motor 50 in a constant linear velocity (CLV) manner. Provided for control (APC).

In this case, the phase detector 74l is supplied with a system clock signal from a system clock generation circuit 74p that operates based on an oscillation signal from a crystal oscillator 74n.

The demodulated data passing through the input/output control circuit 76a of the other signal processing circuit 76 is sent to the syndrome detector 76 for error detection and correction or correction.
b, error pointer control circuit 76c, correction circuit 7
The data is subjected to necessary error correction, deinterleaving, error correction, and other processing via the data output circuit 76d and the data output circuit 76e, and then supplied to the digital/analog (D/A) converter 82.

In this case, the external memory control circuit 76f cooperates with the data selection circuit 74j to control the external memory 84 in which data necessary for correction is stored, thereby performing correction via the input/output control circuit 76a. It is designed to capture the necessary data. Additionally, the timing control circuit 76
g functions to supply a timing control signal necessary for error correction and correction based on the system clock signal from the system clock generation circuit 74p.

The mutating (detection) control circuit 76h operates during error correction and on the basis of the output from the error pointer control circuit 76c or the control signal given via the system controller 64.
Performs predetermined muting control required at the start and end of operation of the DAD playback device.

The audio reproduction signal thus converted into an analog signal by the D/A converter 82 is supplied to the speaker 90 via the low-pass filter 86 and amplifier 88.

Hereinafter, one embodiment of the present invention will be described which is provided as a means for controlling the PLL circuit 72 shown in FIG. A frequency detection circuit according to an example will be described.

FIG. 2 shows a frequency detection circuit according to a first embodiment of the present invention. The digital input signal reproduced by the optical pickup 56 from the optical disk 54 (FIG. 1) has a known maximum inversion period Tmax and minimum inversion period Tmin determined in advance, for example, according to EFM modulation. The input signal 100 is provided to an edge detection circuit 102. This edge detection circuit 102 detects a pulse edge and generates a counter control signal 104. The counter control signal 104 is supplied to two counters 106 and 108 that are connected in parallel to each other. Clock input terminal 110 is connected to one counter 108 and, via an inverter 112, to the other counter 106. Therefore, the demodulated clock signal 114 is inverted by the inverter 112 and then supplied to the counter 106. Counter 106 counts the pulse edge intervals of input signal 100 based on the inverted demodulated clock signal, and counter 108 operates in the same manner as described above based on the demodulated clock signal. The output terminals of these counters 106 and 108 are connected to an adder 116.
The count values 118 and 120 of the counters 106 and 108 are supplied to the adder 116.

When adder 116 receives the next pulse edge in input signal 100, both counters 106,1
Addition processing is performed on the output of 08, and the added data 122
is applied to the first input of the comparator 124. The second input terminal of the comparator includes, for example, a counter type register 1 for storing the maximum inversion period value.
26 are connected. The counter type register 1
26 supplies a register value 128 corresponding to Tmax to comparator 124. Comparator 124
is the above addition data 122 and register value 123
The added data 122 is the register value 1.
28, the output pulse 130 is transmitted to the counter type register 126, thereby setting the register value of the counter type register 126 to “1”.
The count is increased by 1. After repeating the above operation for a predetermined period of time, the counter type register 126 outputs a register value 132 as the final maximum inversion period counted at twice the frequency of the demodulated clock signal 114. do.

According to the first embodiment of the present invention configured in this way, two counters 106 and 108 are provided,
One of them is configured to count pulse intervals by supplying an inverted version of the demodulated clock signal 114. In addition, both counters 10
Counter values 118,120 from 6,108 are added and compared to the register value of Tmax register 126. Therefore, the resolution related to frequency detection can be substantially doubled without setting the clock frequency of the demodulated clock signal 114 for operating the counter high. Therefore, the time margin required for the counters 106 and 108 is the same as in the conventional case, and as a result, the clock margin can be reduced.

FIG. 3 shows a frequency detection circuit according to a second embodiment of the present invention. Note that the same reference numerals are given to the same components as in the first embodiment described above, and the explanation thereof will be omitted. The clock input terminal 110 is connected to the N-stage shift register 14 via the N frequency divider 140.
2, the demodulated clock signal 114 is first divided by N, and then the demodulated clock signal 114 is connected to the N-stage shift register 142.
The signals are sequentially shifted and outputted from N output terminals. The N output terminals of the N-stage shift register are connected to N mutually parallel counters 144-1, 1, respectively.
44-2, 144-3, . . . , 144-N. N counters 144-1, 144-
2, 144-3, . . . , 144-N are supplied with a counter control signal 104 from the edge detection circuit 102, respectively. The outputs of these counters are connected to an adder 146.

According to the second embodiment of the present invention configured in this manner, the frequency of the demodulated clock signal 114 is divided by N, and the frequency of the demodulated clock signal 114 is divided by N.
N counters 144-1, 144-2, 144-3, . . . , 14 through the stage shift register 142.
4-N as a clock signal, and the outputs of the counters are all added together and then input to the comparator 124. Therefore, the clock margin required for each counter to obtain equivalent frequency detection resolution can be substantially reduced to 1/N.

It should be noted that the present invention is not limited to the embodiments described above, and it goes without saying that various modifications may be made within the scope of the present invention by those skilled in the technical field to which the present invention pertains. For example, in the above-mentioned implementation sequence, frequency detection is performed using the maximum value (Tmax) of the inversion periods set according to the EFM, but the invention is not limited to this, and the minimum inversion period (Tmin) is used for frequency detection. You can get the same effect either way. That is, in this case, the magnitude relationship between the data to be processed related to the comparison process by the comparator may be set to be reversed, and a down counter type register may be used as the counter type register.

As described above, according to the present invention, it is possible to provide a frequency detection circuit that can easily improve the detection resolution by reducing the counter clock margin required in accordance with the detection resolution. can.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the basic overall configuration of a digital audio disk (DAD) playback device to which a frequency detection circuit is applied, and Fig. 2 shows a frequency detection circuit according to a first embodiment of the present invention. Block Diagram FIG. 3 is a block diagram of a frequency detection circuit according to a second embodiment of the present invention. 102...edge detection circuit, 106, 108, 1
44-1, 144-2, 144-3,..., 144
-N... Counter, 116, 146... Adder, 12
4...Comparator, 126...Counter type register, 140...N frequency divider, 142...N stage shift register.

Claims (1)

[Claims] 1. A plurality of counter means connected in parallel to each other for counting pulse edge intervals of a digital input signal having an inversion period limit value uniquely set according to a predetermined modulation method based on a clock signal having a predetermined frequency. , which is connected to the plurality of counter means and generates a signal whose phase is inverted at a frequency equivalent to that of the clock signal, or a signal whose frequency is divided and whose phase is shifted from each other, and which is sent to the counter means as a counter clock signal. clock signal supply means for supplying clock signals respectively, register means for storing data, addition means for adding together the count value signals output from the plurality of counter means, and outputs from the addition means and the register means. comparator means for comparison, and storage in the register means in response to the comparison result of the comparator means when the outputs of the addition means and the register means satisfy a predetermined relative magnitude relationship within a predetermined period. A frequency detection circuit characterized in that data is updated and the updated data is held in the register means as data corresponding to the inversion cycle limit value.