JPH0452971B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] Priority processing and latch processing are performed on input data, and the output thereof is held until the processing on the data is completed to prevent malfunction of the circuit.

[Industrial application field]

The present invention relates to a data priority latch circuit used in digital transmission equipment and the like.

[Conventional technology]

According to the conventional technology, as a method of processing interrupt request signals, a level indicating the priority is determined for each interrupt request signal, and each interrupt request signal is once input to a priority circuit, and then Usually, a method is adopted in which the order is assigned according to a predetermined priority order, and interrupt request signals from the same lever are processed starting from the earliest one in terms of time.

[Problem that the invention seeks to solve]

However, in the conventional method described above, when there are multiple causes for generating a certain interrupt request signal, if an interrupt from another factor occurs at the same level during interrupt processing, the processing for the previous factor ends. Even if a factor is cleared, the interrupt request signal will not be restored unless other factors are cleared, so the edge of the interrupt request signal cannot be seen at the same level, and no interrupt requests will occur. It was hot.

[Means for solving problems]

As shown in Fig. 1, the above problems include a priority circuit A that determines the priority of input data, a latch circuit B that latches the output from the priority circuit A, and a latch circuit B that latches the latched contents of the latch circuit B. a status circuit C for notifying an external device; a control circuit E for outputting a control signal when the input data and the latch output of the latch circuit B exist; and a control circuit E for outputting a control signal when the input data and the latch output of the latch circuit B are present; Latch circuit B
Outputs a continuation signal to continue the latched state,
This problem is solved by a data priority latch circuit comprising a timing circuit D which outputs a reset signal to release the latch state of the latch circuit B when the input data is withdrawn and the control signal disappears.

[Effect]

According to the present invention, there is a certain interrupt request signal, and the latch circuit latches the interrupt request signal, so even if an interrupt request of the same level occurs, the interrupt will be canceled if the previous cause is cleared after the previous interrupt processing is completed. Once the interrupt request signal is restored, another request generates the interrupt request signal again, so the edge of the interrupt request signal is visible for interrupts of the same level, so interrupt processing is performed again, and interrupt operation is guaranteed. This gives rise to the advantage of

〔Example〕

The data priority latch circuit referred to here is to which a large number of interrupt request signals are applied, and if only a certain interrupt request signal is applied to this data priority latch circuit, it produces an output and continues to maintain this state. This is a circuit in which an interrupt request signal that is once held continues to be held until the signal becomes invalid, even if a higher priority interrupt occurs in the meantime.

FIG. 1 is a principle diagram of a data priority latch circuit according to the present invention.

In the figure, A is a priority circuit, B is a latch circuit, and C
is a status circuit, D is a timing circuit, and E is a control circuit. The same symbols represent the same objects throughout all the figures below.

As shown in FIG. 1, the present invention is composed of a priority circuit A, a latch circuit B, a status circuit C, a timing circuit D, and a control circuit E, making it possible to extract necessary signals from input data. It is something.

Among the plurality of input data which are interrupt requests, the one with the highest priority is selected by the priority circuit A and outputted to the latch circuit B.

In latch circuit B, the latch element corresponding to its output is temporarily latched, and a latch output is output.

This latch output is input to a status circuit C, which outputs a signal notifying an external processor MPU (not shown) which input data is latched.

The latch output is also input to the control circuit E at the same time.
Control circuit E outputs a control signal when both latch output and input data are present.

This control signal is input to the timing circuit D,
When it is confirmed by counting the clock signal CLK that the control signal continues for a predetermined period of time, a continuation signal is outputted to the latch circuit B to cause the latch circuit B to continue the latched state.

This continuation signal causes latch circuit B to continue the latch state, and at the same time outputs an interrupt request generation signal *INTR to the external processor MPU.

This operation of timing circuit D is to prevent latch circuit B from becoming latched due to short-time pulses such as noise.

When the input data disappears, the control signal is no longer output from the control circuit E, and the timing circuit D outputs a reset signal for causing the latch circuit B to release the latch state.

Therefore, the external processor MPU is automatically reset without resetting the latch circuit B after interrupt processing.

FIG. 2 is a detailed circuit diagram of one embodiment of a data priority latch circuit according to the present invention.

In the figure, 1 is an encoder, 2 is a decoder, and 3 is 8
Bit latch circuit, 4 and 5 are NAND gate circuits, 6 is a three-state buffer, 7 is a NAND gate circuit, 8 is a counter, 9 is a D-type flip-flop, 10 is a NAND gate circuit, 11 is a resistor circuit, 12 and 13 are inverters, 14 is a NAND gate circuits 15 and 16 are OR gate circuits.

In FIG. 2, encoder 1 and decoder 2 correspond to priority circuit A in FIG. 1, 8-bit latch circuit 3 corresponds to latch circuit B, NAND gate circuits 4, 5, and 10 correspond to control circuit E, and 6 corresponds to a status circuit C, and a counter 8 and a D-type flip-flop 9 correspond to a timing circuit D, respectively.

*IR1 to *IR8 are interrupt request lines and negative logic signal input lines.

*IACK1 to *IACK8 are negative logic interrupt enable signal output lines for interrupt factors.

*INTR is a negative logic interrupt request output line through which this circuit requests an interrupt to an external processor.

Also, the output terminals _{1Y1 to 1Y4 of the three-state buffer 6,
2Y1 to 2Y4} are data outputs.

Note that a clock is constantly supplied to this circuit.

When there is no interrupt request, *IR1 to *IR8 are all set to "H", therefore, terminals 2, 4, 6, 8, 10, _{and 12} of the inverter 12 output and the inverter 13 output
Terminals _{10 and 12} become “L”, and NAND gate circuit 4
The 3rd, _{6th, 8th, and 11th} terminals of 5 and 5 become "H", and the _8th terminal of the NAND gate circuit 10 output becomes "L".

As a result, the counter 8 is cleared, and the -output of the D-type flip-flop 9 becomes "H".

Therefore, *INTR is "H".

If, for example, an interrupt factor occurs in *IR5 in this state, *IR5 becomes "L".

As a result, the output of encoder 1 is as follows. The _A2 terminal on the output side of encoder 1 is “L”, _{A0, A1,}
The _E0 terminal becomes "H".

Since the STB terminal of the 8-bit latch circuit 3 is "H", its _D04 terminal is "H", _{the 3rd} terminal of the NAND gate circuit 5 is "L", and therefore the _8th terminal of the NAND gate circuit 10 is "H". '', the counter 8 generates a carry signal at the terminal 15 after counting the clock, and the output of the D-type flip-flop 9 becomes "L", closing the NAND gate circuit 7 and stopping the clock. Therefore, the 8-bit latch circuit 3
The STB terminal becomes "L", the interrupt request signal is also held, and *INTR is also held at "L".

At this time, if an interrupt with a lower priority than *INTR occurs, it will be ignored before coder 1,
If a high priority interrupt occurs, it is ignored before the 8-bit latch circuit 3.

This state continues as long as *INTR is valid, *INTA returns from the microcomputer MPU side, *IACK5 becomes "L", and when *IR5 becomes invalid, _{the 3rd} terminal of NAND gate circuit 5 becomes "H"
Therefore, the No. ₈ terminal of the NAND gate circuit 10 is “L”
The counter 8 is cleared, and the output of the D-type flip-flop 9 becomes "H". As a result, the interrupt request that has been ignored until now appears at the output of the 8-bit latch circuit 3, and at the same time *INTR becomes "H". Become.

Next, the No. ₈ terminal of the NAND gate circuit 10 is “H”
After the counter 8 counts the clock 16 times, a ripple carry occurs, the output of the D-type flip-flop 9 becomes "L", and the interrupt request becomes 8.
It is held in the bit latch circuit 3 and via the NAND gate circuit 14, *INTR becomes "L" and requests an interrupt to the interrupt controller.

The interrupt request signal once held in this manner continues to be held even if a higher priority interrupt occurs until that signal becomes invalid.

FIG. 3 shows an example of application of FIG.

In the figure, 20 and 21 are inverters, 22 is an encoder, 23 is a decoder, 24 and 25 are inverters, 26 is an 8-bit latch circuit, 27, 28, 2
9 is an AND gate circuit, 30 is a bus arbiter, 31 is a resistor, 32 is an inverter, 33, 34
are NAND gate circuits, and 35 and 36 are inverters, respectively.

The example shown in FIG. 3 is also a circuit that operates almost the same as that in FIG. 2, and BREQ1 to BREQ8 are bus request lines,
BACK1-8 are bus acknowledge lines. In this case, when a bus request is input, "H" is output from the 8-bit latch circuit 26 via the encoder 22 and decoder 23, the EN terminal becomes "L", the data is held, and the bus request is canceled. It will continue to be output until

In that case, even if a low-priority bus request or a high-priority bus request is input, it will not be output to the output side, so the device that outputs the bus request first will not receive a bus acknowledgment unless it cancels the bus request itself. Since the output is continuous, malfunctions due to the influence of other bus requests will not occur.

〔Effect of the invention〕

As described above in detail, the present invention has the great effect of preventing malfunctions during interrupt operations and bus acquisition operations.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram of a data priority latch circuit according to the present invention. FIG. 2 is a detailed circuit diagram of one embodiment of a data priority latch circuit according to the present invention. Third
The figure shows an example of application of figure 2. In the figure, A is a priority circuit, B is a latch circuit, and C
is the status circuit, D is the timing circuit, E is the control circuit, 1 is the encoder, 2 is the decoder, 3 is 8
Bit latch circuit, 4 and 5 are NAND gate circuits, 6 is a three-state buffer, 7 is a NAND gate circuit, 8 is a counter, 9 is a D-type flip-flop, 10 is a NAND gate circuit, 11 is a resistor circuit, 12 and 13 are inverters, 14 is a NAND gate circuit, 15 and 16 are OR gate circuits, 2
0, 21 are inverters, 22 are encoders, 23
is a decoder, 24 and 25 are inverters, and 26 is 8
Bit latch circuits, 27, 28 and 29 are AND gate circuits, 30 is a bus arbiter, 31 is a resistor, 32 is an inverter, 33 and 34 are NAND gate circuits, and 35 and 36 are inverters, respectively.

Claims (1)

[Scope of Claims] 1. A priority circuit A that determines the priority of input data, a latch circuit B that latches the output from the priority circuit A, and a system for notifying an external device of the latched contents of the latch circuit B. a status circuit C; a control circuit E that outputs a control signal when the input data and the latch output of the latch circuit B are present; and a control circuit E that outputs a control signal when the input data and the latch output of the latch circuit B are present; It is characterized by comprising a timing circuit D which outputs a continuation signal to continue the state, and a timing circuit D which outputs a reset signal to release the latched state of the latch circuit B when the input data is withdrawn and the control signal disappears. data priority latch circuit.