JPH0452972B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to microcomputers, and particularly proposes a novel interrupt control circuit thereof.

[Background of the invention]

There is a technique for selectively using two registers specified by the same code by applying a switching signal. Since both registers are designated by the same code and can be used differently by a switching signal, one is called the foreground register and the other is called the background register because they can be seen as two sides of a paper.

It is conceivable that the foreground register is normally used for both of these registers, and that when a special command is given, the switching signal is generated to specify the background register. If an interrupt caused by an internal or external source of the microcomputer occurs while this instruction or BANK instruction is being executed, the next interrupt processing will be performed. In this case, the background register remains specified by the BANK instruction, which may cause problems in subsequent processing.

〔the purpose〕

The present invention has been made to solve this problem, and the present invention waits for the completion of execution of the instruction following the BANK instruction, which instructs writing to, reading from, etc., to the background register. This is what we decided to do.

〔composition〕

In the microcomputer according to the present invention, when an internal or external interrupt occurs during the execution of a first instruction that specifies a background register, the microcomputer interrupts the execution of the first instruction until the execution of the second instruction following the first instruction is completed. It is characterized by having a configuration in which the information is held on hold.

〔Example〕

The present invention will be described in detail below based on drawings showing embodiments thereof. FIG. 1 is a logic diagram of an interrupt execution control signal generating circuit which is a main part of a microcomputer according to the present invention.

Occurs by executing the BANK instruction
A 3-input AND gate whose three inputs are the output of inverter 1 which receives the BANK signal BANK, the interrupt request signal IRQ, and the output of inverter 2 which receives the interrupt execution control signal IEC to be created by this circuit. 3 is applied to a clocked inverter 4 driven by the first clock CL1, and its output is applied to a clocked inverter 5 driven by the second clock CL2, and the output of this clocked inverter 5 is It is designed to be given to a processor section (not shown) as a signal IEC.

FIG. 2 is a time chart for explaining the operation of this circuit.

The rising edge of the clock CL2 defines the starting point of the instruction execution cycle, and the falling edge of the clock CL1 defines the ending point. Assuming that the BANK instruction is executed in cycle T1, as shown in FIG.
Therefore, even if an interrupt request is made in the cycle T1 and the signal IRQ is at a high level, the output signal IEC remains at a low level as shown in FIG. When the cycle T2 is entered, the three inputs of the AND gate 3 become high level, and the output of this gate 3 becomes high level as shown in FIG. Therefore, clock CL1 of cycle T2 and clock CL2 of cycle T3
This appears on the output side of inverter 5, so
As a result, the signal IEC becomes high level in cycle T3.

As a result, the next instruction after the BANK instruction, which means writing, reading, etc. to the background register, is executed in cycle T2, and an interrupt is executed in cycle T3 when the instruction is completed.

〔effect〕

As described above, according to the present invention, instructions that should originally be executed continuously, that is, the BANK instruction that specifies a background register, and instructions for processing related to the specified background register (write instructions, read instructions, etc.) are divided. Since it is executed prior to the loading process, the above-mentioned inconvenience is eliminated and smooth processing is possible.

[Brief explanation of the drawing]

FIG. 1 is a logic diagram of an interrupt execution control signal generating circuit which is a main part of the microcomputer of the present invention, and FIG. 2 is a time chart for explaining its operation. 1, 2...Inverter, 3...AND gate,
4, 5...Clocked inverter.

Claims (1)

[Claims] 1 In a microcomputer that is capable of specifying a background register, prohibiting the passage of an interrupt request signal generated internally or externally based on a signal generated during the execution cycle of the first instruction specifying the background register. a delay circuit that captures the output of the gate means within an instruction execution cycle and outputs it in the next instruction execution cycle;
A microcomputer characterized in that an interrupt that occurs during an instruction execution cycle is suspended until execution of a second instruction that uses the background register following the first instruction is completed.