JPH045315B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a communication path memory in which the communication path memory section in a time division switch is duplicated so that when a failure of the main communication path memory is detected, switching to the sub-communication path memory is possible.

Generally, in a time division switch, the control system and communication line system are configured as a so-called complete duplex system, and when a fault is detected, the operation of the faulty device is stopped and only the other device is operated. Particularly in communication systems that transmit data, the influence of intermittent disturbances such as noise during transmission is large, so full duplexing is used, and when detecting an error, there is a method of switching systems all at once, and a method is used to detect a single error. If you always switch over, the exchange operation will stop every time an error occurs, resulting in a decline in exchange service.
A method is used to switch systems when the same error occurs three times. In such a method,
While this may not be a problem when simply exchanging audio signals, when exchanging digital data,
Erroneous data will be output as is, and the reliability of communication networks including digital data will decrease.

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks and to provide a communication path memory that can quickly respond to the occurrence of an error and enable economical switching of communication paths by partially duplicating the communication path system. .

Embodiments of the present invention shown in the drawings will be described below. FIG. 1 shows only the communication path memory portion of the communication path system, and the communication path system requires various switches, registers, etc. and their driving devices in addition to the memory shown. In the present invention, the communication path memory has a so-called duplex configuration. In FIG. 1, SPM0 is a main channel memory, and SPM1 is a sub channel memory, and channel information from a subscriber is simultaneously written to SPM0 and SPM1. In addition to the above communication path information, a parity bit generated by a parity bit generator PG is inserted into the main channel memory SPM0 and stored in the memory. At this time, the selectors SEL0 and SEL1 are controlled by the output of the counter CNT, and the channel information from the subscriber is stored in the main channel memories SPM0 and SPM1. Next, by the output of the control memory CM, one side directly controls the selector SEL0 to select the main channel memory.
Read SPM0, the other is flip-flop FF0
After the time is adjusted by , the selector SEL1 is controlled. Writing (W) and reading (R) are performed in one time slot cycle. The read signal from the sub channel memory SPM1 is delayed by one time slot compared to the read signal from the main channel memory SPM0 (see FIGS. 2B and 2H). Note that the signals read out from each channel memory during half of these time slots are processed by FF1 and FF4.
The signal is maintained for the time slot time. That is,
The signals are B, C, H, and J in Figure 2. Regarding FIG. 2, a parity check is performed in the parity check circuit PC, and if the parity check is good, the time is adjusted by the flip-flop FF3. On the other hand, information from the subscriber is stored in the subchannel memory SPM1, time-adjusted by the flip-flop FF4, and put on standby by the selector SEL2. The signal after the parity check instructs the selection operation of the selector SEL2 via another flip-flop FF2. Flip-flops FF1, FF3, and FF4 match the time relationships, and a selector SEL2 normally selects the output of the main channel memory as a signal addressed to other subscribers. When the parity check circuit PC detects a parity error (that is, detects an information error failure in the main channel memory), the selector SEL2 is switched by the output of the flip-flop FF2 to output the output of the sub channel memory. FIG. 2 also shows an operating waveform diagram. In FIG. 2, n indicates the same data as N, and n indicates the subchannel memory side. That is, only the data "n" is taken out from the sub-channel memory, and all the data before and after it are taken out from the main channel memory, so that the result shown in FIG. 2J is obtained. FF2 is activated by the signal from the error detection circuit PC, sends out the signal F, and maintains the time for one time slot. During this time, the selector SEL2 switches the signal path and sends the data n shown in FIG. 2 to the signal J. Send as. When the time slot ends, FF2 is reset so that signal F disappears. Therefore, the selector SEL2 completes the signal path switching and returns to its previous state, so that the signal D is sent to the signal J.

A communication path memory such as the one in the present invention usually uses a semiconductor memory, but if noise enters between the memory element and the power supply or between the memory element and the ground, the information in the memory may be destroyed. This is not a permanent destruction of the components in the memory, but a temporary loss of information storage, which is recovered the next time it is written/read. Such a phenomenon is referred to as a "single error" in this specification.

In this way, according to the present invention, only the channel memory is duplicated, rather than the entire system, so the configuration is inexpensive, and there is no possibility that the main channel memory and the sub channel memory will be erroneous at the same time regarding the read information. In addition, when an error is detected, the information stored in the sub-channel memory, where the same information was stored, is read out and sent out at a different timing, without outputting erroneous information, which improves the reliability of the channel. will improve. That is, the present invention increases reliability by selectively outputting information in the sub channel memory in response to an information error failure in the main channel memory. Therefore, it is possible to deal with a new failure in the main channel memory other than an error at the time of writing to the main channel memory. This is particularly effective in digital data communication because information passing through the communication path is not lost even if a single error occurs only in the main communication path memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is an operation time chart of each signal shown in FIG. SPM0...Main channel memory, SPM1...Sub channel memory, FF0-FF4...Flip-flop, PC...Parity check circuit, CM...Control memory, CNT...Counter, SEL0, SEL1,
SEL2...Selector.

Claims (1)

[Scope of Claims] 1. In a time-sharing electronic exchange that exchanges digitized information, a main channel memory SPM0 stores error detection information from an error detection information generation circuit PG together with the digital information; A sub channel memory SPM1 stores the same digital information as the main channel memory SPM0, and the read information is checked based on the error detection information in the read information read from the main channel memory SPM0. - An error detection circuit PC that sends out a defective signal; a time difference circuit FF0 that causes a time difference between the read information from the main channel memory SPM0 and the read information from the sub channel memory SPM1; Circuits that adjust the relationship FF1, FF3, FF
4, and a selection output circuit SEL2 that selects and outputs the read information from the main channel memory SPM0 and the read information from the sub channel memory SPM1 based on the detection result of the error detection circuit PC, and the error detection circuit PC is the main channel memory
When a defective signal is generated as a result of checking the information read from SPM0, the error detection circuit
The PC is configured to allow the selection output circuit SEL2 to select and output read information from the sub channel memory SPM1 in which the same information is stored, without outputting erroneous read information from the main channel memory SPM0. A communication path memory characterized by: