JPH0454979B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a resistor formed on a semiconductor substrate.

Usually, the resistance R and the sheet resistance R _s are determined by the width W of the resistor, the length L of the resistor, the thickness t of the resistor, and the specific resistance ρ, and are expressed by the following equations.

R=L/W・t・ρ ……(1) R _s =ρ/t ……(2) As can be seen from equations (1) and (2), there are the following three methods for forming high resistance. There is.

The first method is to adjust the width W and length L of the resistor from the design pattern.The width W of the resistor can be reduced to the lower resolution limit of the photoresist process, but the design should be close to the lower limit. This also has the disadvantage that manufacturing variations become large, making it impossible to obtain a resistor with a stable resistance value, and that if the length L of the resistor is increased to form a high resistance, the degree of integration cannot be increased. .

The second method is to increase the resistivity ρ of the resistor. However, the resistance layer normally used in semiconductor devices is used in other parts such as tunnel wiring, general wiring, gate electrodes, etc., and it is desirable to lower the specific resistance as much as possible from the viewpoint of the purpose of these uses. Therefore, in order to increase the specific resistance of the resistor itself, it is necessary to add a new manufacturing process and create a resistance layer for the resistor. However, the addition of manufacturing process steps increases costs, increases the likelihood of defects, and reduces yield.

As a third method, a high resistance element can also be formed by reducing the thickness t of the resistor, but like the second method, it is necessary to create a particularly thin resistance layer, so the second method is It has the same drawbacks. In the third method, the resistor layer is also etched when forming holes in the interlayer insulating film formed above the resistor layer for electrode extraction. For this reason, there is a limit to how thin the resistive layer can be made, and this method has not been used in the past.

Next, increase the length L of the resistor to create a high resistance element.
A conventional method for manufacturing a semiconductor device manufactured together with a MISFET will be described with reference to the drawings.

FIGS. 1a to 1e are cross-sectional views showing the manufacturing process of a conventional semiconductor device including a resistor and a MISFET.

As shown in Figure 1a, the well-known N channel
After growing an oxide film 2 for element isolation on a P-type semiconductor substrate 1 as in the case of manufacturing MISFET, a first gate insulating film 3 is formed. Next, after ion implantation of a P-type impurity such as boron for threshold control into the element forming region, a first polysilicon layer 4 is grown, a photoresist 5 is deposited, and patterning is performed.

Next, the first polysilicon layer is etched to form a resistor 41 and a first gate electrode 42. Then, N-type impurities are ion-implanted to form source/drain regions 6, and a second gate insulating film 7 is grown. Furthermore, the first and second gate insulating films of the buried contact portion 8 are removed [FIG. 1b].

Next, a second N-type polysilicon layer 9, which will become a second gate electrode, is formed, and a photoresist 5 is applied and patterned (FIG. 1c).

Next, the second polysilicon layer 9 is etched to form a second gate electrode 91 and an extraction electrode 92, and then an insulating film 10 is grown on top of the second polysilicon layer 9 to form a predetermined opening 11 [FIG. 1d] .

Next, the electrode 12 is formed by depositing and patterning Al, which can be rewritten as a resistor.
A semiconductor device including a ROM (hereinafter referred to as EPROM) is completed [Fig. 1e].

The sheet resistance R _s of the first polysilicon layer 4 formed in FIG _. If R s is increased, a phenomenon occurs in which the withstand voltage of the second gate insulating film 7 formed on the first gate electrode 42 (floating gate) decreases, so it is not preferable to lower the impurity concentration to simply increase R _s .

Furthermore, the method of increasing R _s by reducing the thickness of the first polysilicon layer 4 does not pose any problem for EPROM elements; however, in FIG. When the opening 11 is provided in the resistor 41, a portion of the first polysilicon layer serving as the resistor is also etched, and the resistor 41 may be missing. This phenomenon of etching of the first polysilicon has recently started to occur as devices have become smaller and reactive ion etching equipment capable of anisotropic etching has been used as an etching equipment for openings. Ta. This is due to the low selective etching ratio between the insulating film and polysilicon. As described above, the method of forming a high resistance by thinning the first polysilicon layer has the disadvantage that the polysilicon layer is lost when forming the opening, making it impossible to draw out the electrode.

For the above reasons, the conventional method of forming high resistance has been to increase the ratio of the length L to the width W of the resistor, but this method has the drawbacks of low integration and large variations in resistance value. Ta.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device having a resistor in which the above-mentioned drawbacks are eliminated, a thin resistor is formed without increasing the number of manufacturing steps, and the resistor layer is thickened only in the electrode extension portion of the resistor. It is in.

The method for manufacturing a semiconductor device of the present invention includes the steps of forming an oxide film on a semiconductor substrate and then forming a first polysilicon layer, and patterning the first polysilicon layer to form a first electrode of an MIS transistor and a resistor. a step of forming a second polysilicon layer on the entire surface after forming an oxide film on the first electrode; and a step of patterning the second polysilicon layer and forming a second polysilicon layer on the entire surface of the first electrode. A second electrode of the MIS transistor is formed on the oxide film on the electrode of
The method also includes the steps of forming a conductive layer on both ends of the resistor layer and etching the resistive region of the resistor layer so as to obtain a desired resistance value.

Next, embodiments of the present invention will be described in detail using the drawings.

FIGS. 2a to 2e are cross-sectional views of a semiconductor chip in a manufacturing process for explaining the technology related to the present invention. The manufacturing process is almost the same as the MISFET manufacturing process shown in FIGS. 1a to 1e.

First, an oxide film 2 for element isolation is grown on a P-type semiconductor substrate 1, and then a first gate insulating film 3 is formed. Next, after performing ion implantation to control the threshold voltage into the element formation region, a first polysilicon layer 4 having a thickness of 500 to 5000 Å is grown, a photoresist 5 is applied, and patterning is performed (FIG. 2a).

Next, the first polysilicon layer 4 is etched to form a resistor 41 and a first gate electrode 42, and then an N-type impurity is ion-implanted to form a source/drain region 6. Furthermore, after forming the second gate insulating film 7, the first and second gate insulating films in the buried contact portion 8 and the second gate insulating film 7 on the resistor 41 are removed [FIG. 2b].

Next, a second N-type polysilicon layer 9 having a thickness of 4,000 to 8,000 Å is formed, and a photoresist 5 is applied and patterned (FIG. 2c).

Next, the second polysilicon layer 9 is etched,
A second gate electrode 91, an extraction electrode 92, and resistance extraction electrodes 93 and 93' are formed. Subsequently, after growing an insulating film 10, a photoresist 5 is deposited.
After patterning, apertures 11 are formed (FIG. 2d).

Next, Al is deposited and patterned to form the electrode 12, and a semiconductor device including a resistor and EPROM is completed (FIG. 2e).

The semiconductor device formed in this way has a first
Compared to the conventional semiconductor device shown in Figure e, the resistance lead electrode 9
3,93' is formed extra. However, the resistance lead electrodes 93, 93' are formed by etching the second polysilicon layer 9, and the second gate electrode 9
1 and the extraction electrode 92 at the same time, there is no need to add a special process. Furthermore, even if the first polysilicon layer is formed thinly to form the resistor 41 in order to obtain a high resistance element, the resistance lead-out electrodes 93 and 93' are formed in the portion where the opening 11 is formed. There is no risk of the resistor being etched away.

3a and 3b are a plan view and a sectional view taken along line A-A' of a semiconductor chip for explaining one embodiment of the present invention. Note that the insulating film is omitted in FIG. 3a to make the structure clear.

This is the same as the related technology shown in FIG. 2, except that the resistor 41' formed of the first polysilicon layer is formed thinner in the portions where the resistance lead electrodes 93, 93' are not provided. For example, when a resistor with such a structure has to be formed thickly because the first polysilicon layer is used as a low-resistance layer in other parts, the resistor can be formed by forming the first polysilicon layer thickly. After forming the resistor 4, when etching the second polysilicon layer 9 in the manufacturing process shown in FIGS. 2c and d, the etching time is increased.
It can be formed by etching one resistance region to obtain a desired resistance value.
Since the thickness of the first polysilicon layer can be adjusted in this way, the sheet resistance R _s of the resistor can be freely controlled. If a reactive ion etching device is used to etch this polysilicon layer, etching will proceed only in the direction perpendicular to the semiconductor substrate surface. Only the thickness can be adjusted.

As mentioned above, the resistor formed according to this embodiment has a high degree of integration, a good yield, and can be manufactured at low manufacturing cost without adding any special process to the conventional manufacturing process. . In addition, disconnection defects that occur in thin polysilicon resistor electrode parts are no longer caused, and it is possible to manufacture highly reliable semiconductor devices. In the above example, N
Although the description has been made regarding a channel EPROM, it is also applicable to N-channel and P-channel complementary semiconductor devices having two or more layers of conductors.

As explained in detail above, according to the present invention,
This is highly effective because a method for manufacturing a semiconductor device having a resistor with a high resistance value and an improved degree of integration can be obtained without adding any manufacturing steps.

[Brief explanation of the drawing]

Figure 1 a-e includes conventional EPROM
A cross-sectional view of a semiconductor chip in the manufacturing process of MISFET, FIGS. 2a to 2e are cross-sectional views of a semiconductor chip in the manufacturing process for explaining related technology of the present invention, and FIGS. 3a and b are one embodiment of the present invention. FIG. 2 is a plan view and a cross-sectional view of a semiconductor chip for explaining. 1... P-type semiconductor substrate, 2... Oxide film, 3...
First gate insulating film, 4... First polysilicon layer, 5... Photoresist, 6... Source/drain region, 7... Second gate insulating film, 8... Buried contact portion, 9... Third 2 polysilicon layers, 10
... Insulating film, 11 ... Opening part, 12 ... Electrode, 4
1, 41'...Resistor, 42...First gate electrode,
91... second gate electrode, 92... extraction electrode,
93, 93'...Resistance extraction electrode.

Claims (1)

[Claims] 1. A step of forming a first polysilicon layer after forming an oxide film on a semiconductor substrate, and a step of patterning the first polysilicon layer to simultaneously form a first electrode of an MIS transistor and a resistor layer. forming a second polysilicon layer on the entire surface after forming an oxide film on the first electrode; and patterning the second polysilicon layer to form an oxide film on the first electrode. MIS transistor second
forming an electrode, forming a conductive layer on both ends of the resistor layer, and etching the resistor region of the resistor layer so as to obtain a desired resistance value. manufacturing method.