JPH0455026B2 - - Google Patents

Description

Detailed Description of the Invention (Technical Field) The present invention relates to a semiconductor imaging device that projects an image onto its surface by optical means and converts an optical signal into an electrical signal to obtain a video signal, and relates to a semiconductor imaging device that uses an electrostatic induction transistor and The present invention relates to a semiconductor imaging device using field effect transistors, and more specifically, to a semiconductor imaging device with improved signal separation between pixels.

(Prior Art) A photoelectric cell of a conventional semiconductor imaging device is composed of a photodiode for photodetection and a MOS transistor for switching.

Therefore, the photoelectric conversion sensitivity is low because photodetection is performed using a photodiode.

To solve this problem, an electrostatic induction transistor (or field effect transistor) with high photoelectric conversion sensitivity is used for photodetection, and optical carriers are accumulated in the gate region, and the voltage between the source and drain is adjusted according to the potential of this gate region. A semiconductor imaging device has been proposed that can control the current and extract a high output signal, and the basic device is disclosed in Japanese Patent Laid-Open No. 15229/1983.

FIG. 1a shows an embodiment of the imaging device, and is a diagram showing a cross section of one pixel cell portion and a circuit necessary for operation.

In reality, photoelectric cells constituting each pixel are arranged in a matrix on a flat substrate.

Each photovoltaic cell has an N ^- epitaxial layer 2 formed on an N ⁺ Si substrate (source) 1, and an N ^-
P ⁺ layer gate region 3 and N ⁺ drain region 4 in layer 2
is formed, and a drain electrode 5 is formed on the drain.

Further, a gate electrode 7 is formed in at least a portion of the gate region with an insulating film 6 interposed therebetween. Further, a drain electrode 10 is provided at the bottom of the substrate 1. Here, the impurity concentration of the N ^- layer 2 is selected to be sufficiently low so that even if the P ⁺ layer gate region 3 is at zero bias (or reverse bias) with respect to the source, the channel is pinched off, a potential barrier is created, and the drain The potential barrier is also controlled by voltage.
FIG. 1b is a modification of a, and is an embodiment in which the substrate 1 is used as a drain.

That is, a static induction transistor is formed. The value of the capacitor formed in the gate portion via the insulating film 6 is selected so that the signal charge can sufficiently control the current between the source and drain with respect to the capacitance between the gate and source.

Next, the basic operation of a semiconductor imaging device formed from a large number of photoelectric cells will be explained based on the configuration shown in FIG. 1a.

FIG. 2 is an equivalent circuit diagram of a two-dimensional semiconductor imaging device formed from a large number of photoelectric cells (pixel cells).

Each column line is connected to a circuit 28 for applying column line selection pulses φG1 to m, and is connected to the gate portions of pixel cells in each column via additional capacitors.

Each row line is connected to the drain electrode of each row, and one is connected to a load resistor which is an output circuit through switching transistors φS ₁ to φSn provided for each row.
Connected to RL and power supply VD.

In addition, the gates (or bases) of the switching transistors in each row are connected to the row line selection pulses φS1 to n.
It is connected to a circuit 29 for application.

Therefore, the signal of any pixel cell can be read by applying a pulse to one column line and one row line.

When serial video output is desired, for example, a pulse φG for selecting a column line is applied to a certain column, and each pixel cell of a certain column line, which has been charged in advance, is discharged in accordance with the optical signal. Next, by sequentially applying a row line selection pulse φS to each row, each pixel cell is charged, and a video output can be obtained from the output terminal.

Conversely, by applying the row line selection pulse φS to a certain row line, and during the application period sequentially applying the column line selection pulse φG to each column, video output can be obtained from the output terminal. can.

In such a cell structure, since the N ^- layer 2 has a low impurity concentration, a depletion layer is formed between each gate region 3, and signals are mixed between adjacent cells through this depletion layer, resulting in a decrease in resolution. There was also a problem that blooming was likely to occur.

To solve this problem, it is necessary to separate each pixel cell.

FIG. 3 is a partial cross-sectional view of an imaging device having a separation structure, which is considered to solve the above problem. This structure has an N ⁺ region between each gate region from the surface to the substrate.

However, this structure requires that the N ⁺ region 8 be formed deeply by diffusion, for example, if the thickness of the N ^- layer is
In the case of 10 μm, the width of the isolation region needs to be about 20 μm, which may hinder high integration.

In order to integrate so that the same number of pixels can be obtained, it is necessary to increase the pitch interval or to decrease the area of the light receiving section.

In addition, if an N ⁺ isolation region 8 is provided close to or overlapping the P ⁺ gate region 3 in an attempt to achieve high integration, optical carriers may accumulate due to a decrease in breakdown voltage due to this P ⁺ N ⁺ junction and an increase in reverse leakage current. cannot be carried out effectively.

In addition, the area of the P ⁺ gate region 3 is made as small as possible, and the N ^- layer 2 is placed between the P ⁺ gate 3 and the N ⁺ isolation region 8.
A configuration can be considered in which a depletion layer is present between the P + layer and the photogenerated carriers are concentrated in the P ⁺ layer, thereby improving the withstand voltage and reducing reverse leakage radio waves. However, due to the influence of the N ⁺ accumulation layer induced on the surface of the N ^- layer 2, non-uniform photosensitivity may occur, which may lead to an increase in reverse leakage current.

Furthermore, making the P ⁺ region smaller reduces the amount of charge that can be accumulated there, which lowers the saturation exposure amount, which is not necessarily preferable as a pixel for an image sensor.

(Objective of the Invention) An object of the present invention is to reduce blooming by effectively separating signals between pixels, to improve the resolution of the imaging device through high integration, and to manufacture a semiconductor imaging device with high yield. Our goal is to provide the following.

(Description of Structure and Effects of the Invention) In order to achieve the above object, a semiconductor imaging device according to the present invention includes a first semiconductor layer of a first conductivity type with a high concentration, and an intrinsic or first semiconductor layer provided thereon. It consists of a low concentration second semiconductor layer of conductivity type, and third to sixth semiconductor regions provided in the second semiconductor layer, and the third and sixth semiconductor regions are of a high concentration first semiconductor layer. The fourth and fifth semiconductor regions are of the second conductivity type, and optical carriers are mainly accumulated in the fourth semiconductor region, and the potential change causes the first and third semiconductor regions to The pixel cell has a plurality of pixel cells each made of a static induction transistor that controls current between them and obtains an output, and in each pixel cell, the fourth semiconductor region is formed to surround or sandwich the third semiconductor region. , the fifth
The semiconductor region has a lower concentration than the fourth semiconductor region and is formed in contact with the fourth semiconductor region, and the sixth semiconductor region is formed in contact with a peripheral portion of the fifth semiconductor region. ing.

With the above configuration, firstly, the portion of the gate region where optical carriers are accumulated, which is close to the region where the channel is formed, is doped with a high impurity concentration, for example, 10 ¹⁸ cm ^-3
A gate region is formed in contact with the periphery of the high concentration region with a low impurity concentration, for example, 10 ¹⁷ cm ⁻³ or less.

In contact with the low impurity concentration part of each gate,
Provide an N ⁺ isolation region so as to form a P ⁺ P ^- N ⁺ structure junction.

This makes it possible to prevent deterioration in breakdown voltage caused by conventional P ⁺ N ⁺ junction isolation in the gate and isolation region, and also to reduce reverse current.

The impurity concentration in the low concentration gate part is high enough to prevent the P type from inverting to the N type, and the impurity concentration is high enough to prevent the P type from inverting to the N type.
The withstand voltage of the P ^- N ⁺ junction must be selected to be low enough so that there are no operational problems. This includes 5 x less than 10 ¹⁷ cm ^-3
There is no problem if it is in the range of 10 ¹⁵ cm ^-3 or more.

The P layer thus formed serves as the surface of the light-receiving portion and prevents N ⁺ accumulation or formation of an N-type inversion layer on the surface. This reduces the surface recombination current and avoids the concentration of electric fields, which increases photosensitivity, especially the photoelectric conversion efficiency and uniformity of short wavelength light absorbed near the surface, and improves the breakdown voltage and reverse direction. At the same time, a reduction in leakage current can be expected. Furthermore, since the gate region and the N ⁺ isolation region are provided in contact with each other (overlapping each other), high integration is achieved, and the structure allows for the largest P region within a given area, increasing the amount of charge that can be stored. , an image sensor with a large saturation exposure amount can be obtained.

Furthermore, in order to effectively isolate each pixel by the N ⁺ isolation region, the N ⁺ isolation region is formed deeper than the depth of each gate low concentration region provided in contact with (overlapping with) the N ⁺ isolation region. N ⁺ just below the separation area
It is necessary to suppress as much as possible the mixing of signal charges between gate regions through the N ^- region.

On the other hand, for high integration, it is important that the width of the N ⁺ isolation region be as narrow as possible. For this purpose
Even if the depth of the N ⁺ isolation region is shallow, it is necessary that each P layer gate be sufficiently isolated. To achieve this, by making the depth of the P layer in the low concentration region as shallow as possible and by making a large difference in the depth of the N ⁺ isolation region, the depletion layer between the gates can be effectively reduced to N ⁺
Cut by a separation layer. With this structure, the PIN junction of the light receiving section formed by the P-type gate and the substrate becomes shallower, and further improvement in photoelectric conversion sensitivity on the short wavelength side can be expected.

(Description of Examples) Hereinafter, the present invention will be described in more detail with reference to the drawings and the like.

FIG. 4 is a diagram showing a partial cross-sectional structure of an embodiment of a semiconductor imaging device according to the present invention.

In Figure 4, N ⁺ silicon layer (source) 1
An N − layer 12 having a channel region 13 is formed on top of the N ⁻ layer 12 .

Gate regions 14A (high concentration impurity region; P ⁺ ), 14B (low concentration impurity concentration; P ⁻ ) and N ⁺ drain region 15 are formed in the N ^- layer 12, and a drain electrode 16 is formed on the drain 15. is formed.

An insulating film 18 and a gate electrode 19 are formed in at least a portion of the gate region 14A.

Further, an N ⁺ isolation region 17, extraction electrodes 21 and 22, and a source electrode 25 are provided in contact with 14B.

Here, the impurity concentration of the N ⁺ source 11, P ⁺ gate 14A, and N ⁺ drain 15 is selected to be approximately 1 × 10 ¹⁸ cm ^-3 or more, and the impurity concentration of the N ^- layer 12 is approximately 1 × 10 ¹⁵ cm ^-3 or less. The thickness should be approximately 5 to 15 μm. The gate interval is set so that even if the gate voltage is 0 bias with respect to the source potential, the channel is pinched off, that is, no drain current flows.

Furthermore, the peripheral gate portion, which is a feature of the present invention, is approximately 5
It is formed to have an impurity concentration of ×10 ¹⁵ to 1 × 10 ¹⁷ cm ^-3 and a depth of about 0.5 to 1.0 μm. As for shallow junctions, it is easy to form them by ion implantation. On the other hand, the depth of the P ⁺ region is 2~
It is appropriate to choose a thickness of about 3 μm. It is preferable that the N ⁺ isolation region has an impurity concentration of about 1×10 ¹⁶ cm ^-3 or more and a depth and width as large as possible, but generally a depth of 3 μm or more and a width of 8 μm or more are suitable.

To be more precise, considering operating conditions etc.
Avoid coupling each gate region through the N ^- layer.

An example of the manufacturing process of an imaging device having the above structure is shown in the fifth example.
This will be explained with reference to the figures.

On a low-resistance N ⁺ substrate 11, a high-resistance N ^- layer 12 of 50 Ωcm or more is formed to a thickness of 5 to 10 μm by silicon epitaxial growth. Approximately 5000
A field oxide film (SiO ₂ ) of 1.5 nm is deposited by thermal oxidation.

Example of drilling SiO ₂ holes in N ⁺ isolation region 17, depositing N-type impurities such as phosphorus
do.

Heat treatment is performed in an oxidizing atmosphere to form an oxide film on the phosphorus-attached surface and to a depth of approximately 2 μm at a selected time.

After the oxide film is formed, the P ⁺ gate region 14A is
Drill ₂ holes in SiO and use P, for example, boron.
Attaches mold impurities.

Heating in a high temperature oxidizing atmosphere, P ⁺ area 14A
The depth should be about 2 to 3 μm. At this time, the N ⁺ isolation region 17 has a thickness of about 3 to 4 μm.

A hole is made in the oxide film and an N ⁺ drain region 15 is formed by diffusion.

Diffusion conditions are selected so that the depth of the N ⁺ drain region 15 is approximately 0.5 μm.

At the same time, the drain electrode 16 is formed of phosphorus-doped polysilicon or the like.

P ⁺ gate region 14A and N ⁺ isolation region 17
After drilling holes in the oxide film so as to overlap with the oxide film, an insulating film 18 of 1000 to 2000 Å thick oxide film is formed in an oxidizing atmosphere.
form.

Using ion implantation method, acceleration energy 75 ~
Boron ions were implanted at 100keV with an implantation amount of 10 ¹³ to 2×10 ¹⁵ /cm ² in an inert gas atmosphere.
By annealing at 900° C. for 10 minutes, a P ⁻ gate region 14B is formed.

On the oxide film formed in the above step V, etc.
A transparent conductive film 19 such as SnO ₂ is formed.

Holes for taking out the electrodes are made, and aluminum lead-out electrode wirings 21 and 22 are formed.
Furthermore, a source electrode 25 is formed by depositing Au or the like on the back surface of the wafer by vacuum evaporation or the like.

Various modifications can be made to the embodiments described above without departing from the scope of the present invention.

By appropriately selecting the thickness of the N ^- layer 12 and the width of the isolation region 17, the isolation region 17 can be formed simultaneously with the formation of the N ⁺ drain region 15.

In addition, as in the second embodiment shown in FIG ^.
It is also possible to form the layer 12 by digging a trench to a depth of about 1 to 3 μm.

In this case, the depth of the groove can be formed using conventional techniques to a shallow depth that does not affect the mask material or the accuracy of the method.

Furthermore, as in the third embodiment shown in FIG.
For example, the P substrate 24 may be used, and the N ⁺ source portion 23 may be buried therein, and this N ⁺ isolation region may also be used as an output terminal portion of the source.

Therefore, the present invention is not limited to N ⁺ substrates, but can also include circuits for selecting column lines and row lines coexisting with the photoelectric cell matrix section as needed, and integrated and formed on the same substrate. This can be done using integrated circuit technology.

Furthermore, as shown in FIG. 1B as a conventional example, it is also possible to configure a pixel cell by reversing the source and drain.

The content of the embodiments of the present invention can be applied even if the conductivity types are all reversed, and it is not limited to silicon.
Needless to say, it can also be applied to GaAs and other semiconductors.

(Description of Effects) As described above, according to the present invention, blooming is reduced by effectively separating signals between pixels, the resolution of an imaging device is improved by high integration, and the yield is improved. A well-manufactured imaging device is obtained.

[Brief explanation of the drawing]

FIGS. 1a and 1b are a sectional view of a conventional semiconductor imaging device using an electrostatic induction transistor or a field effect transistor, and a circuit diagram necessary for its operation, respectively. FIG. 2 is an equivalent circuit diagram of the semiconductor imaging device. FIG. 3 is a cross-sectional view of a device showing a possible device structure for improving isolation of the device shown in FIG. FIG. 4 is a diagram showing a partial cross-sectional structure of the first embodiment of the semiconductor imaging device according to the present invention. FIG. 5 is a process diagram for explaining the manufacturing process of the device. FIG. 6 is a diagram showing a partial cross-sectional structure of a second embodiment of the semiconductor imaging device according to the present invention. FIG. 7 is a diagram showing a partial cross-sectional structure of a third embodiment of the semiconductor imaging device according to the present invention. 11... N ⁺ silicon layer (source), 12... N ^- layer having a channel region, 13... channel region,
14A...gate region (high concentration impurity region; P ⁺ ),
14B...gate region (low concentration impurity region; P ^- ),
15...N ⁺ drain region, 16... drain electrode,
17...N ⁺ isolation region, 18... Insulating film, 19... Transparent gate electrode, 21, 22... Extraction electrode, 25...
source electrode.

Claims (1)

[Claims] 1. A highly doped first semiconductor layer of a first conductivity type, a lightly doped second semiconductor layer of an intrinsic or first conductivity type provided thereon, and a second semiconductor layer. It consists of third to sixth semiconductor regions provided in the layer, the third and sixth semiconductor regions are of a highly doped first conductivity type, and the fourth and fifth semiconductor regions are of a second conductivity type. The pixel cell is composed of an electrostatic induction transistor that mainly accumulates optical carriers in the fourth semiconductor region and controls the current between the first and third semiconductor regions by changing the potential of the fourth semiconductor region to obtain an output. In each pixel cell, the fourth semiconductor region is formed to surround or sandwich the third semiconductor region, and the fifth semiconductor region has a lower concentration than the fourth semiconductor region. and the sixth semiconductor region is formed in contact with a peripheral portion of the fifth semiconductor region. 2 The impurity concentration of the fourth semiconductor region is 10 ¹⁸ /
cm ³ or more, the impurity concentration of the fifth semiconductor region is
10. The semiconductor imaging device according to claim 1, which has a particle size of 10 ¹⁷ /cm ³ or less. 3. The semiconductor imaging device according to claim 1, wherein the depth of the fifth semiconductor region is shallower than the depth of the sixth semiconductor region.