JPH0455325B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for obtaining a good connection between polycrystalline silicon and an electrode made of Al or an Al alloy.

[Technical background of the invention]

In semiconductor devices, polycrystalline silicon is used as an electrode lead or as a resistor.
Or connected to a low resistance electrode made of Al alloy. Such a semiconductor device will be explained using a bipolar type semiconductor device shown in FIG. 3 as an example.

In Fig. 3, the surface of P-type silicon substrate 1 is
An N ⁺ type buried layer 2 is formed, and an N type epitaxial layer 3 is further formed thereon, and this N type epitaxial layer 3 is separated by a P ⁺ type element isolation region 4 . An N + type collector extraction region 5 and a P type base region 6 are selectively formed in the N type epitaxial layer 3, reaching from the surface thereof to the ^{N +} type buried layer 2, and furthermore, an N type base region 6 is formed in the base region 6. A mold emitter region 7 is formed. A P-type diffused resistor 8 is formed in the adjacent N-type epitaxial layer 3, which is formed simultaneously with the base region 6. Further, on the entire surface, for example, a thermal oxide film 9 and, for example,
A BSG film 10 is formed, and is connected to a polycrystalline silicon pattern 11 for taking out the emitter region 7 and the collector take-out region 5 through contact holes made in the thermal oxide film 9 and the BSG film 10, and is connected to the adjacent diffusion A polycrystalline silicon pattern 12 extending above the resistor 8 is formed. Furthermore, a CVD oxide film 13 is formed on the entire surface.
An emitter electrode 14 connected to the polycrystalline silicon pattern 11 through a contact hole opened in the CVD oxide film 13 and an insulating film thereunder, a base electrode 15 connected to the base region 6, and the polycrystalline silicon A wiring 16 connected to the pattern 12 and the adjacent diffused resistor 8 is formed.

The polycrystalline silicon pattern 11 is used for taking out the electrode and also as an emitter diffusion source, and is further connected to the emitter electrode 14. Further, the polycrystalline silicon pattern 12 is used as a resistor or wiring, and the polycrystalline silicon pattern 12, the diffused resistor 8, and the electrode 16 are connected at one location at the position indicated by X in the figure.

As the wiring metal such as the emitter electrode 14, an alloy material containing Si, such as Al-Si or Al-Si-Cu, is used. The reason why a metal containing Si is used as a wiring metal is that in the thermal process (sintering process) performed to obtain good ohmic contact between Al and the substrate silicon or polycrystalline silicon, Si dissolved in
This is to reduce the amount of polycrystalline silicon and prevent the disappearance of polycrystalline silicon patterns caused by penetration (spikes) of Al into the silicon substrate and diffusion of polycrystalline silicon into Al.

[Problems with background technology]

Conventionally, the Si content in Al has been selected in the range of 1 to 2%, and the sintering temperature (usually 400 to 500
This is a sufficiently high level of solid solubility compared to the solid solubility limit of 0.8% in Al at ℃). However, the solid solubility limit changes depending on the temperature until the sintering temperature is reached, so at low wafer temperatures at the beginning of sintering,
Si precipitation occurs in Al, forming Al crystal grains with a low Si concentration. After that, when the temperature is raised to the sintering temperature, Si diffuses and the polycrystalline silicon layer disappears and the substrate
This results in the phenomenon of Al encroachment into Si. In particular, when substrate silicon, Al, and polycrystalline silicon exist together, as in the area indicated by
Si may be dissolved in Al and further diffused in Al to cause Si precipitation on the silicon substrate surface, resulting in extremely large loss of polycrystalline silicon.

It has been found that this disappearance of polycrystalline silicon largely depends on the grain size of the polycrystalline silicon. For example, doped polycrystalline silicon formed by mixing impurities such as phosphorus or arsenic into gas by LPCVD method etc. is used as polycrystalline silicon, and undoped polycrystalline silicon which is not doped with impurities is ion implanted in a post-process. When compared with doped polycrystalline silicon (hereinafter referred to as ion-implanted polycrystalline silicon), the above-described disappearance phenomenon of polycrystalline silicon is less likely to occur in doped polycrystalline silicon. This difference is due to the fact that the grain size of ion-implanted polycrystalline silicon is about 0.1 to 0.5 μm, whereas the grain size of doped polycrystalline silicon is larger, 1 to 3 μm or more. That is, the fourth
Before sintering as shown in Figures a and b (Figure 4 a)
When polycrystalline silicon 21 and Al 22 are brought into contact with each other, after sintering (FIG. 4b), silicon diffuses from the grain boundaries of polycrystalline silicon 21 into Al wiring 22, forming cavities 23 at the grain boundaries. arise. Therefore, as shown in FIGS. 5a and 5b, the contact area before sintering (FIG. 5a) is different from the contact area after sintering (FIG. 5a).
When the Al wiring 22 is removed as shown in FIG. b), the polycrystalline silicon 21 has disappeared. It is clear that such a phenomenon is more likely to occur in ion-implanted polycrystalline silicon, which has large grain boundaries. Furthermore, when comparing polycrystalline silicon and single-crystal silicon, the fact that single-crystal silicon undergoes less loss can be explained by the above-mentioned difference in grain boundaries.

From the above, polycrystalline silicon and Al
It can be seen that control of the grain boundaries of polycrystalline silicon is important in order to prevent the disappearance of polycrystalline silicon and obtain good contact when the two are brought into contact with each other.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and is aimed at manufacturing a semiconductor device that can prevent the disappearance of polycrystalline silicon due to the diffusion of silicon into the wiring metal, which occurs between the wiring metal and the polycrystalline silicon. It is intended to provide a method.

[Summary of the invention]

The method for manufacturing a semiconductor device of the present invention involves implanting silicon ions into the surface of polycrystalline silicon at a contact portion between polycrystalline silicon and Al or Al alloy to make the surface of polycrystalline silicon amorphous and removing excess silicon. This is characterized by forming an electrode of Al or an Al alloy after the presence of the aluminum.

According to this method, grain boundaries are almost eliminated by making the polycrystalline silicon amorphous, and since there is an excess amount of ion-implanted silicon, it is possible to suppress the diffusion of silicon atoms in the polycrystalline silicon into the wiring metal. This can prevent polycrystalline silicon from disappearing.

[Embodiments of the invention]

Hereinafter, embodiments of the method of the present invention will be described with reference to FIGS. 1a to 1d.

First, an N ⁺ type buried region 22 is formed on the surface of a P type silicon substrate 21, and then an N type epitaxial layer 23 is formed on the entire surface. Next, boron is selectively diffused into a part of the epitaxial layer 23 to form a P ⁺ type element isolation region 24, and the epitaxial layer 23 is
Separate. Subsequently, phosphorus is selectively diffused into a portion of the epitaxial layer 23 to form an N ⁺ -type collector extraction region 25 that reaches the N ⁺ -type buried layer 22 . Next, a thermal oxide film 26 is applied to the entire surface.
After forming, a part of it is selectively etched. Subsequently, after depositing a BSG film 27 on the entire surface,
A heat treatment is performed to diffuse boron to form a P-type base region 28 and a P-type diffused resistor 29 (first
(Figure a shown).

Next, a part of the BSG film 27 on the base region 28 and a part of the thermal oxide film 26 and BSG film 27 on the N ⁺ type collector extraction region 25 are selectively etched to form a contact hole. Continuing,
After depositing an As-doped polycrystalline silicon film over the entire surface, it is patterned to form a polycrystalline silicon pattern 30 that serves as a diffusion source for the emitter region and also serves as an emitter extraction electrode, and the collector extraction region 25.
A polycrystalline silicon pattern 31 is connected to the diffusion resistor 29 and extends over the diffused resistor 29. Next, thermal diffusion is performed to form polycrystalline silicon pattern 3.
As shown in FIG. 1B, an N ⁺ type emitter region 32 is formed by diffusing As.

Next, after depositing a CVD oxide film 33 on the entire surface,
A part of the CVD oxide film 33, a part of the BSG film 27, and a part of the thermal oxide film 26 are selectively etched to expose a part of the polycrystalline silicon pattern 30, the base region 28, the polycrystalline silicon pattern 31, and the diffused resistor 29. Drill a contact hole so that the Subsequently, Si ⁺ ions are implanted under conditions of, for example, an acceleration energy of 50 keV and a dose of 2×10 ¹⁵ cm ⁻² . By this ion implantation, the exposed surfaces of the polycrystalline silicon and the substrate silicon are made amorphous, and an excess of the ion-implanted silicon atoms is caused to exist (as shown in the figure c).

Next, Al-Si (1
%), patterning is performed to form an emitter electrode 34 connected to the polycrystalline silicon pattern 30, a base electrode 35 connected to the base region 28, and a diffused resistor 29 adjacent to the polycrystalline silicon pattern 31. A connected wiring 36 is formed. Thereafter, heat treatment is performed at 450° C. for 30 minutes to obtain ohmic contact at the contact portion (as shown in figure d).

According to such a method, the polycrystalline silicon pattern 3 with exposed contact portion is
By ion-implanting Si ⁺ into the single crystal silicon (base region 28 and diffused resistor 29) surfaces of 0, 31 and the substrate, these surfaces are made amorphous, so grain boundaries are eliminated and Si atoms become Al- Diffusion into the wiring metal made of Si can be suppressed, and moreover, the diffused Si atoms can be compensated for by excess Si atoms that are ion-implanted. Also, as in the above example
If the acceleration energy of Si ⁺ ion implantation is 50 keV, the amorphous layer will have a thickness of 700㎓, and a uniform alloy layer with the wiring metal can be obtained, so localized Al spikes etc. Abnormal diffusion can be prevented.

In fact, the frequency of loss of polycrystalline silicon at the contact area (indicated by X in Figure 1 d and Figure 3), where the wiring metal, polycrystalline silicon, and single crystal silicon of the substrate are connected at one point, can be compared to Al wiring. From FIG. 2, which evaluates the contact conduction yield between silicon and polycrystalline silicon, it can be seen that the loss of polycrystalline silicon is significantly reduced in the method of the present invention. In other words, in the conventional method without silicon ion implantation (comparative example), the contact conduction yield after the sintering process at 450°C and 500°C is approximately
On the other hand, in the method of the present invention (example), almost no contact conduction failure occurred even after the sintering process at 450°C and 500°C. However, after going through the sintering process at 500°C, some contact conduction failure occurs, but this is because the solid solubility limit of Si in Al at 450°C is 0.6%, whereas the solid solubility limit at 500°C is 0.6%.
It is 0.8%, which is thought to be due to the large amount of Si atoms diffused from polycrystalline silicon into Al.

In addition, in the method of the present invention, the Si ⁺ ion implantation conditions must be at least 1× because the surface of polycrystalline silicon or single crystal silicon must be made amorphous.
A dose of 10 ¹⁵ cm ^-2 or more is required.

Furthermore, in the above embodiment, silicon ion implantation was performed only in the contact area after patterning polycrystalline silicon, but after depositing polycrystalline silicon, silicon ion implantation was performed on the entire surface, and then patterning was performed. Good too. Even such a method does not affect the effects of the present invention in any way. Furthermore, in the above embodiment, silicon ions were implanted not only into the polycrystalline silicon contact part but also into the single crystal silicon contact part of the substrate, but if silicon ions were implanted only into the polycrystalline silicon contact part, the Disappearance of crystalline silicon can be prevented, and it is not necessarily necessary to implant silicon ions into the substrate silicon.

〔Effect of the invention〕

As detailed above, according to the method of the present invention, the phenomenon of polycrystalline silicon disappearing is suppressed in the contact area between the wiring metal made of Al or Al alloy and polycrystalline silicon, and a semiconductor device with good conduction characteristics can be manufactured. It is something that can be done.

[Brief explanation of the drawing]

1A to 1D are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a relationship between sintering temperature and contact conduction yield in contact portions manufactured by a conventional method and a method of the present invention. FIG. 3 is a cross-sectional view of a semiconductor device manufactured by a conventional method, FIG. 4 a and b are cross-sectional views showing the state of grain boundaries of polycrystalline silicon before and after sintering, and FIG. 5 a and b are plan views showing the state of polycrystalline silicon before and after sintering, respectively. 21... P type silicon substrate, 22... N ⁺ type buried layer, 23... N type epitaxial layer, 24...
...P ⁺ type element isolation region, 25...N ⁺ type collector extraction region, 26...thermal oxide film, 27...BSG film,
28...P-type base region, 29...P-type diffused resistance, 30, 31...polycrystalline silicon pattern, 3
2...N ⁺ type emitter region, 33...CVD oxide film, 34...emitter electrode, 35...base electrode, 36...wiring.

Claims (1)

[Claims] 1. When manufacturing a semiconductor device having polycrystalline silicon formed on a semiconductor substrate and electrodes made of Al or Al alloy that are in ohmic contact with the polycrystalline silicon, polycrystalline silicon and
Silicon is ion-implanted into the polycrystalline silicon surface at the contact area with Al or Al alloy to make the surface of the polycrystalline silicon amorphous and to make excess silicon exist, and then an electrode of Al or Al alloy is formed. A method for manufacturing a semiconductor device, characterized in that: