JPH0455546B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for forming a tunnel-type Josephson junction used in a superconducting integrated circuit.

(Prior Art) In a method for forming a Josephson junction of the type in which a Josephson junction region is defined by etching a junction constituting layer in which a lower electrode and an upper electrode are coupled via a tunnel barrier layer, It is necessary to bury the periphery of the junction using a post-insulating film and expose the junction surface. As a method for embedding the bond and exposing the bond surface, there is an etch-back method, which is conventionally known as a planarization technique. Figure 5 a~
Figure 3e shows a method for forming Josephson junctions using the etchback method. The conventional technology will be explained below using FIG.

A lower wiring 12 is formed on the base 11, and a first insulating film 13 is used to flatten the buried surface. After sputter cleaning is performed to clean the surface of the lower wiring 12, a bonding layer consisting of a lower electrode 14, a tunnel barrier layer 15, and an upper electrode 16 is formed thereon (FIG. 5a). The junction component layers are selectively etched using an etch mask to define Josephson junction regions (FIG. 5b). After forming the second insulating film 17 to a thickness greater than the step difference caused by the etching, the surface is made flat using a coating film 18 (FIG. 5c). The second insulating film 17 and the coating film 18 are etched at the same etching rate to expose the surface of the upper electrode 16 of Josephson junction (FIG. 5d). Perform spatter cleaning and remove the upper electrode 16.
After cleaning the surface, upper wiring 19 is formed (FIG. 5e).

(Problems to be Solved by the Invention) In the embedding of the junction by the etchback method described in the prior art, electrical continuity is established between the upper electrode 16 of the junction and the upper wiring 19 as shown in FIG. 5d. Therefore, the surface of the upper electrode 16 must be exposed from the second insulating film 17. In the actual etchback process, variations in the etching step shown in FIG. 5B on the substrate, variations in the etching rate on the substrate,
Due to the difference in etching rate between the etching film 18 and the coating film 18, and the accuracy of detecting the end point of etching, a certain margin of etching depth is required in order to reliably expose the surface of the upper electrode 16 over the entire surface of the substrate. be.

On the other hand, the inductance of a superconducting integrated circuit is approximately proportional to the thickness of the interlayer insulating film. Therefore, controlling the thickness of the interlayer insulating film becomes an important issue in the manufacturing process. In particular, the thickness of the insulating film used to embed the Josephson junction is approximately proportional to the inductance of the quantum interferometer, which is one of the gates that make up the superconducting integrated circuit, and has a direct impact on the characteristics and operating margin of the quantum interferometer. Therefore, it is necessary to control it particularly precisely.

In forming Josephson junctions using the conventional etch-back method, since a margin for etching depth is required as described above, it has been difficult to control the thickness of the second insulating film 17 that embeds the junctions.
For this reason, the inductance of the superconducting integrated circuit cannot be controlled to a designed value, resulting in a reduction in operating margins.

It is an object of the present invention to overcome the above-mentioned drawbacks of the prior art and to provide a method for forming a Josephson junction with good controllability of the thickness of the interlayer insulating film, that is, the inductance.

(Means for Solving the Problems) By using the present invention, in a method for forming a tunnel-type Josephson junction, a lower electrode and an upper electrode made of a superconducting film are connected to each other through a tunnel barrier layer. A step of etching to define a bonding area, a step of forming an insulating film with a thickness less than the step difference caused by the etching, a step of flattening the surface using a coating film, and a step of forming the insulating film and the coating film. A method for forming a Josephson junction, comprising the steps of: etching at approximately equal etching rate to expose the surface of the bonding region and leaving a part of the coating film; and removing the coating film; A method for forming a tunnel-type Josephson junction includes a step of etching a bonding layer in which a lower electrode and an upper electrode made of a superconducting film are bonded via a tunnel barrier layer to define a bonding region, and a step caused by the etching. a step of forming an insulating film with the following thickness; a step of flattening the surface using a coating film; and a step of etching the insulating film and the coating film at approximately the same etching rate to expose the surface of the bonding region. and etching the upper electrode in the bonding region at a higher etching rate than the coating film to align the upper electrode surface and the insulating film surface, and leaving a part of the coating film. There is obtained a method for forming a Josephson junction characterized by comprising a step of leaving the coating film and a step of removing the coating film.

(Function) In the present invention, the junction is buried using an insulating film having a thickness equal to or less than the step difference caused by the etching of the junction constituting layer. Therefore, using the etchback method described in the conventional example, the insulating film and the coating film are etched at the same etching rate, and when the upper electrode surface of the junction is exposed, the insulating film other than the junction is covered with the coating film. There is. Even if some overetching is performed to ensure exposure of the upper electrode of the junction, the insulating film will not be etched while the coating remains. By removing this coating film, the thickness of the interlayer insulating film contributing to inductance becomes equal to the thickness of the formed insulating film. In this way, if the present invention is used, the difference between the step difference caused by etching the bonding constituent layer and the thickness of the insulating film becomes the etching margin, and the exposure of the upper electrode surface of the bond changes the thickness of the interlayer insulating film. You can definitely do it without any trouble.

Further, if the second aspect of the present invention is used, the thickness of the interlayer insulating film can be changed by etching the joint portion protruding onto the insulating film using the etchback according to the present invention at a higher etching rate than the coating film. The surface can be made flatter without

(Example) (Example 1) Figures 1a to 1f show the steps for forming a Josephson junction according to the first invention. Below, the first
An embodiment of the first invention will be explained using the drawings.

A lower wiring 12 is formed on a thermally oxidized silicon substrate 11 using niobium Nb with a thickness of 200 nm. Silicon dioxide SiO ₂ with a thickness of 200 nm is formed as the first insulating film 13, and the lower wiring 12 is buried therein. A 200 nm film of niobium is formed thereon as a lower electrode 14 by sputtering. After forming a 10 nm aluminum film by sputtering, thermal oxidation was performed at an oxygen pressure of 40 Pa for 10 minutes to form a tunnel barrier layer 15 made of aluminum oxide film.
form. Finally, niobium is used as the upper electrode 16.
A film of 200 nm is formed by sputtering to form a junction constituent layer consisting of a lower electrode 14, a tunnel barrier layer 15, and an upper electrode 16 (FIG. 1a). Note that the formation of the bonding constituent layers described above is performed in the same vacuum. Next, an etching mask is formed using a positive photoresist AZ1350J (trade name). The bonding layer is processed by reactive ion etching using carbon tetrafluoride gas to define the bonding area (FIG. 1b). Reactive ion etching was performed using a parallel plate type etching device, and the etching conditions were carbon tetrafluoride gas pressure of 5.0 Pa, flow rate of 30 sccm, and power density of 0.16 W/cm ² . Note that when aluminum is etched by reactive ion etching using carbon tetrafluoride gas, the etching rate is extremely low, so only the aluminum part is etched.
Etching is performed by ion milling using 2.0 Pa argon gas. As the second insulating film 17, silicon dioxide is deposited to a thickness of 300 nm by sputtering. A photoresist AZ1450J (trade name) is applied thereon as a coating film 18 using a spinner at a rotation speed of 6000 rpm. Then bake at 180℃ for 60 minutes.
Reflow the photoresist to make the surface flat. (Figure 1c). FIG. 3 shows the relationship between the carbon tetrafluoride gas pressure and the etching rate of silicon dioxide, AZ1450J, and niobium in reactive ion etching using carbon tetrafluoride gas. The electrodes are Teflon, and the carbon tetrafluoride flow rate is
30SCCM, power density is 0.16W/ ^cm2 . From Figure 3, when the carbon tetrafluoride gas pressure is 7Pa, the etching rate of silicon dioxide and AZ1450J is 30nm/
It turns out that it is equal to minutes. When etching is performed under this carbon tetrafluoride gas pressure of 7 Pa, the etching rate of silicon dioxide and AZ1450J are the same, so etching can be performed while keeping the surface flat. Etchback is performed under these conditions to expose the surface of the upper electrode 16 for bonding. Furthermore, over-etching is performed for 2 minutes to ensure that the surface of the upper electrode 16 is exposed over the entire surface of the substrate. 2
In the etching for 1 minute, the coating film 18 is etched by only 60 nm, so the second insulating film 17 other than the junction portion is still covered with the coating film 18 of about 50 nm (FIG. 1d). By soaking the substrate in an organic solvent (e.g. acetone) and cleaning it ultrasonically.
Remove AZ1450J (Figure 1e). After performing sputter cleaning using argon gas to remove niobium oxide and contaminants on the upper electrode 16 of the junction, a 300 nm niobium film is formed by sputtering without breaking the vacuum. Thereafter, patterning is performed using a photoresist, and reactive ion etching is performed under the same etching conditions as those for the lower electrode 14 and the upper electrode 16 to form the upper wiring 19 (FIG. 1f).

In this embodiment, as shown in FIG. 1c,
The thickness of the second insulating film 17 is greater than the step difference caused by etching to define the bonding area.
100nm thin. Therefore, in the etchback process shown in FIG. The insulating film 17 of No. 2 is a coating film 18
covered in. By removing this coating film 18 as shown in FIG. 1e, the thickness of the second insulating film 17 is maintained at the same thickness as when it was formed. From the above, the 100 nm step difference between the upper junction electrode 16 and the second insulating film 17 becomes the etching margin, and while the thickness of the second insulating film is kept at the deposited 300 nm,
The surface of the upper electrode 16 for bonding can be sufficiently exposed. Therefore, by using this embodiment, the controllability of the thickness of the second insulating film 17, that is, the thickness of the interlayer insulating film mentioned in the problem of the conventional example, is improved, and therefore the inductance of the superconducting integrated circuit can be controlled. Improves sex. Furthermore, since there is a sufficient etching margin (100 nm) for exposing the surface of the upper electrode 16 of the junction, the manufacturing process is facilitated and the yield is improved.

(Example 2) FIG. 2 shows a process for forming a Josephson junction according to the second invention. Hereinafter, an embodiment of the second invention will be explained using FIG.

A lower wiring 12 is formed using niobium with a thickness of 200 nm on a thermally oxidized silicon substrate 11. thickness
A 200 nm thick silicon dioxide film is formed as the first insulating film 13, and the lower wiring 12 is buried therein. A 200 nm film of niobium is formed thereon as a lower electrode 14 by sputtering. After forming a 10nm aluminum film by sputtering,
A tunnel barrier layer 15 is formed by thermal oxidation at an oxygen pressure of 40 Pa for 10 minutes. Finally, a 200 nm film of niobium is formed as the upper electrode 16 by sputtering, and the lower electrode 1
4. Form a junction constituent layer consisting of a tunnel barrier layer 15 and an upper electrode 16 (FIG. 2a). Note that the formation of the bonding constituent layers described above is performed in the same vacuum.
Next, an etching mask is formed using a positive photoresist AZ1350J (trade name). The bonding layer is processed by reactive ion etching using carbon tetrafluoride gas to define the bonding region (FIG. 2b).
Reactive ion etching was performed using a parallel plate etching device, and the etching conditions were carbon tetrafluoride gas pressure of 5.0 Pa, flow rate of 30 sccm, and power density.
It is 0.16W/ ^cm2 . Note that since the etching rate of aluminum is extremely low when reactive ion etching is performed using carbon tetrafluoride gas, only the aluminum portion is etched by ion milling using argon gas. As the second insulating film 17, silicon dioxide is deposited to a thickness of 300 nm by sputtering. On top of that, photoresist AZ1450J is applied as coating film 18.
is applied using a spinner at a rotation speed of 6000 rpm. Then, bake at 180℃ for 60 minutes.
The photoresist is reflowed to make the surface flat (Figure 2c). FIG. 3 shows the relationship between the carbon tetrafluoride gas pressure and the etching rate of silicon dioxide, AZ1450J, and niobium in reactive ion etching using carbon tetrafluoride gas. The electrodes are Teflon, and the carbon tetrafluoride flow rate is
30SCCM, power density is 0.16W/ ^cm2 . From FIG. 3, it can be seen that when the carbon tetrafluoride gas pressure is 7 Pa, the etching rate of silicon dioxide and AZ1450J is equal to 30 nm/min. When etching is performed under this carbon tetrafluoride gas pressure of 7 Pa, the etching rate of silicon dioxide and AZ1450J are the same, so etching can be performed while keeping the surface flat.
Etchback is performed under these conditions to expose the surface of the upper electrode 16 for bonding. Further, over-etching is performed for 2 minutes to ensure that the surface of the upper electrode 16 is exposed over the entire surface of the substrate. In the etching for 2 minutes, the coating film 18 is etched by only 60 nm, so the second insulating film 17 other than the junction portion is still covered with the coating film 18 of about 50 nm (FIG. 2d).

Replace the etching electrode with quartz and use carbon tetrafluoride
1 under the conditions of 50SCCM, 20Pa, power density 0.16W/ ^cm2
Perform reactive ion etching for 30 seconds. FIG. 4 shows the relationship between the carbon tetrafluoride gas pressure and the etching rate of silicon dioxide, AZ1450J, and niobium in reactive ion etching using carbon tetrafluoride gas. The electrodes are quartz, the carbon tetrafluoride flow rate is 30 SCCM, and the power density is 0.16 W/ ^cm2 . As shown in Fig. 4, this etching etches 80 nm of niobium, forming the upper electrode 1 of the junction.
6 surface and the second insulating film 17 surface have the same height. (In reactive ion etching under the above conditions, etching for 1 minute is required in addition to the etching time determined from the etching rate in FIG. 4 in order to remove the thin oxide on the niobium surface). By etching for 1 minute and 30 seconds,
Since the coating film 18 to be etched has a thickness of 30 nm,
Even after etching, the second insulating film 17 other than the bonding area remains
It is covered with a coating film 18 of about 20 nm (Fig. 2e). Soak the substrate in an organic solvent (e.g. acetone),
The coating film 18 is removed by ultrasonic cleaning. After sputter cleaning with argon gas to remove niobium oxide and contaminants on the upper electrode of the junction, 300 nm of niobium was added without breaking the vacuum.
Deposit the film using sputtering. Thereafter, patterning is performed using a photoresist, and reactive ion etching is performed under the same etching conditions as the lower electrode 14 and upper electrode 16 to form the upper wiring 19 (second
Figure f).

In this example, in addition to the effect described in the first example, by performing the etching shown in FIG. This has the effect of making the insulating film thinner, reducing inductance, and lowering the step height, making the process easier.

(Effects of the Invention) By using the first aspect of the present invention, the controllability of the film thickness of the interlayer insulating film that embeds the Josephson junction is improved, and the controllability of the inductance of the superconducting integrated circuit is improved. Furthermore, the upper electrode of the bonding can be exposed reliably using the etch-back method. Furthermore, since a large etching time margin can be secured in the etchback, the process is easier and the yield is improved.

Moreover, if the second invention of the present invention is used, in addition to the effects described in the first invention, the flatness of the surface will be improved,
The superconducting and insulating films deposited above the Josephson junction can be made thinner, reducing inductance and increasing the operating speed of superconducting integrated circuits.
Furthermore, it has the advantage that the process becomes easier because the number of steps and cuts caused by the step difference are reduced.

[Brief explanation of drawings]

1A to 1F are process diagrams for explaining an embodiment (Example 1) of the first invention. FIGS. 2a to 2f are process diagrams for explaining an embodiment (Example 2) of the second invention. Figure 3 shows reactive ion etching using a Teflon substrate.
Carbon tetrafluoride gas pressure, niobium, silicon dioxide,
FIG. 3 is a characteristic diagram showing the relationship with the etching rate of photoresist (AZ1450J). FIG. 4 is a characteristic diagram showing the relationship between carbon tetrafluoride gas pressure and etching rate of niobium, silicon dioxide, and photoresist (AZ1450J) in reactive ion etching using a quartz substrate. 5A to 5E are process diagrams for explaining a conventional example. In the figure, 11... substrate, 12... lower electrode, 13... first insulating film, 14... lower electrode,
15... Tunnel barrier layer, 16... Upper electrode, 1
7... Second insulating film, 18... Coating film, 19...
Upper wiring.

Claims (1)

[Claims] 1. In a method for forming a tunnel-type Josephson junction, a step of defining a junction region by etching a junction constituent layer in which a lower electrode and an upper electrode made of a superconducting film are joined via a tunnel barrier layer. a step of forming an insulating film with a thickness equal to or less than the step difference caused by the etching; a step of flattening the surface using a coating film; etching the insulating film and the coating film at approximately the same etching rate; A method for forming a Josephson junction, comprising the steps of: exposing the surface of a bonding region and leaving a part of the coating film; and removing the coating film. 2. In the method for forming a tunnel-type Josephson junction, a step of defining a junction region by etching a junction constituent layer in which a lower electrode and an upper electrode made of a superconducting film are joined via a tunnel barrier layer;
A step of forming an insulating film with a thickness equal to or less than the step difference caused by the etching, a step of flattening the surface using a coating film, and etching the insulating film and the coating film at approximately the same etching rate to form the bonding region. etching the upper electrode in the bonding region at a higher etching rate than the coating film to align the upper electrode surface and the insulating film surface; A method for forming a Josephson junction, comprising the steps of leaving a part of the coating film and removing the coating film.