JPH0456313B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a pattern writing control circuit used in a display device having a multicolor graphic display function.

[Invention, technical background and problems]

Conventionally, writing to video RAM in a CRT display device with a graphic display function required read->modification->write control. That is, when turning on or off a dot at a certain coordinate, calculate the memory address where the dot exists, read the contents of that address (byte or word unit), and turn on or off the bit corresponding to the above coordinate. After performing bit modification to turn off,
The bit-modified data must be written in byte or word units to the same address as when it was read.

In this way, in the past, reading, modifying, and writing controls were required for writing display data to video RAM, which resulted in complicated control and a heavy burden on software.
Moreover, the writing process requires a lot of time, which is a major hindrance to improving the performance of this type of display system. In particular, in a so-called color graphic display device with a multi-color display function, it is necessary to provide video RAM for multiple screens (for example, 4 planes in the case of 16-color display), and the above-mentioned byte readout is performed separately for each plane. , bit modification, byte writing, etc., the various problems mentioned above have become more prominent. Furthermore, conventionally, in the above-mentioned color graphic display device, if the graphics memory has a four-plane structure with one screen (plane) and 16KB (kilobytes), the CPU
The address space for the above memory access seen from the side requires 16 KB x 4 = 64 KB, and a lot of time is wasted in calculating the address of each plane.

As described above, in conventional color graphic display devices, a large amount of time is consumed in pattern writing processing, which is a major hindrance to improving system performance.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a pattern write control circuit that can speed up the process of writing patterns to a video RAM for color graphics.

[Summary of the invention]

The present invention uses a writing mechanism of a video RAM for color graphics, in which a plurality of video RAMs are simultaneously selected and specified in dye memory units, that is, plane units, and arbitrary patterns are written in each at the same time. , it is possible to write patterns for each color screen into the video RAM at high speed.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention. In the figure, 10 is a processing unit (hereinafter referred to as CPU) that controls the entire system, 20 is a CRT display circuit consisting of a video RAM for color graphics using dynamic memory in a CRT display device, a control section thereof, etc. A CPU bus 30 is used for transferring addresses (AD), data (DATA), control signals (CTL), etc. between the CPU 10 and the CRT display circuit 20. 21 to 26 are
This is a functional circuit section forming an internal component of the CRT display circuit 20. Here, 21 is a video RAM for color graphics (hereinafter referred to as V-RAM) composed of a dynamic type memory, and here, as an example, it has a 4-plane structure and is capable of displaying 16 colors. Take it. Each V-RAM divided into four planes is herein referred to as a V-RAM plane.
Each V-RAM plane stores display dot data for a unique one-color screen, with each display dot being one bit.Here, the display screen is 640 dots x 200 lines, and the data to be handled is Since the bit width is 8 bits, the total memory capacity is 16 KB (kilobytes), which is divided into eight 16 KB memory blocks.
It is composed of M ₀ , M ₁ , ...M ₇ . 22 is CRT
CRT display control unit (hereinafter referred to as CRT display control unit) that controls synchronization of the display unit
(referred to as CRT-C). 23 is CRT-C22
Memory address (MA) and CPU1 generated by
Processor address (PA) sent from 0
, select one of them, and select V-
This is an address selector (ADR-SEL) that outputs as RAM address data (VRAD). 24
is a timing gate control unit (TIMG) that performs timing control for V-RAM access.
-CTL), a bit mask section for enabling bit modification on the V-RAM 21, and a color screen selection for selecting and specifying any one or more color screens (V-RAM planes) at the same time. The details will be described later. 25
26 is a data buffer unit (DATA-BUF) with a quadruple configuration that stores read/write data of the V-RAM 21 simultaneously for each plane;
This shift register section (SHIFT-REG) also has a quadruple configuration and outputs data read from the RAM 21 as a bit serial video signal VID.

FIG. 2 is a block diagram showing in detail the structure of the timing gate control section 24 shown in FIG. 1. As shown in FIG. In the figure, 201 is a V-
This is a wait control unit (WAIT-CTL) that controls the timing of RAM access, and receives the memory request signal MRQ sent from the CPU 10, and
The wait signal WAIT is sent to the CPU 10 at a timing synchronized with CLK until the V-RAM access is completed. 202 is a timing generator (TIM-GEN) that generates various control signals for V-RAM access, receives the memory write request signal MWR sent from the CPU 10, and also outputs the character clock CH-CLK and address. It outputs various control signals such as select signal SEL, column address select signal CAS, row address select signal, and write enable signal WE. 203
is a decoder (DEC) that receives and decodes the port address (PORT-ADR) sent from the CPU 10, and S-BMR is the decoder 20
The bit mask register strobe signal S-PSR obtained from 3 is a plane select register strobe signal. Reference numeral 204 denotes a bit mask section for specifying and applying the write operation of each plane of the V-RAM 21 only to arbitrary bits, thereby making it possible to modify the bits on the V-RAM 21. 205
is a color screen selection section for simultaneously selecting and specifying an arbitrary number of V-RAM planes for each color screen of the V-RAM 21; here, the column address select signal CAS is selectively supplied to the four V-RAM planes. By doing so, the configuration is configured to selectively control access permission/prohibition for any one to four designated planes.

FIG. 3 is a block diagram showing in detail the configuration of the V-RAM peripheral section in FIG. 2. In FIG. V-
As described above, the RAM 21 is composed of V-RAM planes 21A, 21B, 21C, and 21D, each of which is 16 KB and corresponds to four types of color screens. Here, V-RAM plane 21A,
21B, 21C are R (Red), G (Green), B
(Blue) dot pattern information for each screen is stored separately, and the V-RAM plane 21D stores the brightness information (full gradation/half gradation) of each display dot and displays a total of 16 color dot patterns. Let's take an example where it is possible. Each V-RAM plane 21
V-RAM address data (VARD) output from the address selector 23 is commonly given to A, 21B, 21C, and 21D, respectively, and they are accessed simultaneously by the same address. Therefore, the address space for V-RAM access handled here is 16 KB, and its address width is 14 bits (7 bits x 2). or,
V-RAM plane 21A, 21B, 21C, 2
Corresponding to 1D, the data buffer section 25, shift register section 26, and data bus (LOCAL-BUS) between the V-RAM and data buffer sections are each quadrupled; 25A, 25B, 25
C, 25D are V-RAM planes 21A, 21
Plane data buffers corresponding to B, 21C, 21D, 26A, 26B, 26C, 26D are also V-RAM planes 21A, 21B, 21C,
This is a plane shift register corresponding to 21D. 301, 302, . . . are constituent elements of the bit mask section 204, and 301 is
Bit mask data sent from CPU10
Bit mask register (BIT−) that receives BMD
MASK-REG), 302, 302,...
is a gate that outputs each bit output of the bit mask register 301 at a timing according to the write enable signal WE. Each gate 302, 30
2. Write enable signal output from...
WE ₀ , ₁ ,... ₇ is each V of V-RAM21
-RAM plane 21A, 21B, 21C, 21
Commonly given to D. Each of 401, 402, . 402, 402, . . . are each bit output PS ₀ , PS ₁ , PS ₂ ,
PS ₃ are received separately and the column address select signal CAS is commonly received, and when the corresponding bit output of the plane select register 401 is "1", the column address select signals _A , _B , _C , _D for the corresponding plane are received.
This is a gate that outputs . This gate 402,4
The outputs of 02, ... are the corresponding V-RAMs.
It is supplied to planes 21A, 21B, 21C, and 21D.

FIG. 4 is a circuit block diagram specifically showing the configuration of the V-RAM 21. Here, each V-RAM
The planes 21A, 21B, 21C, and 21D each have 8 memory blocks _M0 to 16K bits.
It is composed of _M7 , _M10 to _M17 , _M20 to _M27, and _M30 to _M37 . Therefore, each V-RAM plane 21
A, 21B, 21C, and 21D each have a 16KB configuration, and the entire V-RAM 21 has a 64KB configuration. V-RAM address data (VARD) is connected to each V-RAM address line via address lines VRA ₀ to VRA ₆ .
RAM plane 21A, 21B, 21C, 21D
Commonly given to 7 bits on the upper side and 7 bits on the lower side.
By transferring the address twice with the bit, each V-
RAM plane 21A, 21B, 21C, 21D
All addresses are commonly addressed. Further, the row address select signal is commonly given to each V-RAM plane 21A, 21B, 21C, 21D, and the column address select signal _A , _B , _C , outputted from the color screen selection section 205.
CAS _D has its corresponding V-RAM plane 2
1A, 21B, 21C, and 21D separately. The write enable signals ₀ , ₁ , ... ₇ output from the bit mask section 204 are
-RAM plane 21A, 21B, 21C, 21
It is commonly given to D with a corresponding bit position (corresponding memory block).

FIG. 5 shows a V-RAM in an embodiment of the present invention.
This conceptually shows the write access control mechanism, in which each V-RAM plane 21 for each color screen receives a common address and enables simultaneous access control.
A, 21B, 21C, 21D are bit mask parts 2
04 bit selection function and color screen selection section 205
This figure shows how write access is simultaneously and selectively controlled by the plane selection function of .

The operation of one embodiment will now be described with reference to FIGS. 1 to 5. V-RAM of CRT display circuit 20
21 is accessed by CPUU0 and CRT-C
22. during normal times
At the timing to refresh the CRT screen, the address select signal SEL generated by the timing generator 202 of the timing gate control section 24 selects and specifies the memory address (MA) of the CRT-C 22, and therefore this memory address (MA) is address selector 2
3 and is commonly given to each V-RAM plane 21A, 21B, 21C, and 21D of the V-RAM 21 as V-RAM address data (VRAD). At this time, the four types of display dot data for each color screen read from the V-RAM 21 are loaded into the corresponding plane shift registers 21A, 21B, 21C, and 21D of the shift register section 26, and then shifted out. Each is sent to the CRT display unit as a bit serial video signal VID. On the other hand, V-RAM from CPU10
An access request is made by applying a memory request signal MRQ to the wait control section 201 of the timing gate control section 24. At this time, the processor address PA is supplied as a memory address to the V-RAM 21, and furthermore, the write data is transferred to the data buffer section 2.
5 each plane data buffer 25A, 25B,
25C and 25D, or read data is sent to the CPU via the data buffer section 25.
Operations such as being guided to the bus 30 are accompanied. These operations are performed based on signals output from the timing gate control section 24. The wait control section 201 of the timing gate control section 24 controls V-RAM for the CPU 10.
Wait signal until memory access of 21 is completed
Send WEIT. Also, the dimming generator 202 of the timing gate control section 24
When the CPU 10 is ready to access the V-RAM, it outputs an address select signal SEL for selecting and specifying a processor address (PA) to the address selector 23. Further, the timing gate control section 24 controls V-
Row address select signal, column address select signal CAS for controlling RAM21,
Outputs write enable signal WE, etc. Among these signals, the row address select signal is commonly given to each V-RAM plane 21A, 21B, 21C, 21D of the V-RAM 21 as it is, and the column address select signal CAS is
After passing through the color screen selection section 205, the column address select signals _A , _B, corresponding to the V-RAM planes 21A, 21B, 21C, and 21D are
Each V-RAM2 of V-RAM21 as _C , _D
1A, 21B, 21C, and 21D individually. In addition, the write enable signal WE is
A memory write request MWR is generated from V-
When the CPU accesses RAM21, V
- It is outputted at the timing required by the RAM 21 and supplied to the bit mask section 204. Bit mask register 301 of bit mask section 204
is defined as one address register from the perspective of the CPU 10, and can be set to any value.
In response to the bit mask register strobe signal S-BMR output from the register 3, the 8-bit bit mask data BMD is latched. The write enable signal WE mentioned above is sent to the bit mask register 301.
is commonly supplied to each output gate 302, 302, . 21A, 21B, 21C, 2
Bit position on 1D, ie memory block (Mi)
Outputs the write enable signal only to By doing this, each V-RAM 21
-RAM plane 21A, 21B, 21C, 21
Writing to D can be performed only to desired bits. For example, if a request is made to turn on only bit 3 of a certain address of the V-RAM planes 21A, 21B selected by the color screen selection unit 205, which will be described in detail later, the binary value "00001000" is stored in the bit mask register 301. ”, then all “1” (data “FF” _HEX ) to that address
This can be achieved by simply writing . Also, if a request to turn off only bit 3 of that address occurs,
This can be achieved by simply writing all “0” (data “00” _HEX ). Also, a plurality of bits of the bit mask register 301 are turned on, and the color screen selection unit 205 selects, for example, the V-RAM planes 21A, 21B, 21C,
is selected, the V-RAM planes 21A, 21 corresponding to the turned-on bits are selected.
Each bit value of B and 21C is to be rewritten.
Also, if byte access (or word access) is required, the bit mask register 30
This is achieved by setting all bits of 1. By means of such a bit mask,
Bits to be modified can be specified arbitrarily.

Next, the operation of the color screen selection section 205 will be explained. The color screen selection section 205, like the bit mask section 204 described above, uses the V-RAM from the CPU 10.
10 CPUs as needed for write access
It operates upon receiving the data PSD sent from the data PSD, and makes write access possible only to the V-RAM plane specified by the data PSD. That is,
The plane select register 401 of the color screen selection unit 205 receives the plane select register strobe signal S-PSR output from the decoder 203 in accordance with the port address (PORT-ADR) from the CPU 10, and receives the plane select register strobe signal S-PSR sent from the CPU 10.
Latch the bit plane select data PSD. Each bit output PS ₀ , PS ₁ , PS ₂ , PS ₃ of this plane select register 205 is supplied to one input terminal of the corresponding output gate 402 , 402 , . . . The above-mentioned column address select signal CAS is commonly applied to the input terminals. Therefore, when the color screen selection section 205 receives the plate selection data PSD and then receives the column address selection signal CAS, the color screen selection section 205 selects the output gate 4 according to the contents of the data PSD set in the plane selection register 205.
From only 02, 402, ..., column address select signal _A specific to the corresponding plane,
Output CAS _B , _C , _D. For example, in order to select V-RAM planes 21A, 21B, and 21C in the plane select register 205, only bit output PS ₃ is set to "0" and other bit outputs PS 0 are set to "_0" .
~ After the plane select data (PSD; Q ₀ to Q ₃ = “1110”) that sets PS ₂ to “1” is set, when the column address select signal (CAS = “1”) is generated, the plane select Column address select signals _A , _B , and _C at a valid level, that is, a "0" level, are output only from the gate 402 that receives the "1" output from the register 205. Output gates 402 and 40 of this color screen selection section 205
The column address select signals _A , _B , and _C output from 2, ... are each set to the corresponding V
- Supplied to RAM planes 21A, 21B, 21C, V-RAM planes 21A, 21B, 21
Each plane 21 except 21D among C and 21D
A, 21B, and 21C can be accessed for writing at the same time.

As described above, each V-RAM plane 21
For A, 21B, 21C, and 21D, write bits are specified by the bit mask section 204, a color screen (plane) is selected by the color screen selection section 205, and the write bits are respectively written for the specified bit positions of the selected plane. At the same time, a dot pattern is written.

Here, the V-RAM 21 uses the functions of the bit mask section 204 and the color screen selection section 205.
An example of pattern writing to .

First, when clearing the screen according to a software request, the CPU 10 writes all "0" to the entire screen area of the V-RAM 21. At this time, the bit mask register 301 of the bit mask section 204
The bit mask data (BMD; 11111111”) of all “1” is set as described above, and the plane select register 40 of the color screen selection unit 205 is set.
Similarly, plane select data (PSD; "1111") of all "1" is set to "1". Also, plain data buffers 25A, 25B, 25C, 2
Write data of all "0" is stored in each 5D. As a result, each output gate 302, 302, . . . of the bit mask section 204 outputs write enable signals ₀ , ₁ , _. Output. or,
Each output gate 402, 40 of the color screen selection section 205
2, ... is the column address select signal
According to CAS, column address select signals _A , _B , _C , and _D are output with all outputs being "0" to enable writing to all four planes.
By specifying the write bit in the bit mask section 204 and selecting the write plane in the color screen selection section 205, each V-RAM plane 21A, 21
By writing to all addresses B, 21C, and 21D with a common address for each plane,
Each V-RAM plane 21A, 21B, 21C,
21D is simultaneously controlled to write "0" in byte units, that is, to clear the screen.

Furthermore, even when filling in a specific color, high-speed writing can be performed by performing screen clearing in substantially the same manner as described above.

In addition, when a dot pattern of a certain color is selectively written at a certain position on the screen according to a software request, the CPU 10 writes the processor address (PA) corresponding to that position and the bit position. The bit mask data BMD having a bit pattern configuration in which the bit position is set to "1" is stored in the bit mask register 30 of the bit mask section 204.
Set to 1. Furthermore, plane select data PSD corresponding to the specified color is set in the plane select register 401 of the color screen selection section 205,
After that, all "1" is written to the above-mentioned corresponding address (PA). This allows a dot pattern of any color to be written only at any position relative to the screen.
Also, if you want to clear the color at a certain position on the screen, set the data in the bit mask register 301 in the same way as above, and set the plane select data PSD of all "1" in the plate select register 401.
to the address corresponding to the specified position.
Just write all “0”.

By controlling pattern writing to the V-RAM 21 as described above, any plurality of color screens, that is, any plurality of V-RAM planes 21A, 21B, 21
Since patterns of arbitrary colors can be controlled to be written to C and 21D at the same time, color patterns can be written at high speed. Also, CPU10 is
Since all the color screens (four planes in the above embodiment) can be handled in a superimposed state, access to the V-RAM 21 can be controlled with the address space largely sandwiched between them.

〔Effect of the invention〕

As detailed above, according to the present invention, the writing mechanism of the video RAM for color graphics is provided with color screen selection means that can simultaneously select and specify a plurality of the video RAMs in color screen units, that is, plane units. By having a configuration in which arbitrary patterns are simultaneously written to multiple planes specified by the screen selection means, the above-mentioned video
Pattern writing processing to RAM can be performed at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a block diagram showing the structure of the timing gate control section in the above embodiment, FIG. 3 is a block diagram showing the structure of the V-RAM peripheral section in the above embodiment, and FIG. 4 is a block diagram showing the structure of the V-RAM peripheral section in the above embodiment.
FIG. 5 is a circuit block diagram showing the configuration of the RAM, and is a diagram conceptually showing the write access control mechanism in the above embodiment. 10... Processing unit (CPU), 20... CRT display circuit, 21... Video RAM (V-RAM), 21
A, 21B, 21C, 21D...V-RAM plane, 22...CRT display control unit (CRT-C),
23...Address selector (ADR-SEL), 24
……Timing gate control section (TIM・
G-CTL), 25...Data buffer section (DATA
-BUF), 26...Shift register section (SHIFT
-REG), 30...CPU bus, 201...Wait control section (WAIT-CTL), 202...
Timing generator (TIM-GEN), 20
3... Port address decoder (DEC), 204
...Bit mask section, 205...Color screen selection section,
301...Bit mask register (BIT/
MASK...REG), 302, 302...402...
...gate, 401...plane select register, MRQ...memory request signal, WAIT...
...Waiting signal, MWR...Memory write request signal,
CH-CLK...Character clock, SEL...Address select signal, CAS...Column address select signal,...Row address select signal, WE...Write enable signal...S-
BMR...Bit mask register strobe signal, S-PSR...Plane select register strobe signal, BMD...Bit mask data,
PSD...plane select data, VID...video signal.

Claims (1)

[Scope of Claims] 1. A plurality of memory planes each storing pigment information and luminance information of a plurality of colors for one screen for multicolor display, the storage locations of which are composed of a plurality of bits, and a column address select signal. and a graphics memory selectively accessed by a row address select signal; means for supplying common address information to address input terminals of each of the memory planes; and means for supplying the row address select signal to a control terminal of each of the memory planes. supplying means; means for supplying write data to a data input terminal of each of the memory planes; a plane selection register in which memory plane selection information is set prior to supplying the common address information and write data; and the address. When information and write data are supplied, access to the memory plane is permitted/disabled through the gate that commonly receives the column address select signal to the control terminal of the memory plane specified by the selection information set in this plane selection register. a circuit for supplying a signal; a bit mask circuit for supplying bit mask information to each of the memory planes for controlling write permission/inhibition of arbitrary bit positions in each of the memory planes; and a memory plane to which access is permitted by the access permission/inhibition signal. means for commonly writing the write data to a storage location designated by the address information and bit mask information, and the address information is written in the memory plane to which access is permitted by the access permission/prohibition signal. and a pattern write control circuit, wherein the write data is commonly written to a storage location specified by bit mask information.