JPH0456345B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a cache memory control method that uses a small-capacity, high-speed cache memory to equivalently realize a large-capacity, high-speed memory. In computer systems that have cache memory in the central processing unit (CPU), when performing a block fetch to the main memory, the requested address immediately after the request that caused a cache miss because there was no data in the cache was conventionally ignored. The address was initially treated as a prefetch target, but subsequent requests were ignored. The present invention makes it possible to process a request immediately after a request that caused a cache error, or a subsequent request as a prefetch target.
This is intended to improve the prefetch function. [Industrial Application Field] The present invention relates to instructions () within a central processing unit.
S in response to an operand access request from the unit.
(Storage) Pertains to a prefetch function for holding a request address following a cache miss request made by a storage unit, and in particular relates to control of the cache memory in the CPU, control of the main memory read port, and prefetch control. [Prior Art] In a computer system, the time required to access a main memory is much longer than the time required to access a cache memory within a central processing unit (CPU). In order to improve the processing power of a computer system, it is necessary to transfer valid data more efficiently into cache memory, which requires less access time, than from main memory. Central processing unit (CPU) and main storage unit (MSU)
A small-capacity, high-speed memory placed between the two is called cache memory. In general, the faster the memory, the more expensive it is, so it is not economical to configure a large-capacity main memory (hereinafter referred to as main memory) entirely with high-speed memory. Therefore, the cache memory method, which uses a small-capacity, high-speed cache memory to equivalently realize a large-capacity, high-speed memory, is an extremely important technology especially for improving the processing speed of large computers. The parts of the instructions and operand data stored in main memory that are to be used for the time being are stored in cache memory. When the CPU executes an instruction, it first gives an address to cache memory. If the address is in cache memory, a cache hit occurs; if not, a cache miss occurs. While the cache is being hit, the CPU only refers to the cache memory, enabling high-speed processing. cashier
In the event of a miss, the CPU suspends instruction execution and swaps the contents of cache memory with the contents of main memory. The constituent unit of each unit of cache memory is called a "block", and one block consists of several words. When exchanging the contents of cache memory and main memory, it is executed in blocks. In addition, in the case of a cache miss, if the CPU executes a write, the contents are written to the cache memory at that point, and the swap method writes the entire block to the main memory when the contents are exchanged. There is a store-through method that writes to both cache memory and main memory. FIG. 1 shows the configuration of a computer system using a cache memory. The CPU 10 is an I (Instruction) unit 10 that controls instructions.
0, E to perform operations on operand data
(Execution) unit 101, and an S (Storage) unit 102 which performs control of cache hits and misses in response to requests from the I unit 100, particularly by controlling reading and writing of the cache memory and main memory. Ru. The CPU 10 via the S unit 102
The MCU 11 is connected to the MCU 11 (Main Storage Control Unit), and the MCU 11 controls the MSU 1 with the main memory according to requests from the unit 102.
2 (Main Storage Unit). An operand request signal (OP) is sent from the I unit 100 to the S unit 102.
REQ) and the fetch address (OP) for the operand request. REQ ADRS) is sent. Also, from the I unit 100 to the S unit 102
command fetch request signal (IF REQ) and address (IF) for instruction fetch requests. REQ
ADRS) is sent. In order to answer that demand,
The S unit 102 examines the internal cache memory for operands or instructions, and if the cache memory contains the contents, that is, if the cache is a cache hit, the OP STV
(Operand Status Valid) signal or IF STV
(Instruction Fetch Status Valid) signal is returned to I-unit 100. At this time, the I unit can read and write from and to the cache memory.
The I-unit 100 retrieves instructions from cache memory. CACHE Receive as DATA. Also,
E unit 101 opens the operand from cache memory. CACHE Receive as DATA.
In case of cache miss, OP for each operand LMD (Operand Line Missing)
Detect) IF for signals and commands LMD
Returns the (Instruction Fetch Line Missing Detect) signal. At this time, there is no requested content in the cache memory, so the S unit 102
MS for 1 The REQ signal is issued to request main memory reference, and at the same time, the MS REQ
Give the ADRS reference address. Also, the identification signal REQ for the request It also sends out an ID signal. Then, the MCU 11 accesses the main memory of the MSU 12. REQ The ID identifies operand block fetches, instruction block fetches, operand prefetches, translation block fetches, etc. MCU11 to S unit 1
02 contains the requested data (MS DATA) is sent, and at the same time the REQ Identification signal RTN equivalent to ID The ID is also sent. DATA The ID is an identification signal for controlling the order of data, etc. In this way, in a system using a cache memory, if there is another operand request immediately after the operand request that caused the cache miss, the S unit 102 performs prefetch processing on the latter request. An explanatory diagram of the conventional address control system related to the above prefetch and its time chart are shown in FIGS. 5 and 6, respectively.
A conventional cache memory control scheme will be described with reference to the figures. In the timing chart in Figure 6, the operand request (OP REQ) is P (Priority), T (Translative address) within the S unit 102,
Processing is performed in four cycles: B (Buffer access) and R (Result). In the R cycle,
If there is data in Buffer (cache memory), the data in cache memory is
Transfer to general-purpose register in CPU. DMR is
This is a Directory Match Register signal that becomes active when there is requested data in the cache, and becomes inactive when there is not. Notify cache miss when DMR is inactive and there is no data in cache
LMD signal becomes active. At the same time, S
Unit 102 is MS A REQ signal is sent to the MCU 11 to request an exchange operation between the contents of the main memory and the contents of the cache memory. If the LMD signal is issued, the corresponding operand request OP REQ
Operand request OP to lookbehind to REQ1, OP
REQ2 is not processed in a pipeline manner, and the processing is interrupted in the B cycle and T cycle, respectively. OP whose processing was interrupted in B cycle
The operand address for the operand request of REQ1 is OP described later. BEAR (B-cycle
It is stored in a register called OP Effective Address Register. PFAR (Pri-Fetch
It is also stored in a register 52 called Address Register. However, the OP whose processing was interrupted in T cycle Operand address for REQ2 operand request is OP Register 52 called PFAR
is not stored in . OP The operand request (OP) that sent LMD and resulted in a cache miss The request address for (REQ) is used as a reference address to main memory.
The data is transferred to the MCU 11 and block fetch processing is performed. Also, OP Register 5 called PFAR
Request OP with address stored in 2 For REQ1, the address is sent from the S unit 102 to the MCU 11 as a prefetch address. In other words, a prefetch request (SET) is issued 4 cycles after the LMD signal is sent. P.F. REQ) signal, and if the DMR signal indicating a cache hit or miss is OFF (cache miss) in the next B cycle, the MS for block fetch request is sent. Send the REQ signal together with the LMD signal in R cycles. Also, if the DMR signal is ON (cash hit), the MS REQ is not sent. But OP Next OP of REQ1 The request address for REQ2 is OP Register 5 called PFAR
2, the prefetch request signal is not sent and the operand request (OP REQ2)
is ignored. Next, a conventional cache memory control system and its operation will be explained using FIG. Valid (OP T OP The VAL) signal is a signal indicating whether the operand request currently in the T cycle is valid. Valid signal is valid and 2
Bit port identification (OP T OP PORT
When the ID) signal becomes valid, the decoder DEC50 decodes ports 0, 1,
2 is selected, and the requested address is stored in the selected port in the R cycle. OP The TEAR register 51 is a register that stores an operand request address in the T cycle. The OP The input to TEAR register 51 is I
Operand request address (IU) from unit 102 OP REQ ADRS), OP Address from PFAR register 52, operand port (OP
PORT) Addresses from 0 to 2, block
Fetch address register (BFARO, 1,
2, 3) are selected in P cycles. OP The requested address of the operand stored in TEAR51 is TLB53 in T cycles.
is used to convert logical addresses to absolute addresses. At the same time, an operand cache directory (OP CACHE DIRECTORY) memory 54 and a MATCH circuit 55 are used to check whether the address is in the cache memory. The cache hit or miss signal is OP in the B cycle. It is set in the DMR register 56. Also, the absolute address from TLB53 is OP
PFAR register 52 and OP BAAR register 57
is stored in In the case of a cache hit, the requested address is opened in the B cycle. Stored in BEAR register 58 and OP CACHE DATA
Access ARRAY59 to read and write the cache. In the case of a cache miss, the absolute address is MSAR (Main
The address is stored in the Storage Address Register (Storage Address Register) register 60, and the address is used to access the main memory via the MCU 11. In this way, in the conventional cache memory control method, processing was interrupted in the B cycle.
OP The request address for REQ1 is OP It is stored in the PFAR register 52, and only this register is used to perform operand prefetch processing.
In other words, as shown in Figure 6, a cache error occurs and the OP The operand request (OP) that sent the LMD signal REQ) subsequent request OP REQ1 and
OP Processing of REQ2 is interrupted in cycle B and cycle T, respectively. OP The operand request (OP) that sent the LMD signal REQ) indicates that the request is T
OP during cycle T OP PORT OP in R cycle according to ID signal PORT0,
It is stored in either one of 1 or 2. In addition, the above
OP T OP PORT The ID signal takes a value of 0 to 2, and changes in cycles 0→1→2→0→1→..., and takes the value when the T cycle is VALID. OP whose processing was interrupted in B cycle
The request address of REQ1 is OP Stored in BEAR register 58 and OP It is stored in the PFAR register 52. After one more cycle, the OP when the request is T cycle T OP PORT
According to the ID signal, the requested address is OPEN PORT0,
It is stored in either one of 1 and 2. Similarly, processing was interrupted in T cycle.
OP The request address of REQ2 is OP Stored in TEAR register 51, and OPENed after one more cycle.
The requested address is stored in the BEAR register 58. But OP The PFAR register 52 contains
OP The requested address of REQ2 is not stored.
In other words, in the conventional technology, OP PFAR register 5
2 retains the value stored one cycle ago, and after another cycle, the OP when the request is T cycle. T OP PORT The requested address is OPENed according to the ID signal. Stored in one of PORT0, 1, and 2. Above OP OP of the request addresses stored in PORT0, 1, 2 OP that sent LMD REQ
Block fetch processing is performed on the requested address, and processing is restarted for other requested addresses after the above-mentioned request processing is completed. As mentioned above, in the conventional technology, the OP that caused a cache error The request passed to the S unit 101 after one cycle of REQ, that is, the OP REQ
OP immediately after Only the request address of REQ1 is OP
Since the data is stored in the PFAR register 52, the prefetch function for operand requests is quite limited. [Problems to be Solved by the Invention] As described above, in the conventional system, only the operand request immediately after the operand request that caused the cache error could be processed as a prefetch target. Therefore, if there are multiple operand requests following the operand request that caused the cache miss, or if there is a gap of two or more cycles between the operand requests, the above prefetch function may not be able to perform sufficiently. The question arose as to whether it was possible. The present invention eliminates these drawbacks of the prior art,
To provide a cache memory control method that makes it possible to process a plurality of operand requests after an operand request causing a cache error as targets for prefetching. [Means for Solving the Problems] The operation of the device according to the cache memory control method of the present invention is based on the OP that indicates a cache miss. LMD
If the request that immediately follows the request that sent the signal, or the request that occurs even later, is an operand request, the request that follows the request that caused the cache error is
By using the prefetch control device shown in the figure, it is possible to process the data as a prefetch target without ignoring it. The prefetch control device is OP LMD signal,
OP B OP VAL (Valid for requests whose processing was interrupted in B cycle) signal, OP B
OP PORT ID (Identification code of the request address storage port whose processing was interrupted in the B cycle)
signal, OP T OP VAL (Valid for a request whose processing was interrupted in T cycle) signal,
OP T OP PORT Receives the ID (identification code of the request address storage port whose processing was interrupted in the T cycle) signal and opens the OP Control PORT
SET P.F. REQ (controls sending of prefetch address) signal and OP PORT OUT
ID (identifies the port of the outgoing address)
Output a signal. OP The prefetch address stored in either PORT0, 1, or 2 will cause the prefetch to start 8 cycles after the request that caused the cache miss, and another 8 cycles for the subsequent prefetch address. SET above to start P.F. Controlled by REQ signal. In addition, when sending the above prefetch address, the above OP PORT OUT By ID signal
OP One of PORT0, 1, and 2 is selected. [Operation] The present invention stores request addresses for multiple operand requests following the operand request that caused a cache miss in a port register, and selects the contents of the port register using a control signal from a prefetch control device. ing. This makes it possible to prefetch all addresses of a plurality of subsequent operand requests without ignoring them. [Embodiment] The cache memory control method of the present invention will be explained using the system configuration diagram of the computer shown in FIG. 1 mentioned above. IU from I unit 100 REQ
The S unit 102, which receives an operand request by the ADRS signal, requests the I unit 100 if the operand exists in the cache memory.
OP STATUS VALID (OP STV) returns the signal. OP to I-unit 100 if the operand does not exist in cache memory.
LINE MISSING DETECT (OP LMD) signal and main memory control unit (MCU) 1
MS for 1 Send REQ signal, MCU11
A block fetch including the operand is performed by controlling the main storage unit (MSU) 12. In the computer system shown in FIG. 1 using a cache memory, if there is another operand request immediately after the operand request that caused the cache miss, the S unit 102 performs prefetch processing on the latter request. An explanatory diagram of the address control system of the present invention relating to the prefetch and its time chart are shown in FIGS. 2 and 4, respectively, and the cache memory control system of the present invention will be explained with reference to these figures. In Figures 2 and 4, the operand request (OP REQ) is P in S unit 102.
(Priority), T (Translative address), B
(Buffer access) and R (Result) are processed in each of the four cycles. In the R cycle, Buffer
If there is no data in the cache memory, a block fetch is performed, and if there is, the data in the cache memory is transferred to a general-purpose register in the CPU. DMR in Figure 4 is Directory Match
Register signal indicates that the cache is active if there is data for the request, and non-active if there is no data.
This is the signal. When the DMR is non-active and there is no data in the cache, the LMD signal that notifies a cache miss becomes active. At the same time, the S unit 102 REQ signal to MCU1
1 to request an exchange operation between the contents of main memory and cache memory.
If the LMD signal is issued, request the corresponding operand.
OP Operand request OP following REQ
REQ1, OP REQ2 is as shown in Figure 4,
Processing is interrupted once in each B cycle and T cycle. Processing was interrupted in B cycle
OP In the conventional technology, the operand address for the operand request of REQ1 is OP PFAR (Rri−
Fetch Address Register), and limited prefetch processing was performed. In the present invention, the OP that conventionally stores the prefetch address By removing the PFAR register and adding the prefetch control device shown in FIG. 3, which will be described later, the OP shown in FIG. PORT register 20
This makes it possible to hold, select, and send all requested addresses stored in the prefetch as targets for prefetching. The operation shown in FIG. 4 of this embodiment is OP The operand request (OP) that sent the LMD signal REQ) immediately following the request (OP) REQ1),
Or even a later request (OP REQ2), the request that caused the cache error (OP
REQ) followed by two of these requests (OP
REQ1, OP By using the prefetch control device shown in FIG. 3, REQ2) can be processed as a prefetch target without being ignored. Note that even if the number of requests to be prefetched exceeds two, there is no problem in principle and the number of requests can be expanded. Before explaining the timing chart in Figure 4,
First, the cache memory control system of the present invention and its operation will be explained using FIGS. 2 and 3. In the configuration diagram shown in Figure 2, Valid (OP T OP
The VAL) signal is a signal indicating whether the operand request currently in the T cycle is valid. Valid signal is valid and 2-bit port identification (OP TOP PORT When the ID) signal becomes valid, the decoder
One of ports 0, 1, and 2 is selected by the DEC 50, and the requested address is stored in the selected port in the R cycle. This OP The selection of which port to output from PORT0 to 2 is made by the prefetch control device 30 in Figure 3.
This is done by the output signal of OP The TEAR register 51 is a register that stores an operand request address in the T cycle. The OP The input to the TEAR register 51 is
Operand request address from I unit 102 (IU OP REQ ADRS), operand port (OP PORT0~2), block fetch address register (BFAR0,
1, 2, 3) are selected in P cycles. In the present invention, conventional OP PFAR
Register 52 is not present and therefore OP Address from PFAR register is OP TEAR register 5
1 is not entered. OP TEAR register 51
The requested address of the operand stored in is converted from a logical address to an absolute address using the TLB 53 in T cycles. At the same time, the operand cache directory (OP CACHE
DIRECTORY) Memory 54 and MATCH circuit 55
to see if the address is in cache memory. The cache hit or miss signal is OP in the B cycle. It is set in the DMR register 56. Also, the absolute address from TLB53 is OP It is stored in the BAAR register 57. In the case of a cache hit, the requested address is opened in the B cycle. BEAR register 58
stored in OP CACHE DATA ARRAY59
Access to read and write cash.
In the case of a cache miss, the absolute address is changed to MSAR (Main Storage Address) in the R cycle.
(Register) register 60, and its address is used to access the main memory via the MCU 11. The request that caused the cache error (OP REQ)
Multiple requests after (OP REQ1, OP REQ2)
A prefetch control device 30 of the present invention that executes control of processing for prefetching is shown in FIG. In this device, OP OP indicating cache miss of REQ request LMD signal, request whose processing was interrupted in B cycle (OP
OP indicating Valid for REQ1) B OP
VAL signal, request whose processing was interrupted in B cycle (OP OP indicating the identification of the port storing the request address for REQ1) B OP PORT
ID signal, request whose processing was interrupted in T cycle (OP OP indicating Valid for REQ2)
T OP VAL signal, request whose processing was interrupted in T cycle (OP OP indicating the identification of the port that stores the request address for REQ2) T OP
PORT Receive ID signal. And this device 30 is OP SET that controls PORT0 to 2, 20 and sends prefetch addresses P.F.
OP that identifies the port of the REQ signal and the address being sent PORT OUT Sends an ID signal. OP If a REQ request causes a cache miss, the OP The LMD signal becomes active, this signal becomes a trigger, and the OP B OP VAL，OP B
OP PORT ID, OP T OP VAL，OP
T OP PORT Each ID signal corresponds to the PF, which is a prefetch register. REQ
VAL, B, PF OP PORT ID B.PF
REQ VAL T, P.F. OP PORT ID The data is stored in each register of T. the two above
Valid signal (OP B OP VAL，OP T OP
VAL) using a circuit 301, and its output becomes a selection control signal for a decoder 302. Also, P.F. REQ VAL B signal is SET P.F.
It is reset when the priority is determined by the REQ signal. The decoder 302
OP PORT ID B and the PF OP PORT
ID Select each signal in the T register. Output signal OP of the decoder 302 PORT OUT The ID is the operand request (OP) that caused the cache miss.
REQ) followed by operand requests OP interrupted by cycles B and T, respectively. REQ1, OP
This is the port identification signal of the port that stores the request address for REQ2. Therefore, as shown in Figure 3, the operand request OP REQ1 and OP
Stores each request address of REQ2
OP If any one of the outputs of PORT0 to PORT2 is selected by the decoder 21 using the port identification signal,
All prefetched request addresses will not be ignored and will be sent. OP OP stored in either PORT0, 1, or 2 As shown in the time chart in Figure 4, the prefetch address corresponding to REQ1 is the request that caused the cache error (OP 8 cycles after the P cycle of REQ), and the subsequent OP
For the prefetch address corresponding to REQ2, activation of prefetch is started from the P cycle eight cycles later. This start is performed by the SET signal output from the prefetch control device 30. P.F.
Controlled by REQ signal. In addition, when sending the above prefetch address, the above OP sent in the P cycle PORT OUT By ID signal
OP One of PORT0, 1, and 2 is selected. Also, the request sent as a prefetch (OP REQ1, OP In REQ2), OP indicating whether or not it exists in the cache in the B cycle If the contents of the DMR register 56 are OFF (cache miss), the
M.S. The REQ signal is sent out in R cycles along with the LMD signal. Also, the ON state, that is, the cash
MS of prefetch request if hit
No REQ signal is sent. [Effects of the Invention] According to the present invention, the prefetch control device does not ignore all requests after the request that caused caching as targets for prefetching.
Therefore, the prefetch function for operand requests is improved, and fast and efficient cache processing is possible.
Memory control becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a computer system having a cache memory, and FIG. 2 is a configuration diagram of a computer system having a cache memory.
A block diagram of an address control system related to prefetch using the memory control method, FIG. 3 is a block diagram of a prefetch control device according to the present invention, FIG. 4 is a time chart in the present invention, and FIG. 5 is a conventional cache memory control method. FIG. 6 is a block diagram of an address control system related to prefetch according to the present invention, and is a time chart in the conventional system. 10...Central processing unit (CPU), 11...Main memory control unit (MCU), 12...Main storage unit (MSU), 2
0... Port register, 21... Decoder, 30... Prefetch control device in the present invention, 50... Decoder, 51... OP that stores operand request address in T cycle. TEAR (Operand T-
cycle Effective Address Register) register,
52...OP that stores the prefetch address
PFAR register (prior art), 53... TLB for converting logical addresses to absolute addresses, 54... Operand cache directory memory, 5
5...MATCH circuit, 56...OP that sets a signal indicating cache hit or miss. DMR register, 57... BAAR (B-
cycle Absolute Address Register) register,
58...OP that stores the cache request address BEAR register, 59... Operand cache data array, 60... MSAR register that stores the absolute address in case of cache miss, 100... Instruction () unit, 101... Execution (E) unit, 102... S (Storage) unit , 301...gate circuit, 302...decoder.

Claims (1)

[Claims] 1. Command control unit 10 in central processing unit 10
0 gives an address to a cache memory that holds a copy of a portion of the contents of main memory 12; if the address is in the cache memory, it controls the cache hit; if the address is not there, a cache miss occurs. The cashier that controls the
The memory control unit 102 receives a cache reference request (OP) sent from the instruction control unit 100. REQ) causes a cache error, the request (OP) that caused the cache error
Multiple requests (OP) after REQ) REQ1, OP
a plurality of main memory read ports 20 for storing at least request addresses whose processing has been interrupted for REQ2,...), and a cache read port 20 for notifying the cache miss.
Miss signal (OP LMD), the reference request that caused the cache miss (OP All reference requests (OP) after the REQ) REQ1, OP VALID signal (OP B OP VAL，OP T OP VAL,
), and the identification signal (OP B OP PORT ID, OP T OP
PORT ID,...) and enter the reference request (OP ID,...) that caused the cache error. All the reference requests (OP) interrupted every predetermined cycle from REQ1, OP A control signal (SET P.F. REQ) and a selection control signal (OP PORT OUT ID) and a prefetch control means 30 for forming a cache ID).
The reference request that caused the error (OP All requests (OP) after multiple requests (REQ) REQ1, OP REQ2,…)
A cache memory control method characterized in that a request address for a cache is processed as a prefetch target without being ignored.