JPH0456461B2 - - Google Patents
Info
- Publication number
- JPH0456461B2 JPH0456461B2 JP57131561A JP13156182A JPH0456461B2 JP H0456461 B2 JPH0456461 B2 JP H0456461B2 JP 57131561 A JP57131561 A JP 57131561A JP 13156182 A JP13156182 A JP 13156182A JP H0456461 B2 JPH0456461 B2 JP H0456461B2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- leads
- metal piece
- alloy
- plated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/328—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by welding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔発明の技術分野〕 この発明は混成集積回路の製造方法に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to a method of manufacturing a hybrid integrated circuit.
従来、混成集積回路は第1図及び第2図に示す
ように製造している。すなわち、絶縁基板、たと
えばセラミツク基板1の一面に厚膜ペースト印刷
により形成された回路配線基板などの所要個所に
半田ペーストを印刷した後、この半田ペースト上
に集積回路素子(IC)、トランジスタ、ダイオー
ドなどの半導体素子2やコンデンサ3などの部品
をマウントし、熱板などにより加熱、半田付け4
するとともに洗浄、フアンクシヨントリミング、
特性チエツクなどの工程を経てケース付け(図示
せず)する混成集積回路のアウタリードの取出方
法は次のように行つている。まず、第1図Aのよ
うに、ヘツド6を有するアウタリード5を基板1
のアウタリード取出電極部に垂直に設置し、その
電極部で半田付けするものである。しかしこの方
法では、リード5を1本づつ半田付けしなければ
ならず、よつて作業時間がかかり、量産的でない
上、基板1とリード5との接続が半田のみによる
ため、引張りに対して接着強度が弱いという欠点
がある。
Conventionally, hybrid integrated circuits have been manufactured as shown in FIGS. 1 and 2. That is, after printing solder paste at required locations on an insulating substrate, such as a circuit wiring board formed by thick film paste printing on one side of a ceramic substrate 1, integrated circuit elements (ICs), transistors, and diodes are printed on the solder paste. Mount components such as semiconductor elements 2 and capacitors 3, heat them with a hot plate, etc., and solder them 4.
Along with cleaning, function trimming,
The method for taking out the outer leads of a hybrid integrated circuit, which is attached to a case (not shown) after undergoing processes such as characteristic checking, is as follows. First, as shown in FIG. 1A, the outer lead 5 having the head 6 is attached to the substrate 1.
It is installed perpendicularly to the outer lead extraction electrode section of the terminal, and is soldered at that electrode section. However, with this method, the leads 5 must be soldered one by one, which takes time and is not suitable for mass production. Furthermore, since the connection between the board 1 and the leads 5 is made only by soldering, the adhesive is not able to withstand tension. It has the disadvantage of being weak in strength.
この接着強度を改良したものとして第1図Bに
示す方法がある。これは、基板1のアウタリード
5の植設部に穴孔7を設け、ヘツド6を有するリ
ード5を基板1の裏側から挿入するものである。
しかしこの方法では、リード5を裏側から1本づ
つ挿入するため、作業性が悪い上、基板1の表面
でのハンダ付部分4の接触面積が少ないため、オ
ープンになりやすい欠点がある。そこで、この接
触面積を大きくするよう改良したものとして第1
図Cに示す方法がある。これは、アウタリード5
の中間に鍔8を有するものを用い、このリード5
を基板1の表面から挿入し、裏面に突出したリー
ド5の部分をつぶすことにより強固に固定するも
のである。しかしこの方法も、リード5を1本づ
つ挿入しなければならず、しかも基板1の裏側に
おいて、リード5の突出部分をつぶす作業工程が
新たに増えるという欠点がある。 There is a method shown in FIG. 1B that improves this adhesive strength. In this case, a hole 7 is provided in the part of the substrate 1 where the outer lead 5 is installed, and the lead 5 having the head 6 is inserted from the back side of the substrate 1.
However, in this method, the leads 5 are inserted one by one from the back side, which has the disadvantage of poor workability, and because the contact area of the soldered portion 4 on the surface of the board 1 is small, it tends to become open. Therefore, the first method was developed to increase this contact area.
There is a method shown in Figure C. This is Outer Lead 5
This lead 5 has a collar 8 in the middle.
is inserted from the front surface of the substrate 1, and is firmly fixed by crushing the portion of the lead 5 protruding from the back surface. However, this method also has the drawback that the leads 5 must be inserted one by one, and furthermore, an additional work step for crushing the protruding portions of the leads 5 on the back side of the substrate 1 is added.
そこで、上述したようなリード5を1本づつ電
極部に半田付けするという煩雑さを解消したも
の、また引張りに対する接着強度を向上させたも
の、さらに基板1からの浮きを改良したものとし
て第2図に示すような方法がある。すなわち、第
2図A,Bは基板1にあらかじめ半田ペーストを
印刷しておき、この半田ペースト部に電子部分と
同時にリード5を半田付けするもので複数のリー
ドが一体化されたリードフレームを用いるもので
ある。また第2図Cは、第1図B,Cと同様に基
板1にあらかじめ穴孔7を設け、この穴孔7に先
端「ト」字状のリード5の突出部9を挿入し、半
田付けするものである。さらに第2図D,Eは、
先端が凹状になつたリード5を用い、このリード
5の凹部10で基板1の電極部を喰わえ込むよう
に設置し、この状態で半田付けして固定するもの
である。 Therefore, we have developed a second method that eliminates the complexity of soldering the leads 5 one by one to the electrode parts as described above, improves the adhesive strength against tension, and improves the floating from the substrate 1. There is a method as shown in the figure. That is, in FIGS. 2A and 2B, solder paste is printed on the board 1 in advance, and the leads 5 are soldered to the solder paste part at the same time as the electronic parts, and a lead frame in which multiple leads are integrated is used. It is something. In addition, in FIG. 2C, a hole 7 is provided in advance in the board 1 as in FIGS. It is something to do. Furthermore, Figure 2 D and E are
A lead 5 having a concave tip is installed so that the recess 10 of the lead 5 bites into the electrode part of the substrate 1, and in this state it is fixed by soldering.
しかし、これらリードフレームは、第1図のリ
ードピンに比較して基板1への取付け力が強固で
容易であるが、各リードが一体化されているた
め、フアンクシヨントリミング特性チエツク前に
リードを切断しなければならない。また、第1図
および第2図の何れのものもリードピン、リード
フレームともに基板1よりリード5が突出してい
るため、半田ペースト印刷基板へリードを取付け
た後の加熱半田付け、洗浄、フアンクシヨントリ
ミング特性チエツクにおいて取扱いにくく、作業
性がきわめて悪いという問題があつた。 However, these lead frames have a stronger and easier attachment force to the substrate 1 than the lead pins shown in Fig. 1, but since each lead is integrated, it is necessary to attach the leads before checking the function trimming characteristics. Must be disconnected. In addition, in both the lead pins and lead frames in both Figures 1 and 2, the leads 5 protrude from the board 1, so the heat soldering, cleaning, and fusing after attaching the leads to the solder paste printed board are difficult. When checking the trimming characteristics, there was a problem that it was difficult to handle and the workability was extremely poor.
この発明は上記の点に鑑みてなされたもので、
その目的は基板のリードを取出す電極部にSn、
Pb、Zn等の低融点金属あるいはその合金メツキ
処理したFe板片あるいはFe合金板片よりなる金
属片を半田付けし、この金属片に金属片と同様の
メツキ処理をしたCuあるいはCu合金よりなるリ
ードを溶接することによつて、作業性の向上が図
れ、リードの確実かつ強固な取付けが可能とな
り、信頼性が向上するとともに、量産性にも優れ
た混成集積回路の製造方法を提供することにあ
る。
This invention was made in view of the above points,
The purpose is to add Sn to the electrode part from which the leads of the board are taken out.
A metal piece made of an Fe plate or Fe alloy plate plated with a low melting point metal such as Pb or Zn or its alloy is soldered, and this metal piece is made of Cu or a Cu alloy plated with the same plating process as the metal piece. To provide a method for manufacturing a hybrid integrated circuit which improves workability by welding the leads, enables reliable and strong attachment of the leads, improves reliability, and is excellent in mass production. It is in.
基板のリードを取出す電極部にSn、Pb、Zn等
の低融点金属あるいはその合金メツキ処理した
Fe板片あるいはFe合金板片よりなる金属片を半
田付けし、この金属片に金属片と同様のメツキ処
理をしたCuあるいはCu合金よりなるリードを溶
接することによつてリードの確実かつ強固な取付
けを行なつている。
The electrode part from which the leads of the board are taken out is plated with low melting point metals such as Sn, Pb, and Zn, or their alloys.
By soldering a metal piece made of an Fe plate piece or an Fe alloy plate piece and welding a lead made of Cu or Cu alloy that has been plated in the same way as the metal piece, the lead can be made reliable and strong. Installation is in progress.
以下、図面を参照してこの発明の一実施例を説
明する。まず、第3図Aに示すように絶縁基板と
してのセラミツク基板31の一方面上に厚膜ペー
スト印刷により回路配線基板を形成し、この回路
配線基板の電子部品取付け部分に半田ペーストを
印刷する。次に、この半田ペーストを設けた部分
に能動素子や受動素子、つまりICやトランジス
タなどの半導体素子32およびコンデンサ33な
どを半田付けするとともに、これと同時に電極部
34に金属片35などを半田付けする。この金属
片35は、たとえば錫(Sn)、鉛(Pb)、亜鉛
(Zn)などの低融点金属あるいはその合金メツキ
処理した鉄(Fe)鉄片または鉄合金板片であれ
ば良いが実施例においては鉄にSnメツキしたも
のを使用している。次に、この半田付け工程終了
後、洗浄、フアンクシヨントリミング特性チエツ
クなどの工程を行う。
Hereinafter, one embodiment of the present invention will be described with reference to the drawings. First, as shown in FIG. 3A, a circuit wiring board is formed by thick film paste printing on one side of a ceramic substrate 31 serving as an insulating substrate, and solder paste is printed on the electronic component mounting portion of this circuit wiring board. Next, active elements and passive elements, that is, semiconductor elements 32 such as ICs and transistors, capacitors 33, etc. are soldered to the parts provided with this solder paste, and at the same time, metal pieces 35 etc. are soldered to the electrode parts 34. do. The metal piece 35 may be a low melting point metal such as tin (Sn), lead (Pb), or zinc (Zn) or an iron (Fe) plate plated with an alloy thereof, but in the embodiment, uses Sn-plated steel. Next, after this soldering process is completed, processes such as cleaning and checking the function trimming characteristics are performed.
次に第3図BまたはCに示すように、上記金属
片35にヘツド36を有するリード37あるいは
リードフレーム38を、たとえばウエルドマシー
ンにより自動溶接する。上記リード37およびリ
ードフレーム38はたとえば金属片と同様のメツ
キ処理をした銅(Cu)または銅合金であれば良
いが、実施例においては銅に半田メツキを施こし
たものを使用している。 Next, as shown in FIG. 3B or C, a lead 37 or a lead frame 38 having a head 36 is automatically welded to the metal piece 35 using, for example, a welding machine. The leads 37 and lead frame 38 may be made of copper (Cu) or a copper alloy that has been plated in the same manner as the metal pieces, but in the embodiment, solder plated copper is used.
また、上記実施例に記述したように、金属片3
5をSnメツキ処理をした鉄片とし、さらに一般
的な硫酸浴にて電流密度0.5〜1A/cm2で1.0〜1.5
時間のバレルメツキを施すことによりリード37
にメツキ厚が3〜8μの半田メツキをしてから金
属片35とリード37とを自動溶接した後に、強
度テスト(引張テスト)を行つた結果、8Kg以上
の十分な強度を示した。このため、リード37が
引つ張りにより切断して溶接面より剥離すること
はなくなるので、リード37の基板31への溶接
の信頼性を向上させることができる。 Further, as described in the above embodiment, the metal piece 3
5 is an iron piece that has been plated with Sn, and further in a general sulfuric acid bath at a current density of 0.5 to 1 A/ cm2 at a current density of 1.0 to 1.5.
Lead 37 by applying time barrel plating
After solder plating with a plating thickness of 3 to 8 μm and automatically welding the metal piece 35 and the lead 37, a strength test (tensile test) was conducted, which showed sufficient strength of 8 kg or more. Therefore, the lead 37 is not cut due to tension and is not separated from the welding surface, so that the reliability of welding the lead 37 to the substrate 31 can be improved.
以上詳述したようにこの発明によれば、混成集
積回路基板の電極部にリードを取付けするに際
し、あらかじめSn、Pb、Zn等の低融点金属ある
いはその合金メツキ処理したFe板片あるいはFe
合金板片よりなる金属片を半田付けし、この金属
片に金属片と同様のメツキ処理をしたCuまたは
Cu合金よりなるリードを溶接するようにしたの
で、リードと金属片との信頼性のある溶接を得る
ことができる。
As described in detail above, according to the present invention, when attaching leads to the electrode parts of a hybrid integrated circuit board, an Fe plate piece or an Fe plate plated with a low melting point metal such as Sn, Pb, or Zn or an alloy thereof or an alloy thereof is used.
A metal piece made of an alloy plate piece is soldered, and this metal piece is coated with Cu or plated in the same way as the metal piece.
Since the lead made of Cu alloy is welded, reliable welding between the lead and the metal piece can be obtained.
第1図および第2図は従来の混成集積回路の製
造方法を説明するための図、第3図はこの発明に
係る混成集積回路の製造方法の一実施例を説明す
るための図である。
31……セラミツク基板、34……電極部、3
5……金属片、36……ヘツド、37……リー
ド、38……リードフレーム。
1 and 2 are diagrams for explaining a conventional method for manufacturing a hybrid integrated circuit, and FIG. 3 is a diagram for explaining an embodiment of the method for manufacturing a hybrid integrated circuit according to the present invention. 31... Ceramic substrate, 34... Electrode part, 3
5...metal piece, 36...head, 37...lead, 38...lead frame.
Claims (1)
するに際し、あらかじめSn、Pb、Zn等の低融点
金属あるいはその合金メツキ処理したFe板片あ
るいはFe合金板片よりなる金属片を半田付けし、
この金属片に金属片と同様のメツキ処理をしたメ
ツキ厚が3〜8μのCuまたはCu合金よりなるリー
ドを溶接することを特徴とする混成集積回路の製
造方法。1. When attaching leads to the electrodes of a hybrid integrated circuit board, first solder a metal piece made of an Fe plate or Fe alloy plate plated with a low melting point metal such as Sn, Pb, or Zn or its alloy,
A method for manufacturing a hybrid integrated circuit, which comprises welding to this metal piece a lead made of Cu or Cu alloy, which has been plated in the same manner as the metal piece and has a plating thickness of 3 to 8 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57131561A JPS5922351A (en) | 1982-07-28 | 1982-07-28 | Manufacture of hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57131561A JPS5922351A (en) | 1982-07-28 | 1982-07-28 | Manufacture of hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5922351A JPS5922351A (en) | 1984-02-04 |
| JPH0456461B2 true JPH0456461B2 (en) | 1992-09-08 |
Family
ID=15060939
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57131561A Granted JPS5922351A (en) | 1982-07-28 | 1982-07-28 | Manufacture of hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5922351A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61202839U (en) * | 1985-06-10 | 1986-12-19 | ||
| JPS6256310U (en) * | 1985-09-28 | 1987-04-08 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6259461A (en) * | 1985-09-10 | 1987-03-16 | Matsushita Electric Ind Co Ltd | Bipolar type image sensor intergrated circuit |
-
1982
- 1982-07-28 JP JP57131561A patent/JPS5922351A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5922351A (en) | 1984-02-04 |
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