JPH0456507B2 - - Google Patents

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention is directed to scanning binary (for example, black and white) original images containing characters, maps, illustrations, etc. in an image scanning storage device such as a plate-making scanner or facsimile. input multi-gradation image data (line drawings are scanned, but white and black may coexist within the reading pixels of the original image, in which case they are averaged within the reading pixels of the original image and multi-level image data is scanned). The present invention relates to a device for generating binary image data having a resolution higher than that of the input multi-tone image data.

(Prior art and its problems) When image data is input by scanning an original image in an image scanning recording device, there is a limit to the resolution of the input image data obtained due to technical or economic constraints.

For example, CCD image scanners for document reading, which are commercially available and generally available for OA equipment,
Currently, the upper limit is around 400 scan lines/inch (input resolution of 63.5 μm square), and this resolution is sufficient for practical purposes.

On the other hand, if we consider a binary image processing device that scans and inputs a binary image, performs some image processing, and then outputs it at the original size, for example, jaggy does not appear at the edges of the output image. The output scan line count is 1500 lines/inch.
It is said that a resolution of approximately (16.9 μm square) or higher is desirable. Therefore, assuming full-size processing, this level of high resolution is desired on the input side as well.

However, a binary image input device that can read at 1500 lines/inch or more is quite expensive.

(Objective of the Invention) Therefore, an object of the present invention is to solve the above-mentioned problems of the prior art, and to solve the problems of the prior art without directly obtaining high resolution from a binary image input device. An object of the present invention is to provide a high-resolution binary image data generation device that can obtain higher-resolution binary image data from input image data by using the input image data.

(Means for achieving the object) In order to achieve the above object, the high-resolution binary image data generation device according to the present invention uses multi-tone image data obtained by scanning an original image,
An image data storage circuit that stores data for an image area of a predetermined size; and a threshold that calculates the sum of gradation values of a plurality of pixels within the image area and determines a threshold value based on this value. a value determining circuit; distinguishing a plurality of pixels in the image area into a central pixel and peripheral pixels, and binarizing peripheral pixels based on the threshold value determined by the threshold value determining circuit; a comparison circuit; a binary image pattern having a resolution higher than that of the multi-gradation image data and created in advance corresponding to the gradation value of the center pixel and the array of the binarized peripheral pixels; a pattern storage circuit for storing data; outputting corresponding high-resolution binary image pattern data from the pattern storage circuit using the gradation value of the center pixel and the array of the binarized peripheral pixels as addresses; It is characterized by being made to do.

(Operation) The original image is read as multi-tone image data, and the multi-tone image data is stored in an image data storage circuit for an image area of a predetermined size.

A plurality of pixels within this image area are divided into a center pixel and surrounding pixels, and the surrounding pixels are binarized by a comparator using a predetermined threshold value as a reference.

For each combination of the gradation value of the central pixel and the array of binarized peripheral pixels, binary image pattern data with a resolution higher than the resolution of the multi-gradation image data is associated in advance and created. By inputting the gradation value of the center pixel of the center pixel and the arrangement information of its surrounding pixels to the pattern memory circuit as an address, the corresponding high-resolution binary value can be stored. Image pattern data can be obtained as output.

Moreover, the threshold value is automatically determined by the threshold value determination circuit based on the sum of the gradation values of multiple pixels in the target image area, so it can be adjusted according to the aspect of the original image. It becomes possible to obtain detailed image output.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of a high-resolution binary image data generation device according to the present invention. From the input terminal 1, a binary (for example, black and white. This example will be explained in black and white) original image is input at, for example, 400.
Scan line count in lines/inch (63.5μm square resolution)
Image data read in multiple gradations is input (line drawings are scanned, but white and black may coexist within the reading pixels of the original image, in which case they are averaged and multi-leveled within the reading pixels of the original image. ),
From the output end 2, binary image data having a resolution higher than that of the input multi-tone image data is output.

For example, when a CCD scanner is used to read an original image, the read image is accumulated as an analog charge in each cell of the CCD element and converted into a voltage or current value.

Therefore, the read image is obtained as a multi-tone level signal.

On the other hand, in the case of a drum-type scanner for plate making, the light intensity of a read image is converted into an analog current value using a photomultiplier. Therefore, in any type of input device, the original image is read as a gray-scale image with gradation at the light receiving element stage, and it is applicable to the present invention.

Although the gradation width of the image data applied to the input terminal 1 may be any width, an example in which 8 gradation (3 bits) image data is input will be described below.

The data of each pixel (3 bits each) of the 8-gradation image data inputted from the input terminal 1 is sequentially stored in the line memory 3 under timing control by a timing control means (not shown), and is to be processed. Pixel is input terminal 1 and line memory 3
The data is then read out to the latch circuit 4 in the form necessary for processing and sequentially stored, forming an image data storage circuit.

The line memory 3 is a first memory for storing one line of input 8-gradation image data as it is in 8 gradations.
3-bit line memory 3a, and a second 3-bit line memory 3b connected in series to this 3-bit line memory 3a.

The latch circuit 4 includes 3-bit latches 4c, 4b, 4a connected in series from the output end of the second 3-bit line memory 3b, and 3-bit latches 4c, 4b, 4a connected in series from the output end of the first 3-bit line memory 3a. 3-bit latches 4f, 4e, 4d and 3-bit latches 4i, 4 connected in series from input terminal 1
h, 4g.

In such a connection, for example,
Using a timing control method such as that disclosed in Japanese Patent No. 194561, the latch circuit 4 inputs a 3×3 input image.
Image data in the pixel area is sequentially extracted.

This results in these nine 3-bit latches 4
Image data of an image area formed by 3×3 pixels is sequentially input to a to 4i. The position of the pixel in this image area is A, as shown in Figure 2a.
Assuming B, C, D, E, F, G, H, and I, the image data of each pixel is stored in nine 3-bit latches 4a to 4 corresponding to the alpha alphabet of that pixel.
i respectively.

6 is a comparison circuit for binarizing peripheral pixels A to D and F to I based on a predetermined threshold value S, and is composed of eight comparators 61 to 68.

One input X of each of the comparators 61 to 68 in the comparison circuit 6 is supplied with 3-bit data of each of the peripheral pixels A to D, F to I, and the other input Y is supplied with a threshold value determination circuit, which will be described later. A 3-bit threshold value S set by 7 is given.

Each comparator 61 to 68 compares the X input and the Y input, and returns "1" when X≧Y, and "0" when X<Y.
The peripheral pixels are binarized by outputting 1-bit data of each.

The 8-gradation (3-bit) center pixel E and the 8-gradation (3-bit) peripheral pixels A, B, C, D, F, G, H, and I extracted in this way total 11
The bit data is stored as a pattern memory circuit.
Given to the address input of ROM5.

This address input represents a combination of the gradation value of the center pixel and the data pattern of its surrounding pixels in the 3×3 pixel area of the input pixel,
The ROM 5 stores the resolution of the input image (corresponding to the number of scan lines of 400 lines/inch in the above example) in association with each combination (that is, each address).
Binary image pattern data (for example, 5×5 high-resolution pixel data) with a resolution higher than 63.4 μm square resolution is stored in advance.

Then, the ROM 5 reads out the binary image pattern data stored at the address to the output terminal 2 in accordance with the given address input.

Next, with reference to FIGS. 2 and 3, the above-described processing procedure will be explained based on a specific example.

(1) First, read the binary original image shown in a of both figures (only 3 x 3 pixels are displayed in the figures) as 8-gradation image data (gradation values), and 3×3 pixels are stored in the latch circuit 4 as shown in FIG.

(2) Assuming that the threshold value S set by the threshold value determination circuit 7 is 4, each of the comparators 61 to 68 of the comparison circuit 6
, compare the image data value of each peripheral pixel with the threshold value S, and set the peripheral pixels A to D, F to I as "1" when the image data ≧ 4, and as "0" when the image data < 4. Convert to binary image.

This situation is shown in c.

(3) Gradation value of center pixel E and surrounding pixels A~ in c above
High-resolution pattern data of the center pixel E as shown in d is generated according to the combination with the data pattern consisting of the array of "0" and "1" of D, F to I.
Read from ROM5.

This high-resolution pattern data may be obtained by a computer using an appropriate algorithm for all combinations of the gradation value of the center pixel and the data pattern of surrounding pixels, or each data may be obtained from the edges as much as possible. You may also artificially seek it so that it is smooth.

An example of artificially obtaining high-resolution pattern data in which one pixel of an input image is divided into 5.times.5 dots is shown in FIGS. 4A to 4C.

The hatched area in the top column of each figure indicates the position of "1" of the surrounding pixel, and "0" to "7" in the leftmost column.
The numbers up to 1 indicate the gradation value of the center pixel E. Based on the arrangement of these peripheral pixels and the gradation value of the center pixel E, each high-resolution binary image data is rationally formed and assigned.

In this case, the number of combinations obtained by the arrangement of "0" and "1" of the eight peripheral pixels and the gradation value (8 gradations) of the center pixel E is 2 ⁸ × 8 = 2048 (ways). In this way, it is possible to obtain high-resolution binary image data having a maximum of 2048 patterns for one central pixel E, thereby making it possible to obtain an image output pattern that is extremely close to the original image.

In the above example, the case where the threshold value S is "4" was explained, but for example, when processing an original image consisting of very thin lines, the average density of the read area becomes small. If you lower the threshold value S and operate it so that the thin line information (average gradation value is small) in the surrounding pixels will not be lost when you binarize multi-gradation surrounding pixel data. This will further improve reliability when increasing resolution.

The threshold value determination circuit 7 automatically performs such operations to determine an appropriate threshold value S.

A total of 27 bits of image data is input to the threshold value determination circuit 7 from each of the nine 3-bit latches 4a to 4i in the latch circuit 4, and image information in a 3×3 pixel area of the input image is input. Given.

This threshold value determination circuit 7 is configured as shown in FIG. 5, for example, and includes a series of adders 71 to
78, the area of the black (solid) portion within the 3×3 pixel area is calculated by determining the sum Σ of each input 3-bit pixel data.

Then, according to the calculated area of the black background (solid) part, a 3-bit threshold value S stored in advance in the lookup table 8 is read out,
This threshold value S is applied to each of the eight comparators 61 to 68 in the comparison circuit 6.

As a result, for example, in the case of an original image consisting of thin lines, the black background (solid) area becomes small, so the threshold value S can be automatically lowered accordingly.

FIG. 6 is a graph showing an example of the threshold value S that should be stored in advance in the lookup table 8 of FIG.

Using such a lookup table 8,
When the binary images shown in FIG. 7a and FIG. 8a are processed, the following results are obtained.

The gradation values of each pixel in the image data of each binary image are as shown in b in each figure, and when the sum Σ is calculated from these gradation values using the circuit shown in Figure 5, it is as follows. .

<Figure 7> Σ=13 <Figure 8> Σ=47 These total values refer to the P point and Q point in Figure 6, respectively, and are the threshold output from the lookup table 8. The value S is as follows.

<Figure 7> 2.4 <Figure 8> 4.9 When the data values of the surrounding pixels in each figure b are binarized based on each threshold value S above, each c
become that way.

Then, the 3-bit data regarding the center pixel E with 8 gradations and the total 8-bit data regarding the binary peripheral pixels A to D and F to I are input to the address of the ROM 5 that stores the high-resolution binary pattern data. It is possible to obtain an output pattern extremely close to the original image as shown in d.

This makes it possible to accurately recognize even thin lines smaller than the pixel width in the original image, and to achieve high resolution.

(Effects of the Invention) As described above, according to the present invention, image data read in multiple gradations is stored in the image data storage circuit for a predetermined size of image area centered on pixels that are sequentially read. A plurality of pixels in the image area are distinguished into a center pixel and a peripheral pixel, and the latter is binarized using a predetermined threshold value.
Binary image pattern data with a resolution higher than the resolution of the multi-tone image data is stored in advance in association with the combination of the gradation value of the central pixel and the array of binarized peripheral pixels. By inputting information on the gradation value of the center pixel and the arrangement of its surrounding pixels to the pattern storage circuit as an address, corresponding high-resolution binary image pattern data can be obtained as output.

As a result, it is possible to read a binary original image as a multi-tone image and use the resulting gradation to obtain binary image data with a resolution higher than that of the multi-tone image. It is possible to obtain higher resolution binary image data by using an inexpensive low resolution input device.

Moreover, the threshold value, which is the standard for binarizing surrounding pixels, is automatically determined in the threshold determination circuit based on the sum of the tone values of multiple pixels in the target image area. , it is possible to obtain an optimal high-resolution image output according to the aspect of the original image.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2, 3, 7, and 8 are explanatory diagrams showing the procedure of image processing according to the invention,
Figures A to 4C are diagrams showing examples of high-resolution binary image patterns, Figure 5 is a block diagram showing an example of a threshold value determination circuit, and Figure 6 is a diagram showing examples of high-resolution binary image patterns. It is a figure which shows an example of the threshold value to be memorized. 1...Input end, 2...Output end, 3...Line memory, 4...Latch circuit, 5...Binary image pattern data storage ROM, 6...Comparison circuit, 7...Threshold value determination circuit .

Claims (1)

[Scope of Claims] 1. An image data storage circuit that stores multi-tone image data obtained by scanning an original image for an image area of a predetermined size; a threshold value determination circuit that calculates the sum of adjustment values and determines a threshold value based on this value; a comparison circuit that binarizes based on the threshold value determined by the threshold value determination circuit; and a comparison circuit having a resolution higher than the resolution of the multi-tone image data, a pattern storage circuit that stores binary image pattern data created in advance corresponding to the array of the binarized peripheral pixels, and the gradation value of the center pixel and the binarized peripheral pixels. 1. A high-resolution binary image data generation device, wherein the pattern storage circuit outputs corresponding high-resolution binary image pattern data by using an array as an address.