JPH0458177B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for etching a compound semiconductor layer containing gallium or arsenic with extremely high precision.

(b) Background of the technology At present, with the aim of further improving the performance and cost performance of information processing equipment, semiconductor devices are becoming faster and lower in power consumption. Many transistors using much larger compound semiconductors such as gallium arsenide (GaAs) have been proposed. Among these compound semiconductor transistors, heterojunction field effect transistors (hereinafter referred to as heterojunction field effect transistors) achieve an increase in carrier mobility through modulation doping and electrons spatially separated from impurities.
(abbreviated as FET).

Furthermore, in systems that use light as an information signal medium, such as optical fiber communications, optical semiconductor devices such as semiconductor lasers and photodiodes are the most important and fundamental components. In these optical semiconductor devices as well, improvements in their characteristics are being promoted by using a superlattice structure in which the double heterostructure active layer and the like have quantum theoretical dimensions.

As shown in the above example, the ultra-fine design of semiconductor devices requires not only submicronization of the pattern on the semiconductor substrate surface, but also control of the thickness of the semiconductor substrate to about 10 [nm] in the thickness direction. be done.

(c) Prior art and problems In order to form a pattern on a semiconductor substrate surface in the manufacturing process of a semiconductor device, selective etching is performed using a mask or the like. It is sometimes necessary to perform etching to a midpoint in the thickness direction of two semiconductor layers and control the etching accuracy to, for example, 10 [nm] or less.

Conventionally, as an etching method in the manufacturing process of semiconductor devices, for example, a wet etching method using a phosphoric acid (H ₃ PO ₄ ) or hydrofluoric acid (HF) based solution has been performed on GaAS substrates. However, in the wet etching method, selectivity in the etching direction is usually low, and side etching progresses to a large extent, resulting in a significant drop in putter accuracy, and it is extremely difficult to uniformly and precisely control the etching depth.

For the purpose of improving pattern accuracy on the surface of a semiconductor substrate and streamlining the process, the wet etching method is being replaced by a dry etching method.

Dry etching techniques include those in which the etching mechanism is based on chemical action, physical action, and chemical and physical action.

An example of a chemical dry etching method is a plasma etching method. The low-temperature gas plasma normally used in plasma etching is obtained by introducing a suitable reactive gas into a reaction tube at a pressure of about 0.1 to 10 [Torr] and applying high-frequency power to it. Although the degree of ionization of this gas plasma is usually low, it contains many atoms and molecules that have become excited through various collision processes. Atoms and molecules in this excited state have high chemical activity, and a chemical reaction occurs between them on the sample surface that comes into contact with the gas plasma. As a result, volatile reactants are generated, and the atoms and molecules are removed from the sample surface. is removed and etched.

This plasma etching method is usually highly selective to the material to be processed, and the etching direction is isotropic.

On the other hand, the physical dry etching method is an etching method that utilizes the sputtering phenomenon that occurs when particles with large kinetic energy, usually ions, collide with a solid surface. This method can suppress undercuts under the mask by using a uniform incident ion beam with a uniform direction, but it has poor selectivity with respect to the material to be processed, and the ion bombardment may cause damage to the semiconductor substrate. It is necessary to pay attention to the damage caused by

Although an inert gas is used in the sputter etching method, by using this as a reactive gas, a chemical reaction and a sputtering effect coexist, and selectivity with respect to the material to be processed and the etching direction can be obtained. This etching method is called reactive ion etching or reactive sputter etching.

Among the various dry etching methods explained above,
As examples applied to GaAs chemical semiconductors, there are known reactive ion etching methods using chlorine-based or fluorine-based gases, and plasma etching methods using hydrogen (H ₂ ) gas.

Since the reactive ion etching method using chlorine-based or fluorine-based gas usually has a high etching rate (generally from several 100 [nm/min] to several [μm/min]), the etching depth is set to 10% in the middle of the layer.
It is generally impossible to control it to below [nm] level. Furthermore, in such a gas system, contamination of the semiconductor substrate surface by chlorine or fluoride often becomes a problem. On the other hand, although the plasma etching method using H ₂ gas is considered to have less influence of surface contamination, it is extremely difficult to control the etching depth to the above degree. Moreover, as mentioned above, this method is isotropic, and the controllability of the pattern shape is not good.

(d) Purpose of the Invention In order to address the above-mentioned problems, the present invention makes it possible to control the etching depth and accuracy to about 10 [nm] or less for compound semiconductors containing gallium (Ga) or arsenic (As). The purpose of this invention is to provide an etching method.

(e) Structure of the Invention The above object of the present invention is achieved by etching a compound semiconductor layer containing at least gallium or arsenic by a reactive ion etching method using ionized hydrogen atoms.

In other words, in the plasma etching method using H ₂ gas mentioned above, the etching rate is too high for the purpose of the present invention because of the high concentration of excited neutral hydrogen atoms in the plasma as the etching species. On the other hand, in the reactive ion etching method of the present invention, ionized hydrogen atoms, which have a much lower concentration than neutral hydrogen atoms in plasma, are made to enter a semiconductor substrate to be processed placed on an electrode. Since etching is performed using the sputtering effect in the direction of incidence and the chemical reaction caused by hydrogen ions, the etching speed is slow, making it possible to precisely control the etching depth and achieving extremely high precision in pattern shape. becomes.

The present invention can be practiced using a conventional reactive ion etching apparatus such as that illustrated in FIG. Electrodes 2 and 3 are provided vertically facing each other in the etching chamber 1, and gas is supplied to the air pipe 4.
and is introduced and discharged through the exhaust pipe 5. The lower electrode 2 is supported by an insulator 6, and high frequency power is applied between it and the upper counter electrode 3, whereby plasma 7 is formed between both electrodes except in the vicinity of the electrode 2. be done. The semiconductor substrate 8 to be processed is connected to the electrode 2
The above-mentioned reactive ion etching is performed by placing it on top.

Figure 2 shows the etching method of the present invention.
FIG. 3 is a diagram showing an example of the correlation between etching rate and hydrogen gas pressure when etching is performed on a GaAs semiconductor layer and an aluminum arsenide/gallium/(AlxGa1-xAs) semiconductor layer. However, in this example, the plasma frequency is 13.56 [MHZ], and the power density is 5×
10 ^-2 [W/cm ^-3 ] Generated by an electromagnetic field.
In the figure, curve A is a GaAs semiconductor layer, and curve B is a GaAs semiconductor layer.
The case of an AlxGa1−xAs (x=0.3) semiconductor layer is shown.

In Fig. 2, curves A and B both show maximum values near the hydrogen gas pressure of 5 [Pa], and the etching rates at that time are 4 [nm/min] and 3 [nm/min].
It is about [nm/min]. At this maximum hydrogen gas pressure, the ratio of ionized hydrogen atoms in the plasma becomes maximum, and the etching system becomes most stable. Note that when the hydrogen gas pressure is about 1 [Pa] or less or about 50 [Pa] or more, no plasma state is generated.

In this way, for example, by achieving an etching rate of about 4 [nm/min] with high stability, it becomes possible to easily control the etching depth with an accuracy of 10 [nm] or less. .

(f) Embodiments of the invention Examples of the invention will be specifically described below with reference to the drawings.

FIGS. 3a to 3c are cross-sectional views showing an example in which the present invention is implemented in the manufacturing process of a hetero-operated FET. Third
See figure a. On the semi-insulating GaAs substrate 11, a non-doped
GaAs12 to a thickness of about 300 [nm], for example,
N-type Al0.3Ga0.7As13 doped with silicon (Si) to, for example, about 1×10 ¹³ [cm ^-3 ] is
The n-type AlxGa1-xAs layer 14, in which the Al composition ratio x gradually decreases from 0.3 to 0, has a thickness of about 20 [nm], and the n-type GaAs layer 15 has a thickness of, for example, 40 [nm]. ] by molecular beam epitaxial growth method or the like. A two-dimensional electron gas 16 is formed near the heterojunction interface between the non-doped GaAs layer 2 and the n-type Al0.3Ga0.7As layer 13.

Next, source electrodes 17 and 17' and drain electrodes 18 and 18' are formed using, for example, gold-germanium/gold (AuGe/Au), and heat-treated to alloy with the n-type GaAs layer 15 and the like. The low resistance ohmic connection region 19
is formed. Further, the element isolation region 20 is formed by, for example, ion implantation of oxygen (O ₂ ). See Figure 3b. For the purpose of controlling the gate threshold voltage,
Selective etching is performed on the gate region of GaAs layer 15 using a mask. In this example,
For example, by providing a mask 21 with a silicon dioxide (SiO ₂ ) film, the depletion mode FET
According to the present invention, the gate region 22 of the enhancement mode FET is etched to a depth of about 10 [nm], and _the gate region 23 of the enhancement mode FET is etched to a depth of about 30 [nm]. The test was carried out under conditions of approximately 4×10 ^-2 [W/cm ³ ].

For example, if the high frequency power is doubled, the etching speed will be approximately 1.5 times. Etching speed is also controlled by the high frequency power, but if the power is too low, plasma will not be formed stably, and if the power is too high, the etching speed will be approximately 1.5 times. In order to cause strong damage to the semiconductor substrate to be processed, the high frequency power density is 1×10 ^-2 to 4×10 ^-1.
The optimum value is selected within a range of approximately [W/cm ^- ₃ ], taking into consideration the above factors. Furthermore, by adding an inert gas to the H ₂ gas, the degree of freedom in controlling plasma formation, etching rate, etc. is expanded. In the present invention, whose main object is a semiconductor substrate to be processed, it is particularly important not to damage the semiconductor substrate to be processed by the sputtering effect. Referring to FIG. 3c, gate electrodes 24 and 24' are formed of, for example, aluminum (Al) on the etched surface of the gate region.

The gate threshold voltage of this example is approximately -0.5 [V] for the depletion mode FET and approximately 0 [V] for the enhancement mode FET, and the distribution between elements and within the plane is significantly larger than that of the conventional one. has been improved.

The above explanation and examples are used as semiconductor materials.
Although reference is made to GaAs and AlGaAs, the present invention provides for example gallium antimony (GaSb).
Similar effects can be obtained with compound semiconductors containing gallium or arsenic, such as gallium-phosphorus (GaP), indium-arsenic (InAs), or gallium-indium-arsenic (GaInAs).

Effect (g) As explained above, according to the present invention, when etching a compound semiconductor layer containing gallium or arsenic, the depth can be easily controlled to an accuracy of about 10 [nm] or less, and the etching depth can be easily controlled to an accuracy of about 10 [nm] or less. The uniformity is good, and the pattern accuracy is also excellent, which greatly contributes to the industrial implementation of quantum-theoretical dimensions required for, for example, heterojunction FETs.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing an example of an etching apparatus used to carry out the present invention, FIG. 2 is a diagram showing an example of the correlation between etching rate and hydrogen gas pressure, and FIGS. 3 a to 3 c are examples of the present invention. FIG. In the figure, 11 is a GaAs substrate, 12 is a non-doped GaAs layer, 13 is an n-type AlGaAs layer, 14 is an n-type graded AlGaAs layer, and 15 is an n-type GaAs layer.
layer, 16 is a two-dimensional electron gas, 17 and 17' are source electrodes, 18 and 18' are drain electrodes, 19
20 is an ohmic connection region, 20 is an inter-element isolation region,
21 is a mask, 22 and 23 are gate regions, 24
and 24' indicate a gate electrode.

Claims (1)

Claims: 1. A method for manufacturing a semiconductor device, comprising the step of etching a compound semiconductor layer containing at least gallium or arsenic by a reactive ion etching method using ionized hydrogen atoms. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the compound semiconductor is at least one of gallium arsenide and aluminum arsenide.