JPH0458697B2 - - Google Patents
Info
- Publication number
- JPH0458697B2 JPH0458697B2 JP58030297A JP3029783A JPH0458697B2 JP H0458697 B2 JPH0458697 B2 JP H0458697B2 JP 58030297 A JP58030297 A JP 58030297A JP 3029783 A JP3029783 A JP 3029783A JP H0458697 B2 JPH0458697 B2 JP H0458697B2
- Authority
- JP
- Japan
- Prior art keywords
- well
- terminal
- semiconductor
- terminals
- diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
- H10D89/911—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using passive elements as protective elements
Landscapes
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の構造、特に対静電気破壊
防止を強化した構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a semiconductor device, and particularly to a structure with enhanced protection against electrostatic damage.
従来、静電気破壊を防止する構造としては例え
ば相補型MOS集積回路内における入力。および
出力に対する保護ダイオード構造において、同一
のＰウエル上に２つの端子を有し、その夫々に保
護ダイオードが隣接して設けられている場合、第
１図の様にある一定の距離Ｌを維持して配列され
ている。その断面（Ａ−A′断面）は、第２図の
様になり、端子（通常ボンデイングパツト）１と
端子２にそれぞれ接続されたダイオードは、各電
位に対する保護ダイオードの働きをする。この場
合の等価回路は第３図の様になる。この図より、
例えば、端子１に正電位、端子２に負電位の静電
気が印加されたと仮定すると、電流経路はダイオ
ード１６（逆方向）、Ｐウエル抵抗rp、ダイオー
ド１７（順方向）の順に通過する。従つて一般的
には逆方向に働らいているダイオード１６（第１
図におけるＮジヤクシヨン３とＰウエル７間）で
破壊が起る。即ち、同一のＰウエルの中に隣接す
る端子１と端子２との各保護ダイオードが形成さ
れているため、両者はＰウエルの抵抗rpを介して
電気的に接続され、しかも直列抵抗rpが一般的に
小さいため、二端子間における電流制限の働きが
出来なくなることが破壊を生じる大きな原因にな
つている。そこで、破壊強度を強くするためにＰ
ウエルの直列抵抗rpを大きくすることが考えられ
る。つまり、二端子間のＰウエルの距離Ｌを長く
すれば良い。しかし、ここで重要なことは高密度
素子集積回路においては、レイアウトパターンを
大きくできないという制限が伴う。 Conventionally, structures for preventing electrostatic damage include, for example, inputs within complementary MOS integrated circuits. In the protection diode structure for output and output, if there are two terminals on the same P-well and a protection diode is provided adjacent to each terminal, a certain distance L must be maintained as shown in Figure 1. are arranged. Its cross section (A-A' cross section) is as shown in FIG. 2, and the diodes connected to terminals (usually bonding pads) 1 and 2 act as protection diodes for each potential. The equivalent circuit in this case is as shown in FIG. From this figure,
For example, assuming that static electricity with a positive potential is applied to terminal 1 and a negative potential is applied to terminal 2, the current path passes through diode 16 (reverse direction), P well resistor r p , and diode 17 (forward direction) in this order. Therefore, generally the diode 16 (first
Destruction occurs between the N-judge 3 and the P-well 7 in the figure. That is, since the respective protection diodes for adjacent terminals 1 and 2 are formed in the same P well, they are electrically connected via the resistance r p of the P well, and the series resistance r p is generally small, and the inability to limit the current between the two terminals is a major cause of destruction. Therefore, in order to increase the breaking strength, P
It is conceivable to increase the series resistance r p of the well. In other words, it is sufficient to increase the distance L of the P-well between the two terminals. However, what is important here is that high-density element integrated circuits are limited in that the layout pattern cannot be made large.
本発明の目的は隣接する二端子間の新規な対静
電気強化構造を提供することにある。 An object of the present invention is to provide a novel antistatic reinforcement structure between two adjacent terminals.
本発明は、隣接する同一導電型の半導体領域か
ら延在された隣接する二端子の各保護ダイオード
の最短距離の間に異なる導電型の半導体領域を介
在させることによつて、ウエル領域にあつてはそ
のウエルを保護ダイオード部２分することによ
り、電流制限効果を向上させた半導体装置を提供
するものである。 The present invention provides a well region with a semiconductor region of a different conductivity type interposed between the shortest distance of each protection diode of two adjacent terminals extending from an adjacent semiconductor region of the same conductivity type. The present invention provides a semiconductor device in which the current limiting effect is improved by dividing the well into two protective diode portions.
本発明について、図面を参照しながらその一実
施例を詳細に説明する。 An embodiment of the present invention will be described in detail with reference to the drawings.
第４図において、端子１と端子２のＰウエル側
の保護ダイオード３，４は、同一電位であるが、
図の様に二端子間のＰウエルの中央を分離するこ
とにより端子１と端子２との最短電流経路は、途
中で一旦ウエルを抜け出し、基板８（距離１）を
通過するため、同一ウエル上のみを通過するより
も、経路上の内部直列抵抗を著しく高めることが
でき、電流制限効果を向上させることができる。
また、電流経路の断面（Ｂ−B′断面）を考える
と、第５図の様になり、断面図上Ｐウエルが完全
に分離した形となる。その等価回路は、第６図の
様になる。例えば、端子１を正電位、端子２を負
電位に静電気を印加した場合ダイオード２１が逆
方向となり、等価的に高い直列抵抗が入つた事に
なり、静電気印加を逆にした場合はダイオード２
０が同様に等価的に高直列抵抗が入つた事にな
る。よつて、両二端子間の静電印加に対して大き
な電流制限の効果が得られる。なお、この構造は
一般の半導体装置にも同様に適用できる。 In FIG. 4, protection diodes 3 and 4 on the P-well side of terminals 1 and 2 are at the same potential, but
As shown in the figure, by separating the center of the P-well between two terminals, the shortest current path between terminals 1 and 2 will pass through the well and pass through the substrate 8 (distance 1), so The internal series resistance on the path can be significantly increased, and the current limiting effect can be improved.
Further, when considering the cross section of the current path (B-B' cross section), it becomes as shown in FIG. 5, and the P-well is completely separated in the cross-sectional view. The equivalent circuit is shown in FIG. For example, if static electricity is applied with terminal 1 at a positive potential and terminal 2 at a negative potential, diode 21 will be in the opposite direction, and a high series resistance will be introduced equivalently.
0 is equivalent to a high series resistance. Therefore, a large current limiting effect can be obtained with respect to static electricity applied between the two terminals. Note that this structure can be similarly applied to general semiconductor devices.
第１図は従来の装置の平面図、第２図はそのＡ
−A′断面図、第３図は端子１，２から見た等価
回路、第４図は本発明の一実施例の平面図、第５
図はそのＢ−B′断面図、第６図は、その端子１，
２から見た等価回路である。
１，２……端子、３，４，１２，１４……Ｐウ
エル上におけるダイオード、５，６……コンタク
ト、７，１３……Ｐウエル、８，１５……基板、
９……端子１側のアルミ配線、１０……端子２側
のアルミ配線、１６……端子１側のダイオード、
１７……端子２側のダイオード、rp……端子１、
２間のＰウエル抵抗、１８，１９……分離された
Ｐウエル、２０，２１……分離されたＰウエルと
基板のダイオード。
Figure 1 is a plan view of the conventional device, and Figure 2 is its A.
-A' sectional view, Fig. 3 is an equivalent circuit seen from terminals 1 and 2, Fig. 4 is a plan view of an embodiment of the present invention, Fig. 5
The figure is a BB' cross-sectional view, and Figure 6 is the terminal 1,
This is an equivalent circuit seen from 2. 1, 2... terminal, 3, 4, 12, 14... diode on P well, 5, 6... contact, 7, 13... P well, 8, 15... substrate,
9...Aluminum wiring on the terminal 1 side, 10...Aluminum wiring on the terminal 2 side, 16...Diode on the terminal 1 side,
17...Diode on terminal 2 side, r p ...terminal 1,
P-well resistance between 2, 18, 19...separated P-well, 20, 21... diode between separated P-well and substrate.
Claims (1)
けられた他の導電型の第１の半導体層と、表面が
該第１の半導体層の表面に露出し底面が前記半導
体基板と接続して連続する前記第１の半導体層に
少くとも３辺が囲まれるように設けられた前記一
導電型の第２の半導体層と、該第２の半導体層の
両側の前記第１の半導体層に設けられた前記一導
電型の第３及び第４の半導体層と、前記第３及び
第４の半導体層にそれぞれ接続して設けられた第
１及び第２の引出し端子とを有することを特徴と
する半導体装置。1 A semiconductor substrate of one conductivity type, a first semiconductor layer of another conductivity type provided on the semiconductor substrate, a surface of which is exposed to the surface of the first semiconductor layer, and a bottom surface of which is connected to the semiconductor substrate. a second semiconductor layer of one conductivity type provided so as to be surrounded on at least three sides by the continuous first semiconductor layer; and a second semiconductor layer provided in the first semiconductor layer on both sides of the second semiconductor layer. the third and fourth semiconductor layers of one conductivity type, and first and second lead-out terminals connected to the third and fourth semiconductor layers, respectively. Semiconductor equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58030297A JPS59155952A (en) | 1983-02-25 | 1983-02-25 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58030297A JPS59155952A (en) | 1983-02-25 | 1983-02-25 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59155952A JPS59155952A (en) | 1984-09-05 |
| JPH0458697B2 true JPH0458697B2 (en) | 1992-09-18 |
Family
ID=12299797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58030297A Granted JPS59155952A (en) | 1983-02-25 | 1983-02-25 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59155952A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5728171B2 (en) | 2009-06-29 | 2015-06-03 | 株式会社半導体エネルギー研究所 | Semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4405933A (en) * | 1981-02-04 | 1983-09-20 | Rca Corporation | Protective integrated circuit device utilizing back-to-back zener diodes |
-
1983
- 1983-02-25 JP JP58030297A patent/JPS59155952A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59155952A (en) | 1984-09-05 |
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