JPH0459652B2 - - Google Patents

Description

[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention provides a data processing device intended to simplify and speed up data processing by reducing the number of processing steps when a data processing unit performs calculations. Regarding.

(2) Prior Art and Problems A conventional example of a data processing device, particularly a data processing device that performs a convolution operation, will be explained with reference to FIG. In Figure 1, ADR is an address register, sequence ROM is a ROM that stores data processing procedures in the form of a microprogram, IGM is a memory device for generating instructions, DEC is a decoder, IDR is an index register, and data ROM is a ROM that stores data processing procedures in the form of a microprogram. Data for arithmetic processing, such as coefficient data in discrete Fourier transform (DFT) processing, DFT order, data RAM
The data RAM stores fixed data such as storage addresses, the data RAM stores calculation data (variables), the APR is the calculation processing unit, and in this case, the flag register FR, which is formed by flip-flops, and the accumulator ACC. Equipped with etc. SEL indicates conditional branch information selector,
The outputs of the flag register FR and the like in the arithmetic processing unit APR are applied to the selector SEL, which selects the value of the address register ADR and performs a branch operation.

At the beginning of processing, the index register IDR is specified by the instruction generation memory device IGM to obtain the initial address value for reading the data ROM, pointing to the address of the data RAM where the data to be read is initially stored. be done.

Next, the data is transferred via the address of the data ROM by addressing the index register IDR.
Reads specific data from RAM and performs arithmetic processing
Apply to APR. In addition, the index register
IDR is set to data ROM/RAM depending on its address value.
It is also possible to access each individually.

The arithmetic processing unit APR generates data based on the instruction data read from the instruction generation memory device IGM and decoded by the decoder DEC.
Performs arithmetic processing on data read from RAM. When fast Fourier transform (FET), discrete Fourier transform (DFT), correlation calculation, etc. are performed as arithmetic processing, addresses within a certain range in the data ROM, that is, data within a certain range may be used cyclically. In the case of discrete Fourier transform (DFT), the general formula is given by F _K = _N-1 〓 ⁿ⁼⁰ f _o W ^nk , where F _k is the output sequence, f _o is the input sequence, and W ^nk is Indicates twist factor. Here, since W=e ^-j(2 〓 ^/N) n, k=0 to (N-1), W ^nk cycles every nk=N. That is, the value raised to the power of e goes from 0 to 2π, and then repeats from 0 to 2π again.

In area M of the data ROM, W ⁰ to W ^N-1 of the values of W ^nk in the above-mentioned discrete Fourier transform equation are stored at addresses 1 to N (N<M). Then, while obtaining an address by sequentially increasing the values of n and k from 0 to (N-1), the data ROM at that address is read out and applied to the arithmetic processing unit APR. Since the data stored in the data ROM is a series, if the address in the ROM is n=1, the ROM address will simply increase by 1, but if n=2, the ROM address will be intermittently. If n becomes even larger, a huge number of ROM addresses will be specified. Actually
Since the capacity of ROM is limited, it is necessary to circulate within a certain range. For example, when giving the values of n and k such as n=5, k=5, the setting address is
Determining whether or not the ROM address limit value is exceeded is performed as a process by the arithmetic processing unit APR. For example, the arithmetic processing unit APR is provided with several registers, the values of n and k are stored in two registers R1 and R2, the order of the Fourier series is stored in another register R3, and the calculation results for the values of n and k are stored in two registers R1 and R2. When inputting data into another register R4, it would be fine to subtract the value of register R3 from the value (n x k) of other register R4 and get a negative value, but (because the ROM address of the operation result is within the normally used area, there is a problem) However, the subtracted value is not necessarily negative and may be positive. In that case, it will exceed the ROM area, so
It is necessary to perform another operation such as a modulo operation in the arithmetic processing unit APR to obtain a new address. In this way, extra processing was required for the ROM address, including ○ data, ○ calculation, ○ positive/negative determination, and ○ appropriate setting of the new address. When arithmetic processing is required to obtain a new address, the arithmetic processing unit APR sets the flag register FR to, for example, "1" and instructs the selector SEL to perform a conditional branch. The processing of the arithmetic processing unit AP at this time is an operation different from the original data processing, and the operation involves a large number of steps, making control complicated and easily causing delays.

(3) Purpose of the Invention The purpose of the present invention is to improve the above-mentioned drawbacks, and to solve the problem of a branch condition when the state of a predetermined bit of an index register that processes an address given to a data storage device is reversed from the initial state. Get,
It is an object of the present invention to provide a data processing device capable of reducing processing in an arithmetic processing unit, reducing the number of control steps, and speeding up data processing.

(4) Structure of the invention In order to achieve the above object, the present invention has the following structure. That is, an instruction generation memory device that stores microinstructions to be supplied to the arithmetic processing unit and data for generating a data storage device read address to be supplied to the index register; An index having an arithmetic unit that performs an operation to obtain a new address by adding an update amount to the initial value based on an initial value and an update amount, and a register that stores the result of the operation and supplies it as an address to a data storage device. A data storage device that stores data used for arithmetic processing in a predetermined area thereof, and data read from the data storage device, and by instruction data read from the instruction generation storage device. An arithmetic processing unit that performs arithmetic processing, a selector to which a branch condition is given based on the processing result of the arithmetic processing unit, and an address is supplied to the instruction generation storage device whose contents are controlled by the output of the selector. In a data processing device configured with an address register, the predetermined area in the data storage device is set so that its highest address is 2 ⁿ −1 (n is an integer), and the calculation result in the index register is A connecting line is provided to directly connect the n-th bit of the register storing the processing result to the branch condition input of the selector to which the branch condition based on the processing result of the arithmetic processing section is given.

(5) Embodiment of the Invention FIG. 2 is a block diagram showing an embodiment of the present invention, and the same reference numerals as in FIG. 1 indicate the same parts. In Figure 2, CL indicates a connection line, which is derived from the bit one bit higher than the number of bits of the address applied to the data ROM of the register that stores the operation result in the index register IDR, and is connected to the selector SEL. are doing.

The operation shown in FIG. 2 will be explained below, taking as an example the calculation of discrete Fourier variables. In the area M of the data ROM, W ^nk in the above-mentioned discrete Fourier transform equation is
Of the values, W ⁰ to ^{W N-1} are assigned to addresses 0 to (N-1)
(N<M). Then, while obtaining an address by sequentially increasing each value of n and k from 0 to (N-1), the ROM at that address is read out and applied to the arithmetic processing unit APR.

Arithmetic processing can be written as i=(n・k)modN by setting W ^nk = W ⁱ , so if k=0 to 3, n=0 to 3, n=0 W ⁰ , W ⁰ , W ⁰ , W ⁰ n=1 W ⁰ , W ¹ , W ² , W ³ n=2 W ⁰ , W ² , W ⁰ , W ² (This should be W ⁰ , W ² , W ⁴ , W ⁶ (nk) is calculated using modN, so it cycles as above) n = 3 W ⁰ , W ³ , W ² , W ¹ (also W ⁰ , W ³ , W ⁶ , W ⁹ For example, the index register is determined to have a 3-bit configuration based on the capacity and address of the data ROM. The ROM stores data from address 0 to n·k=N-1 in the above equation.
When performing the above calculation with n·k=0 to 3, the calculation result may exceed the address upper limit value depending on the initial value and the added value. To determine whether or not the value is exceeded, we look at the most significant bit of the index register (i.e., the 3rd bit in this case), and find that the initial state is "0" and that it remains "0" during the operation. At this time, it can be determined that the ROM area has not been exceeded. If the most significant bit of the operation result changes from "0" to "1", then the address specification is outside the ROM area, so select the inverted data in the 3-bit register. If the signal is transmitted to the device SEL, it can be determined that a state change has occurred. Therefore, by performing a modulo operation on the index register IDR,
A branch operation is performed by the selector SEL so as to specify an address within the ROM area.

The selector SEL uses this bit inversion information to sequence a new address by, for example, changing the page to be used in the address register ADR.
Can be given to ROM.

(6) Effects of the Invention As described above, according to the present invention, the arithmetic processing section does not need to perform arithmetic operations for address processing for the data storage device, so it is sufficient to use operation steps for data processing. In other words, since it performs the original operation for data processing,
This is effective because the operation program of the arithmetic processing section is simplified and the data processing operation is sped up.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a conventional data processing device, and FIG. 2 is a diagram showing the configuration of an embodiment of the present invention. ADR...address register, SEL...conditional branch information selector, APR...arithmetic processing unit, IDR...
Index register, CL...connection line, IGM...
...Storage device for command generation.

Claims (1)

[Scope of Claims] 1. A memory device for generating instructions that stores microinstructions to be supplied to an arithmetic processing unit and data for generating a data storage device read address to be supplied to an index register; an arithmetic unit that performs an operation to obtain a new address by adding the update amount to the initial value based on the initial value and update amount supplied from the storage device, and stores the operation result that is supplied as an address to the data storage device an index register having a register; a data storage device that stores data used in arithmetic processing in a predetermined area; and a data storage device that uses the data read from the data storage device to read from the instruction generation storage device. an arithmetic processing section that performs arithmetic processing based on the instruction data that has been issued; a selector that is given a branch condition based on the processing result of the arithmetic processing section; an address register for supplying an address; and a data processing device, wherein the predetermined area in the data storage device is set so that its highest address is 2 ⁿ −1 (n is an integer), and the index Data characterized in that a connection line is provided that directly connects the n-th bit of the register that stores the operation result in the operation processing section to the branch condition input of the selector that is given the branch condition based on the processing result of the operation processing section. Processing equipment.